Investigations of Tunneling for Field Effect Transistors

by

Peter Matheu

A dissertation submitted in partial satisfaction of the

requirements for the degree of
Doctor of Philosophy

in

Applied Science & Technology

in the

Graduate Division

of the

University of California, Berkeley

Committee in charge:

Professor Tsu-Jae King Liu, Chair

Professor Sayeef Salahuddin, Member AS&T
Professor Chenming Hu, Outside Member

Spring 2012
Investigations of Tunneling for Field Effect Transistors

Copyright 2012
by
Peter Matheu
 1

Abstract

Investigations of Tunneling for Field Effect Transistors

by
Peter Matheu
Doctor of Philosophy in Applied Science & Technology
University of California, Berkeley
Professor Tsu-Jae King Liu, Chair

Over 40 years of scaling dimensions for new and continuing product cycles has introduced
new challenges for transistor design. As the end of the technology roadmap for semiconduc-
tors approaches, new device structures are being investigated as possible replacements for
traditional metal-oxide-semiconductor field effect transistors (MOSFETs). Band-to-band
tunneling (BTBT) in semiconductors, often viewed as an adverse effect of short channel
lengths in MOSFETs, has been discussed as a promising current injection mechanism to
allow for reduced operating voltage for beyond MOSFET technology.
This dissertation discusses the proposal of BTBT for tunneling field effect transistors
(TFETs). Some early work is briefly reviewed to better appreciate the academic re-
search landscape regarding BTBT. Then, experimental observations of a steeply switching
enhanced-Schottky-barrier MOSFET are analysed in detail and the steep characteristic is
plausibly explained by metal impurity trap states near the source tunneling junction. Next,
follow-up experiments to investigate the role of traps in BTBT are reviewed with a likely
explanation that traps in close proximity to the tunneling junction can lower the activation
energy for BTBT. Finally, a source design study for a planar homojunction germanium-on-
insulator TFET finds that a static reverse bias can dramatically alter the optimal doping
profile for the source tunneling junction and highlights the importance of tight electrostatic
control for improved ION /IOFF in TFETs.
 i

To my family and friends.

For their continual support throughout my graduate school odyssey, most especially my
parents and my siblings for their limitless patience and understanding.
 ii

Contents

Contents ii

List of Figures iv

List of Tables vi

1 Introduction 1
1.1 CMOS Solid State Switching Devices . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Proposed Alternatives to CMOS-based Logic . . . . . . . . . . . . . . . . . . 2
1.3 Tunneling Field Effect Transistors: Basic Design and Operation . . . . . . . 4
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Bibliography 7

2 Enhanced Schottky Barrier MOSFET with Steep Subthreshold Swing at

Low Current 9
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Silicide/Silicon Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Modified Designs for Band-to-Band Tunneling . . . . . . . . . . . . . . . . . 13
2.4 Device Characterization and Discussion . . . . . . . . . . . . . . . . . . . . . 15
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Bibliography 26

3 Engineered Electronic Trap States in Tunneling Diodes 29

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2 Impurity Selection for Electronic Trap State . . . . . . . . . . . . . . . . . . 31
3.3 Experimental Design Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4 Diode I-V Characteristics and Temperature Dependence . . . . . . . . . . . 36
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Bibliography 43
 iii

4 Erbium Trap Assisted TFET 45

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2 Experimental Design Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3 Electrical Characterization and Temperature Dependence . . . . . . . . . . . 47
4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Bibliography 55

5 Design Optimization of Homojunction TFETs with Back Biasing 56

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.2 Simulation Structure to Investigate Lower Eg Materials for Planar Homojunc-
tion TFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3 Planar GeOI TFET Performance Enhancement via Back Bias . . . . . . . . 60
5.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Bibliography 70

6 Conclusion 72
6.1 Summary of Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.2 TFET Design Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Bibliography 75

A Appendix: Process Flow Template 76

 iv

List of Figures

1.1 MOSFET Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 MOSFET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 MOSFET I-V Alternative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 SB-MOSFET Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 SB Band Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 SB MOSFET Band Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 SB TFET Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Fabricated SB TFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6 Pocket SB-MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7 Enhanced SB-MOSFET Initial Transfer Characteristics . . . . . . . . . . . . . . 17
2.8 Enhanced SB-MOSFET Transfer Characteristics . . . . . . . . . . . . . . . . . . 18
2.9 Enhanced SB-MOSFET Activation Energy . . . . . . . . . . . . . . . . . . . . . 19
2.10 Enhanced SB-MOSFET Band Diagram . . . . . . . . . . . . . . . . . . . . . . . 20
2.11 Enhanced SB-MOSFET SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.12 Enhanced SB-MOSFET I-V (VB ) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.13 Enhanced SB-MOSFET SS(VB . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.14 Enhanced SB-MOSFET Output Characteristics . . . . . . . . . . . . . . . . . . 23
2.15 Enhanced SB-MOSFET Output Characteristics . . . . . . . . . . . . . . . . . . 24

3.1 Esaki Diode Band Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2 Trap Assisted Tunneling Models . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3 Trap Assisted Tunneling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4 Erbium Heterodiode Splits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.5 Erbium Ion Implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6 Phosphorus n-well Split . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.7 p-i-n Heterodiode I-V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.8 p-i-n Heterodiode dI/dV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.9 Heterodiode EA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.10 p+/n+ Heterodiode I-V(T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11 p+/n+ Heterodiode Band Alignment . . . . . . . . . . . . . . . . . . . . . . . . 41
3.12 p+/n+ Heterodiode EA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
 v

4.1 Er TATFET Cross-sectional Schematic . . . . . . . . . . . . . . . . . . . . . . . 45

4.2 Er TATFET Band Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3 Typical Transfer Characteristics for Er-TATFETs . . . . . . . . . . . . . . . . . 48
4.4 Typical Transfer Characteristics for Control TFETs . . . . . . . . . . . . . . . . 48
4.5 Temperature Dependent Transfer Characteristics for an Er-TATFET . . . . . . 49
4.6 Temperature Dependent Transfer Characteristics for a p-i-n Control TFET . . . 49
4.7 SS for an Er-TATFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.8 SS for a Control TFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.9 EA for p-i-n Control TFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.10 Activation Energy for Er-TATFETs . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.11 Thought Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.1 Simulated SOI TFET Transfer Characteristics . . . . . . . . . . . . . . . . . . . 57

5.2 Simulated SOI TFET ION /IOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3 Enhanced SOI TFET Transfer Characteristics . . . . . . . . . . . . . . . . . . . 59
5.4 GeOI Optimal Source Parameters for ION /IOFF . . . . . . . . . . . . . . . . . . 61
5.5 Simulated GeOI ION /IOFF (VB ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.6 Simulated GeOI BTBT Contours . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.7 GeOI Transfer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.8 GeOI TFET with LG Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.9 GeOI TFET Drain Induced Barrier Effects . . . . . . . . . . . . . . . . . . . . . 66
5.10 GeOI TFET Source Design Overlap Comparison . . . . . . . . . . . . . . . . . . 67
5.11 Simulated GeOI TFET Output Characteristics . . . . . . . . . . . . . . . . . . 68
5.12 GeOI TFET Ge Body Thickness Dependence . . . . . . . . . . . . . . . . . . . 68
 vi

List of Tables

3.1 Experimental heterodiode splits and rectifying device yield. . . . . . . . . . . . . 36

4.1 Transistor dimensions for control and experimental devices. . . . . . . . . . . . . 50

 vii

Acknowledgments
I would like to acknowledge the support of my colleagues throughout my graduate academic
career. My first advisor, Professor Edward T. Yu, was instrumental in guiding me in my
early days as a researcher. His patience and keen eye towards analyzing my work will always
be appreciated. I learned a great deal about research and the scientific method through my
work with him and the other graduate students in his group, namely Daniel Derkacs, Swee-
Hoe Lim, Jeremy Law, Hongtao Zhang, and Sourobh Raychaudhuri. Professor Peter Asbeck,
Professor Yu-Hwa Lo, and Professor Yu’s unyielding support no doubt greatly improved my
candidacy to pursue a doctoral degree at the University of California, Berkeley.
After arriving at Cal, my current advisor, Professor Tsu-Jae King Liu, guided me through
the competitive atmosphere of top tier academic research with unwavering patience. I sin-
cerely thank Professor King Liu for seeing a greater potential in what I could accomplish
than I at first saw in myself. While I have learned a lot about semiconductor device physics
in the classroom and the lab, Professor King brings intangible qualities to my education
that I now count as more valuable than the sum of all of my academic work. Her exemplary
advising and management truly sets an uncompromising tone for the pursuit of research ex-
cellence. I am in her debt and truly appreciative of the opportunity to work in her research
group here at Berkeley.
Additionally, I am grateful to Professors Chenming Hu and Sayeef Salahuddin for their
help in designing my experiments, interpreting results, and for greatly enriching my ex-
perience at Berkeley. I would also like to thank Professors Ming Wu, Junqiao Wu, David
Attwood, and Eugene Haller for participating as preliminary and qualifying exam committee
members.
While I often strive for a high degree of self-reliance as a Ph.D. candidate, this disser-
tation would not be possible without the help and advice of so many others. For process
calibration, design, and troubleshooting in the Berkeley Microlab and Nanolab, the following
individuals extended a helping hand beyond expectations: Sia Parsa, Jimmy G. M. Chang,
Kim Chan, Joe Donnelly, Brian McNeil, Bob Hamilton, Jay Morford, and Danny Pestal. To
my colleagues for their help with training, experiments, and discussions: Joanna Lai, Dono-
van Lee, Changhwan Shin, Byron Ho, Zachery Jacobson, Sung-Hwan Kim, Vincent Pott,
Louis Hutin, Jaeseok Jeon, Xin Sun, Nattapol Damrongplasit, Nuo Xu, Eung Seok Park,
Sapan Argawal, Pratik Patel, Anupama Bowonder, and Kanghoon Jeon. Others for their
help in troubleshooting equipment (and my sanity) in the lab: Patrick Bennett, Roger Chen,
Amit Lakhani, Jodi Iwata, Jack Yaung, Philip Chen, Adrienne Higa, Stevan Djordjevic, Lee
Fok, Jason Valentine, Erick Ulin-Avila, Guy Bartal, Christopher Rhodes, and Nathan Emley.
Lastly, I have to thank a few friends I have made along the way whose guidance was
greatly appreciated (whether they would admit to mentoring me or not): Dr. David F. P.
Pile, Prof. Rupert Oulton, Dr. David Hammond, Dr. Muralidhar Ambati, Prof. Geoffroy
Lerosey, Dr. Ze’ev Abrams, and Christopher Gladden.
 1

Chapter 1

Introduction

1.1 CMOS Solid State Switching Devices

The continued improvement of metal-oxide-semiconductor field effect transistor (MOSFET)
performance is due in large part to the scalability of semiconductor manufacturing and
demand driven new-product cycles. A simple description of a MOSFET is as follows: with a
bias applied between the source and the drain, the gate electrode can dramatically alter the
resistance of the channel by capacitively coupling to the semiconductor region immediately
below the gate. A schematic cross-section of a MOSFET is presented in Fig. 1.1. The gate
capacitively couples to the silicon (Si) substrate and controls a source side energy barrier,
modulating the current flowing from the source to the drain (see Fig. 1.2).

Figure 1.1: A schematic cross-section of a typical MOSFET. Historically, scaling down the printed gate
length improved ION . MOSFET design requires a balance between the separation distance between the
source and drain doping profiles and the operating voltage of the device. The cut-line AA’ approximately
references the location of the channel for the band diagram in Fig. 1.2

Scaling, or reducing key physical dimensions of the transistor structure, has regularly
CHAPTER 1. INTRODUCTION 2

improved device performance and density for over 40 years. With decreasing critical dimen-
sions and increasing device density, new design challenges are continually addressed to meet
the demand in a growing market for electronics. An important concern raised in literature
(e.g., reference [1]) is that an increase in the passive power density for current MOSFET
technology is unavoidable with continued scaling. Various alternative devices have been
proposed to replace or complement MOSFETs and all are designed to maintain or improve
performance while reducing the off-state power consumption.

Figure 1.2: A band diagram for the MOSFET from the AA’ cutline in Fig. 1.1. The off-state (black lines)
presents a source side energy barrier to prevent carriers from entering the channel. In the on state (green
dotted lines), the barrier is lowered and carriers move from the source to the drain.

1.2 Proposed Alternatives to CMOS-based Logic

A lower limit for the switching efficiency of a MOSFET relates the strength of the capac-
itive coupling of the gate to the distribution of mobile charge carriers in the source. For
MOSFETs, the distribution of carriers in the source is sometimes referred to as a Boltzmann
distribution in energy peaking near the conduction (valence) band edge for an n-channel (a
CHAPTER 1. INTRODUCTION 3

p-channel) device.[2] A metric for the efficiency of gate coupling to the channel is the inverse
subthreshold slope, SS:1
 −1  
d (log10 ID ) kB T Cdm
SS = = ln (10) 1+ . (1.1)
dVGS q Cox

In equation 1.1, kB is Boltzmann’s constant, q is the charge of one electron, Cox is the
areal gate oxide capacitance and Cdm is the areal depletion layer capacitance. Equation 1.1
approaches a lower limit of approximately 60 mV/dec at T = 300K when Cdm/Cox is close to
zero.
Scaling has historically involved decreasing LG and increasing Cox (by decreasing the
effective oxide thickness) so as to increase ION . Even with the co-optimization of material
properties (e.g., peak doping concentration, strain engineering), an aggressively scaled MOS-
FET can exhibit short channel effects that reduce the gate control of the channel. New device
structures have been proposed to replace MOSFETs when decreasing LG and increasing Cox
is no longer possible due to material constraints (or economically viable).
A promising alternative for new current injection mechanisms is any switch that is not
limited to a kBqT ln (10) minimum. Fig. 1.3 qualitatively shows the benefit of a low SS for
an alternative device. A steeply switching device allows for a lower threshold voltage, VT ,
(hence a lower power supply voltage, VDD ) and the possibility of a lower IOFF which decreases
the passive power consumption.
Proposals for alternative devices include scaled down mechanical relays [3], impact ion-
ization FETs [4], feedback FETs [5], FETs with negative gate capacitance [6], and band-
to-band tunneling (BTBT) FETs.[7] This dissertation explores the properties of BTBT and
trap-assisted tunneling (TAT) in the context of tunneling FETs (TFETs).

1
SS equally refers to the subthreshold swing.
CHAPTER 1. INTRODUCTION 4

Figure 1.3: A steeply switching device proves a compelling goal for a MOSFET replacement. The blue
curve represents a traditional MOSFET I-V transfer characteristic. The solid green curve comparatively
highlights the main benefit of a steeper transfer characteristic: a reduction in the power supply voltage,
VDD . Presumably, a steeper SS characteristic can be threshold-voltage shifted (as depicted in the dashed
green curve).

1.3 Tunneling Field Effect Transistors: Basic Design

and Operation
Models for the tunneling probability and the tunneling current (via BTBT) in semiconductors
were succinctly and nearly simultaneously proposed by Leonid V. Keldysh and Evan O.
Kane.[8, 9] Equation 1.2 gives the tunneling current density for a direct bandgap material
commonly found in literature.[10]
√ " √ 3/2
#
2 2m∗ q 2 F π m∗ Eg
JT = 1/2
exp − √ (1.2)
3π 3 h̄2 Eg 2 2h̄qF
m∗ is the carrier effective mass, F is the electric field, Eg is the semiconductor bandgap, and
h̄ is Planck’s constant. Consolidating the electric field pre-factors of equation 1.2 gives the
more common expression for Kane’s equation,
JT = AF · e−
B/F
, (1.3)
where A and B represent material properties for the semiconductor of interest. For a TFET,
equation 1.3 implies that the BTBT generation rate of carriers into the channel is exponen-
tially sensitive to the electric field at the tunneling junction. Whereas for a MOSFET, the
population of carriers in the channel is exponentially sensitive to the surface potential (or
the channel potential).
CHAPTER 1. INTRODUCTION 5

Immediately apparent in equations 1.2 and 1.3 is that a larger electric field at the tun-
neling junction produces a larger BTBT current (i.e., a larger ION ). Incorporating a larger
built-in electric field into the design of a TFET should then increase ION (and thus perfor-
mance) for a given power supply voltage. A conventional TFET design typically utilizes a
very steep doping profile in the source in order to realize a large built-in electric field near
the BTBT junction. Despite advancements in low energy ion implantation, flash annealing,
and in situ doping during epitaxial growth, fabricating very steep doping profiles remains a
challenge.
In 1994, Reddick and Amaratunga proposed and fabricated the first known Si based
BTBT transistor.[11] Motivated by the potential for increased functionality due to negative
differential resistance observed in other tunneling devices, a gated reverse biased diode was
fabricated on bulk Si. This proposed structure called for modulating the tunneling current
by modulating the tunneling barrier width, determined in part by the band gap (Eg ), the
applied bias, and the depletion width.[11] Reddick and Amaratunga also acknowledged the
potential advantage of a necessarily narrow tunneling barrier for the purpose of scaling
beyond complementary MOS (CMOS) transistor technology limits.
Since 1994, numerous experimental avenues seeking sub-60 mV/dec SS at room tem-
perature have been explored. Most approaches have focused (and continue to focus) on the
importance of a large built-in electric field obtained either by in situ epitaxial growth, het-
erostructure formation, 1D quantum confinement, or hyperabrupt depleted pocket doping.[7,
12–15]

1.4 Thesis Organization

This dissertation details three experiments investigating the role of traps within or near a
tunneling junction and follows with a new design approach for a simplified source doping
profile design without an ambitiously steep gradient. In chapter 2, a SB-MOSFET structure
is modified to take advantage of a steep doping profile obtained via dopant segregation from
silicide. Sub- kBqT ln (10) SS is observed and interpreted as a trap based tunneling process
followed by thermionic emission of carriers near the source.
In chapter 3, erbium (Er) impurity atoms are purposely introduced into Si near a hetero-
junction formed with p+ poly-crystalline germanium (Ge). The presence of traps in p-i-n
heterodiodes is verified with temperature dependent measurements and a trap-assisted tun-
neling simulations using a commercially available TCAD semiconductor device simulation
software package. A very low activation energy, EA , is observed for a p+/n+ heterodi-
ode with Er electronic trap states present within the bandgap of Si and TCAD simulations
highlight the limitations of tunneling models for tunneling into and out of trap states.
Er based trap-assisted TFETs (Er-TATFETs) were fabricated on silicon-on-insulator
(SOI) substrates and subsequently characterized. Results from temperature-dependent mea-
surements are presented in chapter 4. Low temperatures (T ≤ ∼200K) were necessary in
order to mitigate thermal generation current due to trap states. The EA in the subthreshold
CHAPTER 1. INTRODUCTION 6

regime for Er-TATFETs was found to be slightly lower in comparison to the EA for p-i-n
control TFETs.
Chapter 5 extends an SOI TFET simulation study to explore the role of reverse back
bias for n-channel germanium-on-insulator (GeOI) based TFETs. A gate-overlapped source
is found to provide superior ION /IOFF enhancement with VB < 0V in comparison to a steeply
graded gate-aligned source. Applying a reverse back bias with a gate-overlapped source can
trigger a large area tunneling junction at turn-on and also mitigate some SCEs.
Finally, chapter 6 summarizes this dissertation and highlights some of challenges facing
TFET devices.
 7

Bibliography

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[2] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, UK:
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[3] V. Pott, H. Kam, R. Nathanael, J. Jeon, E. Alon, and T.-J. K. Liu, “Mechanical
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[7] A. Seabaugh and Q. Zhang, “Low-voltage tunnel transistors for beyond CMOS logic,”
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[8] L. V. Keldysh, “Behaviour of Non-Metallic Crystals in Strong Electric Fields.,” Soviet
Physics: J. Exptl. Theoret. Phys., vol. 33, pp. 994–1003, 1957.
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91, 1961. doi: 10.1063/1.1735965. [Online]. Available: http://link.aip.org/link/
?JAP/32/83/1.
BIBLIOGRAPHY 8

[10] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. Wiley, 1981.

[11] W. M. Reddick and G. A. J. Amaratunga, “Silicon surface tunnel transistor,” Applied
Physics Letters, vol. 67, no. 4, pp. 494–496, 1995. doi: 10.1063/1.114547. [Online].
Available: http://link.aip.org/link/?APL/67/494/1.
[12] K. Bhuwalka, S. Sedlmaier, A. Ludsteck, C. Tolksdorf, J. Schulze, and I. Eisele, “Ver-
tical tunnel field-effect transistor,” Electron Devices, IEEE Transactions on, vol. 51,
no. 2, pp. 279 –282, Feb. 2004, issn: 0018-9383. doi: 10.1109/TED.2003.821575.
[13] S. H. Kim, H. Kam, C. Hu, and T.-J. K. Liu, “Germanium-source tunnel field effect
transistors with record high ION /IOFF ,” in VLSI Technology, 2009 Symposium on, Jun.
2009, pp. 178 –179.
[14] J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris, “Band-to-band tunneling in
carbon nanotube field-effect transistors,” Phys. Rev. Lett., vol. 93, p. 196 805, 19 Nov.
2004. doi: 10.1103/PhysRevLett.93.196805. [Online]. Available: http://link.
aps.org/doi/10.1103/PhysRevLett.93.196805.
[15] P. Patel, K. Jeon, A. Bowonder, and C. Hu, “A low voltage steep turn-off tunnel tran-
sistor design,” in Simulation of Semiconductor Processes and Devices, 2009. SISPAD
’09. International Conference on, Sep. 2009, pp. 1 –4. doi: 10.1109/SISPAD.2009.
5290257.
 9

Chapter 2

Enhanced Schottky Barrier MOSFET

with Steep Subthreshold Swing at
Low Current

2.1 Introduction
When a metal is placed in intimate contact with a semiconductor surface, an intrinsic poten-
tial barrier forms at the interface between the metal and the semiconductor and is referred
to as a Schottky barrier (SB).[1] A non-zero barrier acts to disrupt (though not prohibit) the
free flow of charge carriers across the interface and a depletion region forms in equilibrium to
maintain charge neutrality.1 The value of this SB and how it can be modified is important
when designing low resistance contacts to semiconductor devices such as diodes, transistors,
and resistors.
Metal-semiconductor alloys are routinely formed to reduce the contact resistance of semi-
conductor devices. For a silicon based device, the alloy is a silicide and serves as the metal in
a metal-semiconductor junction. Silicides are the result of an elevated temperature alloying
process referred to as silicidation. For a MOSFET, proper design of the transistor allows for
self-aligned silicidation to take place. For example, platinum is deposited as a blanket film
on top of a MOSFET structure; under thermal treatment, platinum-silicide (PtSi) forms
where Si is exposed to the Pt film. If Pt does not react with the underlying material, the
silicidation process is selective and forms only where Si is exposed.
A Schottky barrier MOSFET (SB-MOSFET) is similar to a conventional MOSFET but
utilizes a SB interface at the source and drain junctions instead of an impurity doped semi-
conductor. A generic SB-MOSFET is schematically shown in Fig. 2.1. The main difference
between the two device structures is that the source-side potential barrier of a MOSFET is
replaced by a SB with an associated Schottky barrier height (SBH). Replacing the source
and drain doping profiles with a silicide holds some promise towards addressing challenges
1
For real material systems.
CHAPTER 2. ENHANCED SCHOTTKY BARRIER MOSFET WITH STEEP
SUBTHRESHOLD SWING AT LOW CURRENT 10

Figure 2.1: A SB-MOSFET device structure. The metal (or silicide) source and drain are well aligned
with the gate edge.

associated with scaling the source and drain profiles in a conventional MOSFET. Reference
[2] provides a good introduction to SB interfaces, some underlying physics and assumptions,
as well as a topical review of the present state of SB-MOSFETs.
Ideally, a well-designed SB-MOSFET provides a solution to various scaling problems
including:[2, 3]

ˆ Low parasitic resistance or access resistance.

ˆ Reduced variability due to source and drain extension profiles near the channel.

ˆ Improved mitigation of short channel effects (SCE).

ˆ Reduced off-state leakage due to the intrinsic SBH.

ˆ Elimination of parasitic bipolar action.

In Fig. 2.1, the source and drain SB junctions are closely aligned to the gate edge with no
gate-to-metal overlap. Aligning the SB interface near the gate edge is important so that
capacitive control of the channel is not compromised.
A key design goal for a SB-MOSFET is a low SBH for carriers injected into the channel.
A low SBH increases the on-current (ION ) (in strong inversion) and presumably the transistor
performance. The intrinsic SBH is determined by the silicide-silicon work function difference.
A SBH can be modified, however, by doping the silicon near the SB.[4] Figure 2.2 shows a
band diagram alignment for a SB interface with and without dopants modifying the SBH.
Optimal SB-MOSFET design necessitates the careful choice of metal for the silicide
formation. An additional requirement is that the silicide formation must also be manageable
from a fabrication perspective. The silicidation process involves the co-diffusion of Si into
CHAPTER 2. ENHANCED SCHOTTKY BARRIER MOSFET WITH STEEP
SUBTHRESHOLD SWING AT LOW CURRENT 11

Figure 2.2: Band diagram of a metal-semiconductor interface with (a) and without (b) dopants. Dopants
near the interface are used to engineer, or adjust, the SBH. φB is the SB potential.

Figure 2.3: Qualitative band diagrams of a SB-MOSFET in the (a) off-state and (b) the on-state. Various
leakage (a) and current injection routes (b) are highlighted in the schematic.

the metal and vice-versa. This alloying reaction produces a reactive interface, or reaction
front, which moves away from the original metal-silicon interface.[5] The choice of the metal,
optional interface materials, silicidation temperature, and geometry of the silicon device all
factor into the final position of the silicide-silicon interface. Consequently, SB junctions well
aligned to the gate edge present a processing and device physics challenge.
Fig. 2.3 shows band diagrams in the off-state and on-state of a SB-MOSFET. When the
potential drop across the source-side SB junction is large enough, the depletion width in
the semiconductor narrows such that field emission tunneling current, IFE , through the thin
triangular barrier is appreciable and becomes the dominant current injection mechanism. In
this way, ION is limited by the SBH at the source. When the SBH is too large, a smaller
fraction of the available states in the metal source contributes to current injection. In general,
SB-MOSFET non-idealities include low ION , subsurface SB junction leakage away from the
active channel of the device, and parasitic metal-semiconductor diode behavior apparent in
the output characteristics (ID (VGS , VDS ) vs. VDS ).[2]
SB-MOSFET fabrication techniques provide an additional avenue towards fabricating
an alternative solid-state switching device. Modifying the SBH using dopant segregation
of impurities implanted into silicide (ITS), relatively steep doping profiles can be realized
CHAPTER 2. ENHANCED SCHOTTKY BARRIER MOSFET WITH STEEP
SUBTHRESHOLD SWING AT LOW CURRENT 12
with a low thermal budget.[4] As discussed in chapter 1, a steep doping profile yields a
large built-in potential and thus a large built-in electric field near the proposed tunneling
junction. Since the band-to-band tunneling (BTBT) probability increases nearly exponen-
tially with the electric field, a large built-in potential near the tunneling junction is desirable.

2.2 Silicide/Silicon Interface

An inherent shortcoming of any thermal process in forming a silicide is the stochastic na-
ture of small imperfections in the initial conditions during semiconductor processing. Most
theoretical and empirical models typically assume an atomically abrupt interface regarding
metal-semiconductor junctions.[2, 6] However, the formation of a silicide by thermal process-
ing necessarily involves co-diffusion of metal atoms into Si and Si atoms into the metal.[5]
Fick’s law of diffusion can be applied to a silicide growth system assuming steady state con-
ditions 2 during certain phases of the growth.[7, 8] For diffusion limited silicide formation,
the final atomic profile of a metal impurity in silicon represents an exponential decay extend-
ing from the silicide/silicon interface.[9] The metal impurity peak concentration is strongly
correlated with the final silicide stoichiometry and nearly equals the atomic density of crys-
talline silicon. The characteristic decay length is governed by the time and temperature of
the silicidation process.
Another consideration is the orientation of silicide grains as the silicide forms. While on
aggregate the reaction interface can be smooth (as schematically depicted in [5]), silicides
commonly considered for SB-MOSFET applications are known to be poly-crystalline. As
such, each grain in the poly-crystalline silicide forms in an energetically favorable orientation
for that particular localized reaction front. Consequently, silicide/silicon interfaces appear
rough on a scale close to or less than the average grain size. This is unfortunate in the context
of scaled SB-MOSFETs in that the silicide/silicon interface is not atomically abrupt and
inherently leads to variability.[10] The stochastic nature of the resulting interface increases
device sensitivity to key device parameters such as subthreshold swing (SS ) and threshold
voltage, VT . Reducing variability is important in almost any type of device scaling, especially
for alternative devices such as TFETs where the SS is very sensitive to local electric field
fluctuations at the tunneling junction.
As a result, a silicide/silicon interface for the purpose of a steeply switching transistor
must, in addition to previous requirements on processing and device design, be uniform across
the width of the device if the interface is close to the tunneling junction. One contributing
factor to a rough interface is the rapid thermal anneal (RTA) process often used to form a
silicide. While an RTA process can reduce the thermal budget, poly-crystalline grain size
can be sensitive to RTA process parameters. By trading a short RTA process time for a
longer temperature ramping time, localized temperature fluctuations at the silicide reaction
front can be mitigated.
2
Such as constant flux or diffusion limited growth.
CHAPTER 2. ENHANCED SCHOTTKY BARRIER MOSFET WITH STEEP
SUBTHRESHOLD SWING AT LOW CURRENT 13
Finally, using a Kissinger analysis to model the silicide thickness with the clas-
sical growth rate equation (equation 2.1) yields a predictive RTA process parameter
set which can be incorporated into a modified SB-MOSFET design. The growth rate
equation predicts the silicide thickness,Z, for
 a known activation energy, EA , tempera-
−EA
ture dependent diffusivity, D = D0 exp kB T , pre-exponential diffusion coefficient, D0 , a
given temperature range from T0 to T , and a known temperature ramp rate, dt/dT : [5, 8, 11]

Z t Z T  −1
2 dT
Z = Ddt = D dT
0 T0 dt
 −1     
dT kB 2 EA 2 EA
= D0 T exp − − T0 exp − . (2.1)
dt EA kB T kB T0

When the temperature remains constant, the thickness is simply estimated by integrating
2.1 (without a variable substitution) to obtain

Z 2 = D (T ) · t. (2.2)
Predictive modeling of the silicide thickness allows for a lower temperature ramp rate
with the end goal of a uniform silicide/silicon interface.
Additionally, when engineering the SBH with doping near the interface, the ITS method
piles up dopants near the interface, similar to dopant segregation induced by silicidation.
However, the ITS method results in a steeper doping profile.[12]
Thus, key requirements for an adequate silicide/silicon interface include:

ˆ Known diffusion coefficients and activation energies for the metal-silicon material sys-
tem.

ˆ A steep, electronically active impurity doping profile near the gate edge.

ˆ A desirable work function yielding a low SBH for the injected charge carriers.

ˆ A uniform, or smooth, silicide/silicon interface parallel to the gate edge.

2.3 Modified Designs for Band-to-Band Tunneling

PtSi was chosen as the lead candidate material for the source and drain for a modified SB-
MOSFET design. PtSi formation is relatively well understood with a low intrinsic SBH for
holes for p-channel FET operation and satisfies many of the aforementioned requirements.[4,
5, 8, 12] To redesign a SB-MOSFET for BTBT current, an asymmetric p-i-n doping profile
is incorporated across the channel region. An additional method to enhance the built-in
electric field near the tunneling junction involves creating a small depletion region, or pocket
CHAPTER 2. ENHANCED SCHOTTKY BARRIER MOSFET WITH STEEP
SUBTHRESHOLD SWING AT LOW CURRENT 14

Figure 2.4: Schematic cross-section of a p-i-n TFET with SB junctions very near the source and drain. In
(a), a pocket doping profile via ITS is introduced prior source ion implantation. In (b), a p-i-n doping profile
via ITS is proposed as a control structure to examine the effect of the pocket formation via ITS. The ITS
method is proposed to form the steep doping profiles necessary for a lower threshold for BTBT.

of opposite doping, near the source tunneling junction.[13] Fig. 2.4 shows a schematic cross-
section of a SB based TFET with and without a doped pocket profile.
Figure 2.5 highlights key fabrication steps for the devices and shows a plan-view scanning
electron micrograph of the fabricated device. The fabrication process for the SB-MOSFET
is described in more detail in section 2.3. The PtSi formation was accomplished with the
following RTA process parameters:

1. 20◦ C/min temperature ramp rate.

2. 300◦ C for 5 min.

3. 25◦ C/min temperature ramp rate.

4. 400◦ C for 5 min.

5. 25◦ C/min temperature ramp rate.

6. 425◦ C for 3 min. with O2 flowing at 25 sccm.

7. Cool down to room temperature.

Out-diffusion of Si to the surface of the PtSi occurs during the final thermal steps. Flowing
oxygen during the final step is necessary to form a protective SiOx layer on top of the PtSi.
This protective SiOx layer prevents removal of the PtSi during a necessary soak in heated,
dilute aqua regia to remove the remaining Pt that did not react with Si.[14]

Fabrication of p-Channel SB S/D FETs

A lightly p-type doped (1·1015 cm−3 ) silicon-on-insulator (SOI) wafer was used as the starting
substrate. Conventional planar processing steps were used to fabricate SB-FETs with a body
CHAPTER 2. ENHANCED SCHOTTKY BARRIER MOSFET WITH STEEP
SUBTHRESHOLD SWING AT LOW CURRENT 15

Figure 2.5: The sequence of key device fabrication process steps is shown on the left, and a plan-view
scanning electron micrograph of a fabricated device is shown on the right with the source, gate, and drain
labeled.

thickness tSi = 25 nm and a thermal gate-oxide thickness tox = 2.8 nm. Note that the self-
aligned PtSi formation step is performed prior to the introduction of any source or drain
dopants. This silicide was formed by sputter deposition of a 17 nm-thick Pt layer followed
by thermal annealing according to the steps listed in the previous section and similar to
the process in [14]. Following silicidation, the n-type source and p-type drain regions were
sequentially formed by ITS processes as follows. First,a drain-masked As+ implantation
process (1 · 1015 cm−2 at 10 keV) followed by a dopant segregation anneal in N2 at 450
◦
C for 15 min was used to form the n-type source region. Second, a source-masked BF+ 2
implantation process (1 · 1015 cm−2 at 10 keV) followed by a dopant segregation anneal in N2
at 500 ◦ C for 5 min was used to form the p-type drain region. The peak doping concentration
in the Si is primarily a function of the segregation anneal temperature [15] and Secondary
Ion Mass Spectrometry (SIMS) analysis of test samples in [15] indicates that the peak As
concentration at the PtSi-Si interface is between 1019 cm−3 and 1020 cm−3 .
Preliminary n-channel SB-MOSFETs were fabricated similar to reference [15] to verify
the silicidation and ITS processing parameters. Experimental splits included pocket SB-
TFETs with control p-i-n SB-TFETs along with temperature and time variations in the
final RTA dopant segregation anneals.

2.4 Device Characterization and Discussion

Device characterization was performed using an HP4155C semiconductor parameter ana-
lyzer and a wafer-probe station with a temperature-controlled chuck. Long integration time
was used so that the noise floor is approximately 10 fA.3 While fabricated n-channel SB-
MOSFETs showed decent transfer characteristics to verify the process flow design (similar to
[15]), SB-MOSFETs modified as pocket TFETs did not yield promising results. A working
hypothesis is as follows:
3
Each data point represents an average of values measured over a period of 266 ms.
CHAPTER 2. ENHANCED SCHOTTKY BARRIER MOSFET WITH STEEP
SUBTHRESHOLD SWING AT LOW CURRENT 16
ˆ Silicide formation inherently involves a Si supply from the SOI substrate and, thus,
the active area of the device.

ˆ When Si diffuses and reacts with Pt, vacancy sites are left behind in near the sili-
cide/silicon interface.

ˆ The RTA process following ITS uses a low temperature anneal and yields electronically
active dopants near the interface.

ˆ If dopant atoms are electronically active, then the dopant atoms occupy lattice sites.

ˆ The formation of a pocket doping profile via a second ITS procedure with a subsequent
dopant segregation necessarily involves the second impurity species displacing the first
impurity species from lattice sites between the PtSi-Si interface and the pocket profile

ˆ If the second impurity species does not displace an appreciable fraction of the first
impurity species in a controlled manner, then the second species merely compensates
the first species resulting in a poorly performing asymmetric SB-MOSFET.

Fig. 2.6 highlights typical transfer characteristics exhibited by pocket SB-TFETs co-
fabricated with p-i-n modified SB-MOSFETs. The pocket transistors display ambipolar
behavior. Similar to SB-MOSFET operation, carriers are likely injected over a thermal
barrier due to a poorly defined pocket dopant profile.

Figure 2.6: Transfer characteristic of a modified SB-MOSFET with a pocket doping profile near the source.
Low ION /IOFF and poor SS are representative of a typical pocket TFETs fabricated in this manner.
CHAPTER 2. ENHANCED SCHOTTKY BARRIER MOSFET WITH STEEP
SUBTHRESHOLD SWING AT LOW CURRENT 17

Figure 2.7: Initial measurements of the transfer characteristics of a p-channel enhanced SB-MOSFET (with
channel length LG = 5 µm and channel width W = 0.7 µm) at two temperatures. The gate voltage step is
10 mV and VDS = -0.5 V. Solid symbols are used for the source current at every third gate voltage step.

Fig. 2.7 shows the initially measured transfer characteristics (|ID | vs. VGS ) for an inter-
esting p-channel p-i-n SB-FET at two temperatures, 300 K and 323 K. A large negative gate
voltage is required to invert the surface of the source region due to the n+ poly gate material
and heavy source doping.4 Note that a change in polarity for ID is evident near VGS = -0.6
V. This polarity change is likely due to reverse-bias diode leakage, which could account for
the observed small opposite-polarity component (approximately 50 fA/µm) of drain current
for VGS > -0.6 V.
Subsequent, more detailed measurements of the transfer characteristics are shown in
Fig. 2.8. The increased gate current is most likely due to cumulative stress over many
measurements made using a long integration time. Despite this increase in the direct gate
4
|VT | can be lowered to be close to 0 V by using a gate material with a larger work function (e.g. p+
poly-Si) and also by lowering the active source doping concentration (by adjusting the dopant segregation
anneal conditions.
CHAPTER 2. ENHANCED SCHOTTKY BARRIER MOSFET WITH STEEP
SUBTHRESHOLD SWING AT LOW CURRENT 18

Figure 2.8: Measured transfer characteristics of a p-channel enhanced SB-MOSFET (with channel length
LG = 5 µm and channel width W = 0.7 µm) at 300K for various values of VDS . The gate voltage step is 10
mV. The light-gray dashed line indicating 60 mV/dec sub-threshold swing is shown for reference. The solid
magenta line is the measured gate current for VDS = -0.5 V.

current, ID is unchanged and continues to show steep switching behavior. Also of note,
the opposite-polarity component of I D is independent of both V GS and VDS (Figs. 2.7
and 2.8). The hollow square symbols in Fig. 2.8 correspond to a two-dimensional (2-D)
device simulation of a SB-MOSFET,[16] discussed in more detail below. For a low operating
voltage, this device exhibits a relatively high on/off current ratio: ION /IOFF = 1.17·103 for
0.2 V gate-voltage swing (from -0.63 V to -0.83 V) at VDS = -0.2 V. Although this device
exhibits relatively low drive current (even at high voltages), an appreciable ION /IOFF is
observed.
To elucidate the limiting mechanism of carrier transport in this device, EA was extracted
from the more detailed |ID |-vs.-VGS measurements made in the temperature range from 10
◦
C to 50 ◦ C (VDS = -0.5 V). EA is only calculated for |ID | > |IG |, corresponding to VGS <
-0.63 V, in order to avoid any artifacts due to the aforementioned small opposite-polarity
CHAPTER 2. ENHANCED SCHOTTKY BARRIER MOSFET WITH STEEP
SUBTHRESHOLD SWING AT LOW CURRENT 19

Figure 2.9: The inset shows the activation energy (EA ) extracted from measurements of log |ID | vs. 1/T,
for T in the range from 10 ◦ C to 50 ◦ C. The open squares (shown for every third gate-voltage step) correspond
to 2-D device simulation for VDS = -0.5 V.

component of drain current. The dependence of EA on VGS (Fig. 2.9) indicates that the
current-limiting mechanism changes with gate bias: at low biases (|VGS | < 0.7 V) EA is
very large (which suggests that the current is limited by thermionic emission of holes either
over a large barrier or from deep traps) and changes more rapidly than qVGS . At moderate
biases (0.7 V < |VGS | < 0.9 V), EA decreases directly with increasing |VGS |, as expected for a
SB-MOSFET when the thermal barrier is greater than the SBH. At high biases (|VGS | > 0.9
V), EA becomes a weaker function of |VGS | as the current becomes limited by SB tunneling.
The rapid change in EA near turn-on is most likely due to thermionic emission of holes
from deep acceptor-like trap states into the valence band (see Fig. 2.10). These trap states
are associated with metallic impurities and/or crystalline defects located close to the PtSi/Si
interface, and holes can be supplied to them via tunneling from the PtSi, a process that turns
on abruptly with increasing |VGS |. As the gate overdrive increases to bring the Si into strong
inversion, injection of holes into the channel from trap states is eventually superseded by
CHAPTER 2. ENHANCED SCHOTTKY BARRIER MOSFET WITH STEEP
SUBTHRESHOLD SWING AT LOW CURRENT 20

Figure 2.10: Schematic energy band diagrams illustrating two carrier injection mechanisms in an enhanced
p-channel SB MOSFET. (a) Before the Si is inverted, holes tunnel to and can hop between electronic trap
states which are distributed both in energy and space near the metal source. They then move to the
Si valence band via thermionic emission. (b) When the Si is inverted, carrier injection is dominated by
traditional thermionic emission over the Schottky barrier from the metal source.

thermionic emission of holes over the source side Schottky barrier.

The transfer characteristic in Fig. 2.8 was simulated using Synopsys Sentaurus Device
TCAD software [16]. The design parameters for the simulated structure are the same as for
the fabricated device: LG = 5 µm, W = 0.7 µm, tSi = 25 nm, tox = 2.8 nm, n-type source
doping ND = 1019 cm−3 , and p-type drain doping NA = 1019 cm−3 . By employing a SB at the
source and drain electrodes with an effective SBH of 0.33 eV and a reduced minority carrier
lifetime (300 ns) to reflect the presence of traps, good agreement between simulated and
measured characteristics (for VDS = -0.5 V) is achieved for the gate voltage range beyond
the steep switching regime. The difference between the simulated and experimental EA
(see Fig. 2.9) highlights the fact that the device simulator does not account for the effect
of tunneling into trap states with a metal boundary condition. As an additional note, no
BTBT model was invoked in the device simulator; thus the simulated device characteristic
does not show sub-60mV/dec switching behavior.
The relatively slow temperature ramp rate described in the previous section (20 ◦ C/min,
see 2.3) and extended anneal time used for the silicidation process in this work likely resulted
in a very extended spatial distribution of Pt atoms within the silicon, as has been observed
for Ni silicidation [9, 17]. Pt impurities in n-type Si have been reported to behave as deep-
level acceptor-like traps [18], supporting the explanation of the large activation energy at
turn-on.
Consistent with the EA measurements, SS < 60 mV/dec is seen at low current levels
(below 10 pA/µm) corresponding to |VGS | < 0.7 V, for multiple values of VDS as well as at
elevated temperature (Fig. 2.11). SS values are shown only for |ID | > |IG |, again to avoid
any artifacts due to the aforementioned small opposite polarity component of drain current.
CHAPTER 2. ENHANCED SCHOTTKY BARRIER MOSFET WITH STEEP
SUBTHRESHOLD SWING AT LOW CURRENT 21

Figure 2.11: Sub-threshold swing (SS) vs. drain current, derived from the measurements in Fig. 2.8. The
sub-60 mV/dec behavior seen below 5 pA/µm is only weakly dependent upon VDS and temperature. The
inset shows that no charging is occurring (to possibly account for the sub-60 mV/dec behavior) for VDS =
-0.5 V since |ID +IS | matches |IG | very well.

The inset of Fig. 2.11 shows that even after many measurements IG remains relatively low
and that all current is accounted for in the measurement (i.e., no charge build-up occurs
to possibly account for the sub-60 mV/dec behavior). Also, IG cannot possibly cause the
observed sub-60 mV/dec SS since IG changes gradually in the range |VGS | < 0.7 V. At higher
current levels, SS increases with ID as expected for a SB-MOSFET.
The transfer characteristics in Fig. 2.12 show that with back bias (VB ) the threshold
voltage (for Si inversion) is reduced with forward back biasing (VB < 0), and increased with
reverse back biasing (VB > 0).5 The dependence on VB with increasing reverse back biasing
decreases as the backside of the n-type source region becomes accumulated. Note that SS
below 60 mV/dec is maintained with back biasing. The results in Fig. 2.13 further suggest
that the hole tunneling process occurs in series with thermionic emission into the valence
band (as illustrated in Fig. 2.10(a)), since VB does not affect the range of ID over which
steep switching is observed.
5
Similar to a SOI-MOSFET.
CHAPTER 2. ENHANCED SCHOTTKY BARRIER MOSFET WITH STEEP
SUBTHRESHOLD SWING AT LOW CURRENT 22

Figure 2.12: Transfer characteristics for various back biases.

Fig. 2.14 shows the measured output characteristics (ID vs. VDS ) for the same device.
Linear behavior is seen at low VDS , which is consistent with a p+ doped drain [19, 20]. (The
current is limited by carrier drift across the channel region (rather than by SB tunneling) at
low drain biases [19].)
The on/off current ratios in Fig. 2.15 are derived from the transfer characteristics pre-
sented in Fig. 3, for each value of VDD . The two reference lines in Fig. 2.15(a) represent
SS = 75 mV/dec and 100 mV/dec, which span a range of typical values for conventional
short-channel MOSFETs. It can be seen that the enhanced SB-MOSFET achieves a higher
on/off current ratio than a conventional MOSFET for VDD < ∼0.25 mV. In Fig. 2.15(b),
the on/off current ratios at VDD = 0.2 V are presented as a function of temperature. The en-
hanced SB-MOSFET shows a reduced temperature dependence compared to the lower limit
of temperature dependence for a conventional MOSFET. This is consistent with a carrier
injection mechanism that is not limited by thermionic emission. One example of a carrier
injection mechanism not limited by thermionic emission would be band-to-band tunneling
and a previous study of band-to-band tunneling transistors also shows a reduced dependence
on temperature [21].
CHAPTER 2. ENHANCED SCHOTTKY BARRIER MOSFET WITH STEEP
SUBTHRESHOLD SWING AT LOW CURRENT 23

Figure 2.13: SS in the steep-switching regime shows little dependence on VB , suggesting that electronic
trap states near the silicide/silicon interface provide for an alternative hole injection process.

Figure 2.14: Measured output characteristics of the enhanced SB-MOSFET of Fig. 2.7. ID is linear with
VDS , at low values of VDS . The inset shows a zoomed-out view of the same plot, so that the curves for larger
gate biases can be seen.
CHAPTER 2. ENHANCED SCHOTTKY BARRIER MOSFET WITH STEEP
SUBTHRESHOLD SWING AT LOW CURRENT 24

Figure 2.15: On/off current ratios for the reported device. ION is taken to be ID at VGS - VT = VDD while
IOFF is taken to be ID at VGS = VT . VT is defined to be VGS for |ID | = |IG |, in this case VT = -0.63 V.
In part (a), the on/off current ratio is plotted as a function of VDD and with log-linear reference lines of 75
mV/dec and 100 mV/dec for comparison. A polynomial fit (grey curve) helps illustrate the low power on/off
performance trend for this device. Part (b) shows the on/off current ratio at VDD = 0.2 V as a function
of temperature and a lower thermal limit reference line of a conventional MOSFET device calculated for a
voltage range of 0.2 V.
CHAPTER 2. ENHANCED SCHOTTKY BARRIER MOSFET WITH STEEP
SUBTHRESHOLD SWING AT LOW CURRENT 25
2.5 Summary
The experimental results reported in this chapter indicate that the presence of trap states
within a narrow, barrier-enhancing doped silicon region next to a Schottky source junction
offers an interesting approach towards observing sub-60 mV/dec SS for MOSFET devices.
Similar work has been presented in literature.[22–24] Silicide TFET devices presented in
the literature perhaps utilize the same or similar operating mechanism, though each article
typically explains the steep switching as a result of BTBT. In general, a exponential decay
with a high concentration of metal impurity atoms in a transition zone in close proximity to
a silicide-silicon interface may augment the electronic band structure such that the effective
band gap for tunneling is reduced.
 26

Bibliography

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2165331.
 29

Chapter 3

Engineered Electronic Trap States in

Tunneling Diodes

3.1 Introduction
Well documented investigations of the role of traps in band-to-band tunneling (BTBT) typ-
ically focus on reverse biased or Esaki-like tunneling diode structures.[1–3] These structures
offer simple device physics modeling for studying tunneling since there is only a single pn
junction. A motivating factor for investigating trap states and BTBT is the unexplained
observation of excess current in Esaki diodes.[4] At a low forward bias, an Esaki diode con-
ducts current primarily via BTBT up to an applied bias corresponding to a peak bias (see
Fig. 3.1). When the band overlap reaches zero, BTBT should cease and the current should
diminish to the normal forward bias diode current (approximately given by the diode equa-
tion). However, an excess current is observed due to tunneling into and out of electronic
trap states located within the band gap as well as from states located within the band edge
tails.[4]
Figure 1 in [4] schematically presents various trap assisted tunneling routes as a basis
for modeling the excess current. Excess current is often attributed to intrinsic defects in
crystalline silicon and a deliberate introduction of crystal imperfections by radiation bom-
bardment correlates with a dramatic increase in the excess current (see Figure 4 in [4]).
Early theoretical and experimental investigations into BTBT laid the foundation for un-
derstanding the role of tunneling in leakage for scaled down silicon MOSFET devices.[5]1
Modeling work by Hurkx and later Schenk led to improvements in the BTBT models in-
corporated into semiconductor device simulations.[3, 5, 6] Qualitatively, when these models
are employed in a device simulation, the BTBT generation rate is calculated at each grid
point. This generation rate is heavily dependent on the value of the electric field at that
grid point. Other factors, such as minority carrier lifetimes and the presence of trap states,
1
For example, increasing the peak doping concentrations or utilizing steep doping profiles while scaling
down dimensions
CHAPTER 3. ENGINEERED ELECTRONIC TRAP STATES IN TUNNELING
DIODES 30

Figure 3.1: An Esaki diode in thermal equilibrium (a). The heavily doped p and n quasi-neutral regions
cause band overlap between the valence and conduction bands in the off state. (b) A small forward bias
is applied such that the band overlap is zero. (c) Qualitative I-V characteristics for a typical Esaki diode
(black line) show excess current greater than the forward bias diode current (blue line) when the applied
voltage exceeds the bias point labeled as (b). The bias points for parts (a) and (b) are labeled in part (c).

are incorporated into calibration parameters for improvements to the model. While these
models work well in predicting the tunneling rate in and around a reverse biased pn junction,
the models do not account for any spatially dependent term in the calculation of the BTBT
generation rate.

Figure 3.2: In (a), a BTBT generation rate is calculated with (blue arrow) and without (green dots) a
spatial dependence for the tunneling model. Part (b) illustrates both thermal excitation to and from traps
(solid green arrow) and an additional path for carriers exiting from traps, field emission tunneling (dashed
green arrow). Field emission from the trap is modified in a local tunneling model by calibration parameters.

A spatial dependence is necessary for accurate device structure modeling when the band-
CHAPTER 3. ENGINEERED ELECTRONIC TRAP STATES IN TUNNELING
DIODES 31
to-band overlap occurs over an appreciable distance. Without a spatially dependent term
in the tunneling model, tunneling from an occupied state to an unoccupied state is approx-
imated by a tunneling generation rate calculated at a single point. Additionally, the role
of traps is relegated to generation and recombination models near the grid point when the
tunneling rate is calculated. Figure 3.2 highlights the difference between a local and nonlo-
cal tunneling model. These models are approximations and therefore insufficient for TFET
design and simulation where the role of traps in BTBT is under investigation.
The Synopsys TCAD Sentaurus simulation engine includes a robust dynamic nonlocal
BTBT tunneling model which greatly improves the accuracy of TFET simulation and de-
sign work. The dynamic nonlocal trap-assisted tunneling model, however, does not explicitly
model tunneling into and out of electronic trap states in conjunction with the BTBT tunnel-
ing model.[7] Rather, this model incorporates previous trap-assisted tunneling models (e.g,
Hurkx and Schenk) with a modified electric field calculated by the maximum of the gradient
of the potential profile. This highlights a shortcoming of most tunneling models to accurately
calculate discrete tunneling into and out of electronic trap states.
The lack of a robust numerical tunneling model for traps necessitates the use of exper-
imental methods to further investigate the role of traps in BTBT. A powerful analysis for
investigating electronic trap state properties is to calculate the activation energy, EA , from
temperature dependent current-voltage measurements (see 2.9). Calculation of the activa-
tion energy is possible with an Arrhenius analysis [8] and calculating EA as a function of the
applied bias assists in determining how trap states affect the normal operation of a tunneling
device.
For an Arrhenius analysis, the data is presumed to have an exponential dependence
related to the thermal energy:  
−EA
I ∝ A · exp . (3.1)
kB T
A is an exponential prefactor and kB T is the thermal energy. Taking the natural logarithm
of both sides yields the slope intercept form y = m · x + b where the slope is −E kB
A
and the
1
dependent variable is T .
EA 1
ln (I) ∝ ln (A) − · , (3.2)
kB T
The slope of a best fit line of the natural logarithm of the temperature dependent data versus
1
T
allows the straight forward calculation of EA . For electronic trap states, determining EA
helps identify the energy level of the trap state as well as the dominant current injection
method.

3.2 Impurity Selection for Electronic Trap State

Fig. 3.3 shows four possible routes for carriers to enter and exit an electronic trap state
located within the band gap. By lowering the temperature of the semiconductor, carriers
CHAPTER 3. ENGINEERED ELECTRONIC TRAP STATES IN TUNNELING
DIODES 32
exhibit a lower thermal energy and so reduces the probability of thermal excitation into and
out of the trap. Ideally, a low enough temperature will quench the trap assisted thermal
excitation process. As suggested in the example in Fig. 3.3, this leads to a greater fractional
tunneling component in the generation rate of carriers in the conduction band. An electronic
trap state energy level, ET , appreciably far from both the valence and conduction bands can
assist in isolating the role of tunneling into and out of trap states in a dynamically biased
semiconductor junction. ET sufficiently far from both band edges at a low temperature
should enhance the tunneling probability into and out of the trap as the thermal excitation
probability is decreased. Heterodiodes were fabricated to explore the role of traps states in
close proximity to a BTBT junction.

Figure 3.3: Four routes are shown in (a) for carriers entering and exiting a trap state and energy ET .
Thermal excitation is shown in solid green arrows while tunneling into and out of the trap is shown with
dashed green arrows. (b) Lowering the temperature of the measurement can reduce the thermal excitation
components.

A dated but comprehensive chart of electronic trap state types and energy levels appears
in section 1.4.2 of [8]. From the chart in [8], chromium is immediately identified as a single
level trap close to the mid-gap of Si (EC − ET = 0.41 eV). However, very few reports exist
detailing the electronic properties of chromium in Si. A more detailed search of the literature
suggests erbium (Er) as another likely candidate for engineered electronic trap states.[9–12]
A majority of the literature regarding Er impurities in Si focuses on the opto-electronic
properties for the purpose of integrated Si based photonics. Er typically exhibits a trap
state energy level between the mid-gap of Si and the conduction band edge. A trap located
close to the mid-gap of Si is advantageous since a larger energy is necessary to excite a carrier
either to or from a trap.
CHAPTER 3. ENGINEERED ELECTRONIC TRAP STATES IN TUNNELING
DIODES 33
Various reports identify multiple energy levels for Er in Si ranging from 0.18 eV < EC −
ET < 0.6 eV with mid gap trap states seemingly more likely to occur in.[9–11, 13] The
concentration of Er atoms, the background doping of the Si, as well as the proximity of
oxygen atoms and crystalline defects in the Si all influence the electronic trap state properties.
With this in mind, reference [12] notes that the optically active Er concentration is limited
to approximately 3 · 1017 cm−3 . The work reported here targets an Er concentration close to
1017 cm−3 so as to avoid adverse effects of a high concentration of impurities, some of which
may not be fully electronically active.

3.3 Experimental Design Goals

To explore the role of traps in BTBT, Er was purposely introduced into heterodiode devices,
schematically depicted in Fig. 3.4. On-wafer splits were employed to provide control sam-
ples for co-fabricated devices. The device structures consist of either a p+-i-n+ or p+/n+
heterodiode with p+ poly-germanium (Ge) selectively deposited on the Si surface of an
silicon-on-insulator (SOI) wafer. For the Er+ on-wafer split, the top half of the wafer re-
mained in the original state while the bottom half was implanted with Er+ ions with a dose
of 7 · 1011 cm−2 and an implant energy of 10 keV. Ge was chosen for the heterostructure
material since Ge has a lower band gap than Si and poly-crystalline Ge can be selectively
deposited onto Si using low pressure chemical vapor deposition (LPCVD). Fig. 3.4 shows
four experimental splits incorporated into the top and bottom half of the wafer for a total
of eight splits.
TRIM simulations using SRIM software were used to predict a peak concentration for
the device structure.[14] Low temperature oxide (LTO) deposited by LPCVD was used to
protect the surface of the structure during ion implantation and can be easily removed with
a hydrofluoric (HF) acid wet etch prior to further processing. Fig. 3.5 shows the results of
numerical calculations performed by SRIM (using a TRIM calculation) of Er+ ions implanted
into a test structure. Nearly all of the Er+ ions remain within the first 15nm (150 angstroms)
of Si for a 10 keV energy implant through a 10nm thick LTO film. Ideally, engineering the
trap profile to be close to the Si surface will promote a trap assisted BTBT (TA-BTBT)
process since tunneling junction is designed to coincide with the heterojunction.
Sample preparation involved typical planar processing techniques with the following key
fabrication steps listed below:

ˆ Active area definition.

ˆ Er+ ion implantation for the bottom half of wafer.

Energy = 10 keV, Dose = 7·1011 cm−2

ˆ As+ ion implantation.

Energy = 10 keV, Dose = 1015 cm−2
CHAPTER 3. ENGINEERED ELECTRONIC TRAP STATES IN TUNNELING
DIODES 34

Figure 3.4: Four device structures are shown, each co-fabricated on the same wafer. Each of the four splits
was fabricated with and without implanted Er+ for a total of eight splits. Trap states are represented in the
diagrams as narrow hyphenated marks.

Split for a blanket As+ and masked As+ . (See Fig. 3.4.)
Solid phase epitaxy regrowth (SPER) anneal at 550◦ C for 4 hours.
Rapid thermal anneal (RTA) at 1050◦ C for 10 seconds.

ˆ Selective p+ poly-Ge deposition with in situ doping near 3·1019 cm−3 .

LPCVD 425◦ C with 3:1 ratio of BCl3 :GeH4 gas flow.

ˆ P+ ion implantation split.

P segregation anneal for 1 hour at 700◦ C.

The intention of the phosphorus implant and segregation anneal split is to test a phosphorus
”pile up” at the poly-Ge/Si interface. Such a pile up could induce a deeper n-type well as
a test for cutting off BTBT at energies from the valley of the well to EC,Si beyond the well.
Fig. 3.6 qualitatively highlights this proposal for cutting off the BTBT near the tunneling
heterojunction.
CHAPTER 3. ENGINEERED ELECTRONIC TRAP STATES IN TUNNELING
DIODES 35

Figure 3.5: Erbium ion implantation numerical calculations performed by SRIM software. Various combi-
nations of the Er+ implant energy and LTO film thickness are displayed. The curves are plotted from the
silicon substrate surface and implanted concentrations normalized to the dose.

Figure 3.6: As proposed, an n-type well near the tunneling heterojunction should cut off some BTBT
paths. The majority of the band gap difference between Ge and Si is represented by ∆EV .
CHAPTER 3. ENGINEERED ELECTRONIC TRAP STATES IN TUNNELING
DIODES 36
3.4 Diode I-V Characteristics and Temperature
Dependence
Fabricated diodes were characterized using either a HP4155C or an Agilent B1500A semi-
conductor parameter analyzer. Initial measurements of all of the experimental splits showed
some diodes with rectifying behavior and others with resistive behavior. Table 3.1 summa-
rizes the experimental split yield. Diode I-V curves were measured with an applied bias on
the p+ poly-Ge contact with a 5 mV step size at medium to long integration time for lower
noise and low current accuracy. Temperature dependent measurements were carried out on
rectifying diodes from 300K to as low as 150K and used to determine the activation energy as
a function of applied bias. For each temperature dependent measurement, the samples were
held at the target temperature for at least 45 minutes in order to achieve a stable thermal
equilibrium in the measurement probe station.
Reasons explaining why only some of the experimental splits did not yield rectifying
behavior remains unknown. Unfortunately, an interesting rectifying split for p+/n+ hetero-
diodes without phosphorus and with Er has no control device (i.e., a similar device without
Er) for a more direct comparison to isolate the role of Er trap states in a tunneling junction.
One hypothesis is that the presence of Er atoms mitigated some of the damage caused by the
blanket As+ implant. Testing this hypothesis was beyond the scope of this work. Alternative
process flows to enhance the yield of a similar experiment could include a thicker SOI layer
for improved recrystallisation during the SPER anneal or a lower dose As+ implant. The
rest of this section focuses on the tunneling diode results with some comparisons to control
p-i-n diodes as well as simulated diode behavior when appropriate.

Blanket As+ P+ Er+ Rectifying?

0 0 0 Yes
0 1 0 Yes
0 0 1 Yes
0 1 1 Yes
1 0 0 No
1 1 0 No
1 0 1 Yes
1 1 1 No
Table 3.1: Experimental heterodiode splits and rectifying device yield.

Fig. 3.7 shows temperature dependent current-voltage (I-V) characteristics of fabricated

p-i-n heterodiodes with and without Er trap states. Heterodiode p-i-n devices fabricated
with implanted Er atoms showed a slightly greater dependence on temperature at small
reverse bias. This can be observed in the slightly larger spread in reverse bias saturation
CHAPTER 3. ENGINEERED ELECTRONIC TRAP STATES IN TUNNELING
DIODES 37
current.2 Additionally, comparing the first derivatives of the I-V characteristics, Fig. 3.8,
shows that p-i-n heterodiodes with Er have a smaller slope across a range of reverse bias.
That is, the reverse bias diode saturation current is more than likely dominated by the Er
trap states purposely introduced into the Si substrate.

Figure 3.7: I-V characteristics for a p-i-n control heterodiode (solid lines) and a p-i-n heterodiode with
Er trap states (symbols) over a temperature range of 275K to 350K. For a small reverse bias, the I-V
characteristics for the heterodiodes with Er traps states show a slightly greater temperature dependence
than for the control device.

EA was calculated using an Arrhenius analysis described in section 3.1. Preliminary

calculations for EA using the I-V curves in Fig. 3.7 are shown in Fig. 3.9. EA for the
p-i-n heterodiode with Er trap states appears slightly greater (0.6 eV) than the p-i-n control
diode (0.5 eV). Presumably, the majority of carrier generation in a p-i-n heterodiode control
structure occurs in the depleted intrinsic Si region. With an energy very close to the middle
of the band gap (∼0.5 eV), this most likely corresponds to inherent point defects in the
intrinsic Si. When Er traps are present, the traps plays a greater role in the generation and
recombination of carriers and as such an Er trap level dominates the activation energy over
a range of reverse bias. An Er in Si trap state energy level of 0.6 eV is in good agreement
with a trap energy value reported in literature provided this trap level is the dominant
generation-recombination center in comparison with other known trap levels of Er in Si.[9,
10]
2
Both devices represented in Fig. 3.7 are fabricated to the same physical dimensions.
CHAPTER 3. ENGINEERED ELECTRONIC TRAP STATES IN TUNNELING
DIODES 38
TCAD simulations using Synopsys Sentaurus [7] were employed to verify that EA corre-
sponds to the trap energy level of the Er impurity atoms. For simplicity in the simulation,
crystalline Ge material parameters were used for the poly-Ge material. Fig. 3.9 shows the
calculated EA for two experimental p-i-n diodes as well as the activation energies from sim-
ulated p-i-n heterodiodes with and without traps. Each simulation uses a dynamic nonlocal
BTBT model as well as a recombination-generation based dynamic nonlocal trap assisted
tunneling model. No other models for the physics of trap states in a semiconductor were
used. The simulated trap energy level was set such that EC − ET = EA calculated from the
measured I-V characteristics. Trap states were included in the simulation at a concentration
chosen to be NT = 5·1017 cm−3 . This NT yields an EA in close agreement with experimental
results for a p-i-n heterodiode with Er. Simulation results with NT = 0 cm−3 show a much
higher activation energy, suggesting that the simulation software does not correctly account
for intrinsic electronic trap states without use of additional generation-recombination models.

Figure 3.8: The first derivative of the I-V characteristics in Fig. 3.7 are presented for the p-i-n heterodiode
control (solid lines) and p-i-n heterodiodes with Er trap states (dotted lines). The slopes for the heterodiodes
with Er trap states remain less than the corresponding slopes for the heterodiode controls.

While the p+/n+ heterodiode with Er traps show tunneling behavior in reverse bias
and rectifying behavior in forward bias, the control devices for this experimental split do
not show any rectifying behavior. While the simulation software does not explicitly account
for tunneling into and out of a trap state, the previous verification of the behavior of Er
trap states as generation-recombination centers serves to substantiate at least a nominally
correct incorporation of trap states in a simulation. Ge/Si (p+/n+) structures with and
without trap states and with no intrinsic region were simulated for I-V characteristics at
temperatures down to 175K.
CHAPTER 3. ENGINEERED ELECTRONIC TRAP STATES IN TUNNELING
DIODES 39

Figure 3.9: EA calculated from experimental results for a p-i-n control heterodiode and a p-i-n heterodiode
with Er trap states in Si (symbols). EA calculated from simulated temperature dependent heterodiode I-V
curves (solid lines) shows some agreement with the incorporation of Er in Si. The simulation result for no
traps appears at higher energy and is noisy due to the numerical errors in the simulator at very low current.
The symbols are plotted with fewer data points for clarity.

Fabricated p+/n+ heterodiode devices with Er trap states show tunneling behavior in
reverse bias (see Fig. 3.10), however, no peak-to-valley current ratio or negative differential
resistance (indicative of Esaki tunneling behavior [8, 15]) is evident at any forward bias
despite the expected Esaki band alignment at zero bias (see Fig. 3.11). Fig. 3.12 shows the
calculated EA for the experimental I-V curves presented in Fig. 3.10. EA for the p+/n+
tunnel diode with Er trap states remains very low with applied reverse bias - EA is 55
meV at very small reverse bias and decreases with increasing reverse bias. Since there is
no negative differential resistance at small forward bias, the conduction and valence bands
may not be overlapping in energy at zero bias. Since the traps lie within the Si, further
application of a reverse can lower the trap state energy levels below the energy of tunneling
carriers. This could explain why the experimentally determined EA decreases with reverse
back bias towards the lower tunneling energy for a reverse biased p+/n+ heterodiode.
Simulated temperature dependent I-V characteristics for a p+/n+ heterodiode with no
trap states shows EA trending to 0 eV at zero bias. As noted for Fig. 3.11, band overlap at
zero bias is expected for the simulated structure where the simulated physical parameters are
in close agreement to experimental values (either predicted or measured), so EA trending to
0 eV at zero bias suggests that the simulation software assumes little to no activation energy
necessary for BTBT in an Esaki tunneling diode. EA calculated from simulated character-
istics increases with increasing reverse bias (Fig. 3.12) though still remains low throughout
CHAPTER 3. ENGINEERED ELECTRONIC TRAP STATES IN TUNNELING
DIODES 40

Figure 3.10: Typical tunneling diode characteristics for fabricated p+/n+ heterodiodes measured across
various temperatures. Not all temperatures are displayed for clarity. Note that there is no negative differ-
ential resistance characteristic of an Esaki tunneling diode.

the same reverse bias range. Unfortunately, simulated p+/n+ heterodiode structures with
trap states show little to no change in EA when compared to simulated results for a p+/n+
heterodiode with no trap states.
Other simulation studies (not presented here) suggest that the simulation software does
not couple the dynamic nonlocal trap assisted tunneling model with the dynamic nonlocal
BTBT model (i.e., the models appear to be non-interacting).3 While tunneling is a majority
carrier process,[8] the close proximity of a large concentration of trap states to a tunneling
junction is expected to alter the tunneling dynamics. This effect is likely not accurately
captured in the simulation software.

3
For example, a simulated Esaki-like p+/n+ heterodiode without the dynamic nonlocal BTBT model
but with the dynamic nonlocal trap assisted tunneling model shows no indications of BTBT, with or without
traps.
CHAPTER 3. ENGINEERED ELECTRONIC TRAP STATES IN TUNNELING
DIODES 41

Figure 3.11: Simulated band diagrams for EC and EV for a poly-Ge/Si p+/n+ heterodiode at zero applied
bias and a reverse bias of Vapp = -0.5 V. The alignment at zero bias suggests Esaki tunneling diode behavior
should be observable.

Figure 3.12: The calculated EA from fabricated p+/n+ tunnel diodes with Er trap states shows a very
low activation energy from small reverse bias to Vapp = -0.5 V. Simulated I-V characteristics for a p+/n+
heterodiode without trap states also result in a low EA for -0.5 V ≤ Vapp ≤ 0 V.
CHAPTER 3. ENGINEERED ELECTRONIC TRAP STATES IN TUNNELING
DIODES 42
3.5 Conclusion
Failed experimental splits for the fabrication of p+ poly-Ge on SOI heterodiodes made it
challenging to isolate the effects of Er impurity atoms in close proximity to BTBT junctions.
Experimental splits involving phosphorus segregation from the poly-Ge either did not exhibit
rectifying behavior or did not yield any significant variation in operation of the device.
Results for p-i-n heterodiode structures suggest that engineering an Er trap density in the
intrinsic Si region can change the activation energy in reverse bias towards an expected trap
energy level of Er in Si.[9, 10]
When possible, TCAD simulations using Synopsys Sentaurus commercial software were
employed to validate and explore the role of traps near a tunneling junction. While the
dynamic nonlocal models for BTBT and trap assisted tunneling have been independently
verified,[7] the models together were insufficient in explaining the role of Er trap states in a
p+/n+ heterodiode tunneling junction.
 43

Bibliography

[1] E. O. Kane, “Theory of tunneling,” Journal of Applied Physics, vol. 32, no. 1, pp. 83–
91, 1961. doi: 10.1063/1.1735965. [Online]. Available: http://link.aip.org/link/
?JAP/32/83/1.
[2] G. Hurkx, D. Klaassen, and M. Knuvers, “A new recombination model for device
simulation including tunneling,” Electron Devices, IEEE Transactions on, vol. 39, no.
2, pp. 331 –338, Feb. 1992, issn: 0018-9383. doi: 10.1109/16.121690.
[3] A. Schenk, “Rigorous theory and simplified model of the band-to-band tunneling in
silicon,” Solid-State Electronics, vol. 36, no. 1, pp. 19 –34, 1993, issn: 0038-1101. doi:
10.1016/0038-1101(93)90065-X. [Online]. Available: http://www.sciencedirect.
com/science/article/pii/003811019390065X.
[4] A. G. Chynoweth, W. L. Feldmann, and R. A. Logan, “Excess tunnel current in sil-
icon esaki junctions,” Phys. Rev., vol. 121, pp. 684–694, 3 Feb. 1961. doi: 10.1103/
PhysRev . 121 . 684. [Online]. Available: http : / / link . aps . org / doi / 10 . 1103 /
PhysRev.121.684.
[5] G. Hurkx, “On the modelling of tunnelling currents in reverse-biased p-n junctions,”
Solid-State Electronics, vol. 32, no. 8, pp. 665 –668, 1989, issn: 0038-1101. doi: 10.
1016/0038- 1101(89)90146- 9. [Online]. Available: http://www.sciencedirect.
com/science/article/pii/0038110189901469.
[6] G. Hurkx, D. Klaassen, and M. Knuvers, “A new recombination model for device
simulation including tunneling,” Electron Devices, IEEE Transactions on, vol. 39, no.
2, pp. 331 –338, Feb. 1992, issn: 0018-9383. doi: 10.1109/16.121690.
[7] Sentaurus Device User Guide. Synopsys, Inc., 2010.
[8] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. Wiley, 1981.
[9] A. Cavallini, B. Fraboni, and S. Pizzini, “Deep levels in Er-doped liquid phase epitaxy
grown silicon,” Applied Physics Letters, vol. 72, no. 4, pp. 468–470, 1998. doi: 10.
1063/1.120788. [Online]. Available: http://link.aip.org/link/?APL/72/468/1.
BIBLIOGRAPHY 44

[10] S. Binetti, A. Cavallini, A. Dellafiore, B. Fraboni, E. Grilli, M. Guzzi, S. Pizzini, and S.

Sanguinetti, “Erbium-doped silicon epilayers grown by liquid-phase epitaxy,” Journal
of Luminescence, vol. 80, no. 14, pp. 347 –351, 1998, issn: 0022-2313. doi: 10.1016/
S0022- 2313(98)00127- 6. [Online]. Available: http://www.sciencedirect.com/
science/article/pii/S0022231398001276.
[11] J. L. Benton, J. Michel, L. C. Kimerling, D. C. Jacobson, Y.-H. Xie, D. J. Eaglesham,
E. A. Fitzgerald, and J. M. Poate, “The electrical and defect properties of erbium-
implanted silicon,” Journal of Applied Physics, vol. 70, pp. 2667–2671, Sep. 1991. doi:
10.1063/1.349381.
[12] A. Polman, G. N. van den Hoven, J. S. Custer, J. H. Shin, R. Serna, and P. F. A.
Alkemade, “Erbium in crystal silicon: optical activation, excitation, and concentration
limits,” Journal of Applied Physics, vol. 77, no. 3, pp. 1256–1262, 1995. doi: 10.1063/
1.358927. [Online]. Available: http://link.aip.org/link/?JAP/77/1256/1.
[13] S. Libertino, S. Coffa, G. Franzo, and F. Priolo, “The effects of oxygen and defects
on the deep-level properties of Er in crystalline Si,” Journal of Applied Physics, vol.
78, no. 6, pp. 3867–3873, 1995. doi: 10.1063/1.359903. [Online]. Available: http:
//link.aip.org/link/?JAP/78/3867/1.
[14] J. F. Ziegler, J. P. Biersack, and M. D. Ziegler, SRIM - The Stopping and Range of
Ions in Matter (SRIM co., 2008). [Online]. Available: http://www.srim.org.
[15] L. Esaki, “New phenomenon in narrow germanium p − n junctions,” Phys. Rev., vol.
109, pp. 603–604, 2 Jan. 1958. doi: 10.1103/PhysRev.109.603. [Online]. Available:
http://link.aps.org/doi/10.1103/PhysRev.109.603.
 45

Chapter 4

Erbium Trap Assisted TFET

4.1 Introduction
Drawing upon previous results reported in chapters 2 and 3, the experiment reported here
was co-designed with the heterodiode work to explore the broader role of traps in a TFET. To
investigate how trap states alter the activation energy of band-to-band tunneling (BTBT) in
a transistor, planar SOI TFETs were fabricated with and without ion implanted erbium (Er)
intended to form electronic trap states within the band gap. The overall design (depicted
schematically in Fig. 4.1) calls for the traps to be located in close proximity to the tunneling
junction as well as preferentially between the mid-gap of Si and the conduction band edge
of Si.
Er impurity atoms were again chosen to form the electronic trap states with a target
concentration near 1017 cm−3 . Er ions were implanted prior to the silicon nitride spacer

Figure 4.1: Traps are located in close proximity to the tunneling junction which is designed to be near
the gate edge of the SOI TFET. A self aligned Er+ ion implant avoids the introduction of trap states in the
channel region. The spacers are comprised of thermally grown oxide on poly-Si (light blue), a silicon nitride
thin film (orange), and a low temperature oxide (light blue).
CHAPTER 4. ERBIUM TRAP ASSISTED TFET 46

Figure 4.2: Er electronic trap states in crystalline Si should be located between EC − ET = 0.18 eV and
EC − ET = 0.6 eV. The orange arrows indicate thermal excitation routes while the black arrows suggest
tunneling paths available to carriers in close proximity to the traps.

formation so that the traps are well aligned with the gate edge near the source. Fig. 4.2
shows a schematic energy band diagram with a trap state located near the tunneling junction.
Figs. 4.1 and 4.2 represent an n-channel Er-based trap-assisted TFET (Er-TATFET) design
with hash marks indicating the qualitative position of the traps.
Low temperature measurements were again employed in order to reduce the thermal
excitation to and from the trap states (see Fig. 3.3). Careful analysis of the temperature
dependence yields the activation energy (EA ) as a function of the applied gate bias for the
Er-TATFETs.

4.2 Experimental Design Goals

An on-wafer experimental split allows for the co-fabrication of experimental Er-TATFETs
and control p-i-n SOI TFETs. Using photolithography, one half of the wafer is masked
during the Er+ ion implantation so that p-i-n TFETs are fabricated without any engineered
electronic trap states. Key fabrication steps include:

ˆ Active area definition, thermal oxide for gate dielectric, and gate stack formation.
tox = 2.81 nm.

ˆ Poly-Si gate definition and gate sidewall re-oxidation.

ˆ Er+ ion implantation

Energy = 10 keV, Dose = 7·1011 cm−2 .
CHAPTER 4. ERBIUM TRAP ASSISTED TFET 47

ˆ Silicon nitride spacer formation.

ˆ TFET source masked As+ ion implantation: Energy = 20 keV, Dose = 1.5·1015 cm−2 .

ˆ Solid phase epitaxy regrowth (SPER).

Anneal at 550◦ C for 4 hours.

ˆ Second spacer formation with low temperature oxide.

ˆ TFET drain masked B+ ion implantation: Energy = 10 keV, Dose = 5·1015 cm−2 .

ˆ Solid phase epitaxy regrowth (SPER).

Anneal at 550◦ C for 4 hours.

ˆ Two step rapid thermal anneal (RTA) for 900C/15s and 1050C/15s.

No metal contact layer is used in part to avoid any risk of metal impurities in close
proximity to the tunneling junction.

4.3 Electrical Characterization and Temperature

Dependence
Er-TATFETs were characterized using either an HP4156C or Agilent B1500A semiconductor
parameter analyzer. Care was taken to ensure accuracy of low current measurements both
in the electronic measurement and the experimental setup. The temperature dependence
was investigated in the range from 77K to 300K in a vacuum cold-probe station. Due
to a low fabrication yield, all fabricated devices were first screened using an ElectroGlas
Autoprobe system modified for use with an HP4156C analyzer. Some ambipolar TFET
behavior is expected for a planar SOI TFET. Overall, the asymmetric design exhibited better
n-channel behavior across all active devices in this experiment. Measurement parameters for
DC transfer characteristics consisted of VS = 0 V, VDS = 1 V and 1.5 V, and sweeping VGS
from 1 V to beyond 4 V to provide adequate gate overdrive. A large drain bias is necessary
so that the tunneling current can increase significantly beyond the gate leakage current.
CHAPTER 4. ERBIUM TRAP ASSISTED TFET 48

Figure 4.3: Typical DC transfer characteristics for an SOI Er-TATFET. W = 0.7 µm , LG = 0.82 µm, and
VDS = 1.5 V.

Figure 4.4: Typical DC transfer characteristics for a control SOI TFET. W = 0.7 µm, LG = 10 µm, and
VDS = 1.5 V.
CHAPTER 4. ERBIUM TRAP ASSISTED TFET 49

Figure 4.5: Temperature dependent DC transfer characteristics for an Er-TATFET from 77K to 300K. W
= 0.7 µm, LG = 0.82 µm, and VDS = 1.5 V.

Figure 4.6: Temperature dependent DC transfer characteristics for a p-i-n control TFET from 77K to
295K. W = 0.7 µm, LG = 10 µm, and VDS = 1.5 V.
CHAPTER 4. ERBIUM TRAP ASSISTED TFET 50

Figs. 4.3 and 4.4 show typical DC transfer characteristics (ID (VGS ) vs. VGS ) for an
n-channel Er-TATFET and a control SOI TFET. |IG | > |ID | at lower biases is most likely
due to the aggressively thin gate oxide. While strong capacitive coupling to the channel
is necessary for good control of the tunneling junction, an aggressively thin gate oxide will
”leak” gate current to the channel via direct tunneling and Fowler-Nordheim tunneling.[1]
An obvious disadvantage for silicon based TFETs is the relatively large bandgap of silicon
(1.12 eV at room temperature) requiring a larger operating voltage to achieve an adequate
ION .
Figs. 4.5 and 4.6 show the temperature dependent characteristics of an Er-TATFET.
ID in the on-state decreases with temperature due in part to the lower thermal generation
of carriers in the depleted region of the active area. Additionally, dopants begin freeze-
out in Si at temperatures below 200K which reduces the active carrier concentrations. For
some measurements, ID did not decrease monotonically with temperature due to variable
contact resistance related to difficulty in probing the device pads at lower temperatures. The
subthreshold swing (SS) appears to show little dependence on temperature, verifying that
BTBT has a weak dependence on temperature.
Due to the low yield of fabricated devices, temperature dependent measurements were
conducted for only six TFETs: two p-i-n control TFETs and four Er-TATFETs. Table 4.1
lists dimensions and labels the transistors reported in this section. Variability across devices
(e.g., 10−8 A/µm ≤ ION ≤ 10−6 A/µm) prevents a direct comparison of I-V characteristics.

TFET W (µm) L (µm) Type

T1 0.7 5 p-i-n Control
T2 0.7 10 p-i-n Control
T3 0.7 2 Er-TATFET
T4 10 2 Er-TATFET
T5 0.7 0.76 Er-TATFET
T6 0.7 0.82 Er-TATFET
Table 4.1: Transistor dimensions for control and experimental devices.

Comparing Figs. 4.5 and 4.6, the SS for the Er-TATFET shows a greater sensitivity with
temperature whereas the SS for the control TFET is relatively insensitive to an increase in
temperature. This is not unexpected for a transistor at elevated temperatures with deep level
traps near the source. Figs. 4.7 and 4.8 show how the SS changes with the drain current for
an Er-TATFET and a control TFET, respectively. Qualitatively, Fig. 4.7 shows a greater
temperature sensitivity for an Er-TATFET SS that is more readily apparent, especially at
lower currents and higher temperatures. Direct quantitative comparisons of SS may prove
misleading due to the variability observed across devices. Interestingly, the Er-TATFET SS
improves as the temperature decreases and the temperature sensitivity decreases for T ≤
200K. This validates the experimental design hypothesis that a lower temperature can
CHAPTER 4. ERBIUM TRAP ASSISTED TFET 51

Figure 4.7: SS shown as a function of ID for a range of temperatures for a TFET with Er trap states near
the source. SS degrades with increasing temperatures, especially at lower drain current.

Figure 4.8: SS shown as a function of ID for a range of temperatures for a control TFET. SS remains
relatively insensitive to increasing temperatures.
CHAPTER 4. ERBIUM TRAP ASSISTED TFET 52

reduce the thermal excitation generation current due to the trap states and partially isolate
behavior of the traps at low temperature.
EA calculated for the p-i-n control TFETs over a temperature range of 77K-300K is pre-
sented in Fig. 4.9. EA for the control TFETs remains low from weak to strong inversion.
The EA calculated for all six TFETs for 77K ≤ T ≤ 200K is plotted in Fig. 4.10 as function
of the drain current at 175K (close to the middle of the temperature range for this experi-
ment). Calculating EA for T ≤ 200K helps insure that any quantitative comparison of EA
between control and experimental devices isolates the role of trap states with minimal ther-
mal generation current. Fig. 4.10 shows that the incorporation of a nominal concentration
of Er trap states in Si slightly lowers EA for BTBT in a transistor in weak inversion.

Figure 4.9: EA shown as a function of ID calculated for temperature 77K ≤ T ≤ 200K for p-i-n control
TFETs. A low EA validates a weak temperature dependence for BTBT.
CHAPTER 4. ERBIUM TRAP ASSISTED TFET 53

Figure 4.10: EA shown as a function of ID for comparison across devices. The independent variable is
chosen to be ID (T = 175K)) for TFET. For small ranges of ID in the subthreshold region, Er-TATFETs
exhibit a slightly lower EA (closed symbols) in comparison to EA for p-i-n control TFETs with no Er traps
(open symbols).

4.4 Conclusion
Isolating the role of a single trap in a large device through electrical characterization requires
a prohibitively low current measurement. Targeting an impurity trap concentration near the
maximum observed limit for electronically active Er in Si should improve the signal compared
to isolated trap states, though a higher concentration may also alter the trap properties.[2]
It has been noted that the properties of traps in a semiconductor are dependent on the
proximity to nearby trap states, the doping polarity of the semiconductor, and the thermal
processing steps subsequent to the formation of the trap state.[3] Qualitatively, this makes
sense: if a single trap state interrupts the periodicity of the semiconductor crystal, then if
follows that traps in close proximity further interrupt this periodicity.
As a thought experiment, one could imagine a ’trap state’ concentration so great that a
mini-band of delocalized states is formed within the band gap of the semiconductor (a goal
for exotic materials research for photovoltaics).[4, 5] If the presence of a miniband within the
band gap significantly reduces the effective energy band gap for tunneling, then a natural
conclusion to this thought experiment is to use a lower bandgap material at the tunneling
junction. The advantage of a heterostructure is that it can lower the effective tunneling
bandgap and so increase the tunneling current (ION for a TFET). In short, a TFET design
CHAPTER 4. ERBIUM TRAP ASSISTED TFET 54

Figure 4.11: (a) A substantially high concentration of electronically active traps states present in the
tunneling junction could form a quasi-continuous third band within the bandgap of the semiconductor. (b)
In the context of BTBT junction design, a lower bandgap material should provide a cleaner and more efficient
tunneling path.

should necessarily incorporate strong electrostatic control so that a reduced effective bandgap
can be employed in the source without sacrificing off-state leakage.
 55

Bibliography

[1] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. Wiley, 1981.

[2] A. Polman, G. N. van den Hoven, J. S. Custer, J. H. Shin, R. Serna, and P. F. A.
Alkemade, “Erbium in crystal silicon: optical activation, excitation, and concentration
limits,” Journal of Applied Physics, vol. 77, no. 3, pp. 1256–1262, 1995. doi: 10.1063/
1.358927. [Online]. Available: http://link.aip.org/link/?JAP/77/1256/1.
[3] A. G. Milnes, Deep Impurities in Semiconductors. New York: Wiley, Oct. 1973.
[4] M. A. Green, “Third generation photovoltaics: ultra-high conversion efficiency at low
cost,” Progress in Photovoltaics: Research and Applications, vol. 9, no. 2, pp. 123–135,
2001, issn: 1099-159X. doi: 10.1002/pip.360. [Online]. Available: http://dx.doi.
org/10.1002/pip.360.
[5] K. M. Yu, W. Walukiewicz, J. Wu, W. Shan, J. W. Beeman, M. A. Scarpulla, O. D.
Dubon, and P. Becla, “Diluted II-VI oxide semiconductors with multiple band gaps,”
Phys. Rev. Lett., vol. 91, p. 246 403, 24 Dec. 2003. doi: 10.1103/PhysRevLett.91.
246403. [Online]. Available: http://link.aps.org/doi/10.1103/PhysRevLett.91.
246403.
 56

Chapter 5

Design Optimization of Homojunction

TFETs with Back Biasing

5.1 Introduction
One target metric for any solid state switching device is a large ION /IOFF current ratio. Since
the steepest switching for a band-to-band tunneling (BTBT) transistor occurs at lower cur-
rent (see equation 1.3 and Figs. 1 and 4 in [1]), minimizing leakage current and maintaining
a low IOFF is necessary in order to observe a steep subthreshold slope (SS). Strong electro-
static control over the entire active region of a TFET is then necessary to mitigate off-state
leakage and maintain a low IOFF . A narrow tunneling barrier width at the onset of tunneling
and a large tunneling area both act to increase ION . Increasing the tunneling area can be
accomplished by parallel band bending (or parallel band-to-band overlap) across the width
of the tunneling junction. The SS for a TFET with a large area BTBT junction is then
limited by the steepness of the density of states energy distribution (provided IOFF remains
low).
Various TFET structures have been proposed to improve upon early planar gated reverse-
biased p-i-n diode designs. These designs often increase the fabrication complexity. (For
example: heterostructures, compound semiconductor materials, quantum confinement for
a density-of-states cutoff, or an asymmetric bi-layer structure.[2–4]) To maintain a simple
design approach for a TFET, this chapter explores a planar homojunction design for ease of
manufacturability.
An initial investigation of a planar p-i-n silicon-on-insulator (SOI) TFET structure
showed that a reverse back bias (VB < 0 V) can improve ION /IOFF .[5] An SOI substrate
allows for the application of a static reverse back-side bias (throughout the DC transfer
characteristic) which enhances the vertical component of BTBT. Figs. 5.1 and 5.2 show a
>50% improvement in ION /IOFF for VB = -3 V. The SOI TFET structure was optimized at
VB = 0 V. As reported in [6], reducing the semiconductor body thickness improves the gate
CHAPTER 5. DESIGN OPTIMIZATION OF HOMOJUNCTION TFETS WITH BACK
BIASING 57
control provided that tBODY remains large enough to avoid quantum conofinement effects.1
A sufficiently thin tBODY allows for a fully depleted active area and also reduces the ther-
mal generation-recombination current for a reverse biased p-i-n diode TFET.[7] Since the
benefit of a static reverse back bias should be transferrable to a lower bandgap material, a
germanium-on-insulator (GeOI) TFET design study is presented in the remaining sections
of this chapter.

Figure 5.1: Simulated SOI TFET ID (VGS ) with (open squares) and without (filled squares) back bias.
SS (VGS ) with (open squares) and without (filled squares) a reverse back bias. The lefthand y-axis corre-
sponds to the ID -VGS transfer characteristic and the righthand y-axis corresponds to the SS.

1
For a thin semiconductor, the bandgap increases with increasing quantum confinement.
CHAPTER 5. DESIGN OPTIMIZATION OF HOMOJUNCTION TFETS WITH BACK
BIASING 58

Figure 5.2: ION /IOFF for two different constant current IOFF values. In both cases, ION /IOFF improves
with reverse back bias with a greater effect for a lower IOFF .

5.2 Simulation Structure to Investigate Lower Eg

Materials for Planar Homojunction TFET
Fig. 5.3(a) shows a schematic diagram of the planar GeOI TFET design simulated in this
study. The net doping profiles within the semiconductor layer along the A-A’ cutline are
illustrated in Fig. 5.3(b), for two TFET source profile designs. One has a maximum p-type
source dopant concentration of 2·1019 cm−3 aligned to the gate edge, and a narrow Gaussian
source doping profile that corresponds to a gradient of 1 nm/dec; this is heretofore referred
to as the gate-aligned (GA) source design. The other has a maximum p-type source dopant
concentration of 4·1019 cm−3 offset from the gate edge by 10 nm, and a wide Gaussian source
doping profile that corresponds to a gradient of 20 nm/dec; this is heretofore referred to as
the gate-overlapped (GO) source design. As will be shown below, the GA source design is
optimal if VB = 0 V, but the GO source design is optimal if VB = -1.7 V.

Fixed Parameters
The default value for the gate length (LG ) is 30 nm to avoid significant short-channel effects,
as will be discussed below. The other fixed design parameters are chosen to achieve good
electrostatic integrity: the Ge thickness (TGe ) is 10 nm; the gate dielectric has an equivalent
oxide thickness of 0.8 nm, and the buried oxide (BOX) layer is 10 nm thick. The gate-sidewall
CHAPTER 5. DESIGN OPTIMIZATION OF HOMOJUNCTION TFETS WITH BACK
BIASING 59

Figure 5.3: (a) Schematic cross-section of an n-channel planar GeOI TFET. A-A is the cutline for which
the absolute value of the net dopant concentration profile is shown in (b). (b) Comparison of the net doping
profiles for a gate-overlapped (GO) source design (solid line) and a gate-aligned (GA) source design (dashed
line). The center of the channel region is located at x = 0 nm.

spacers are comprised of an inner 5-nm-thick silicon-dioxide layer and an outer 15-nm-thick
silicon-nitride layer. The Ge channel region is lightly doped p-type at 1015 cm−3 . The gate
material is metallic with a work function of 4.0 eV. Ohmic contacts to the source and drain
regions (each 30 nm long) are made along the upper Ge surfaces outside of the spacers. The
underlying substrate is p-type Si with a 1019 cm−3 dopant concentration. The n-type drain
has a maximum dopant concentration of 4·1018 cm−3 that is offset from the edge of the gate
by 10 nm, and a Gaussian doping profile that corresponds to a gradient of 5 nm/dec (see
Fig. 5.3(b)). This drain design was found to be optimal for minimizing off-state leakage
without degrading ION /IOFF , for VDD = 0.25 V and VB = 0 V.

Variable Parameters
The maximum source dopant concentration, NSRC , was varied from 1·1018 cm−3 to 1·1020
cm−3 in this study. The source doping profile decays as a Gaussian function toward the
channel region. The gate-to-source overlap, LOV,S , is defined as the distance from the gate
CHAPTER 5. DESIGN OPTIMIZATION OF HOMOJUNCTION TFETS WITH BACK
BIASING 60
edge to the position where the Gaussian decay begins. (If LOV,S is negative, the source doping
profile begins decaying from a position to the left of the gate edge. If LOV,S is positive, the
source doping profile begins decaying from a position to the right of the gate edge, underneath
the gate.) LOV,S was varied from -14 nm to 6 nm, and the doping gradient (DG) was varied
from 1 nm/dec to 22 nm/dec, in this study. The three source design parameters (NSRC ,
LOV,S , and DG), as well as the body thickness TGe , influence the location and size of the
tunneling region and thereby ION /IOFF .

Simulation
Synopsys TCAD software was used to study the performance of GeOI TFETs via 2D de-
vice simulations. Sentaurus Structure Editor was used to define the TFET structure, and
Sentaurus Device was used to simulate device operation using a dynamic non-local BTBT
model based on Kane’s model.[8] Equation 1.3 in chapter 1 represents a simplified version of
Kane’s model. The properties of Ge are well characterized, so the default Ge material param-
eters were used in this work: A = 2.8·1015 cm−3 s−1 , and B = 1.9·107 V/cm. The dynamic
non-local BTBT model has been demonstrated to be in good agreement with experimental
results.[9]

5.3 Planar GeOI TFET Performance Enhancement

via Back Bias
Gate Aligned and Gate Overlapped Designs
ION /IOFF is the primary figure of merit used to assess the effect of the source doping profile
parameters for TFETs in this study. ION is defined to be the drain current, ID , at VGS -
VOFF = 0.25 V for VDS = 0.25 V, where VOFF is defined to be the value of the gate-to-source
voltage (VGS ) that corresponds to ID = IOFF = 100 fA/µm. (In other words, it is assumed
that, in practice, gate work function engineering and delta doping can be used to tune VT ,
as for a MOSFET, so that VOFF = 0 V.)
Fig. 5.4 shows ION /IOFF contours and highlights the dependence of ION /IOFF on LOV,S
and the DG. Contours are presented for two values of NSRC , Fig. 5.4(a) represents NSRC
= 2·1019 cm−3 with VB = 0 V and Fig. 5.4(b) represents NSRC = 4·1019 cm−3 with VB =
-1.7 V. These peak doping concentrations in the source correspond to the optimized GA and
GO source designs. The hatched region in Fig. 5.4(a) indicates the range of LOV,S and DG
combinations that result in IOFF > 100 fA/µm due to the short-channel effect.
Fig. 5.4(a) shows that for VB = 0 V, the optimal source design is the GA profile (i.e.
provides for the highest ION /IOFF ), since the contours peak when LOV,S is near 0 nm and
the DG is close to 1 nm/dec. (This is representative of the trend seen for the entire range of
NSRC values studied in this work, when VB = 0 V.) Note that the design window for optimal
performance is relatively narrow. This is because tunneling occurs primarily from the GA
CHAPTER 5. DESIGN OPTIMIZATION OF HOMOJUNCTION TFETS WITH BACK
BIASING 61
source region to the channel inversion layer, so that it is highly sensitive to the alignment
between the source-channel junction and the gate edge: if the gate underlaps the source,
then gate coupling to the channel at the source junction is degraded; if the gate overlaps the
source, then the source depletion width (hence tunneling distance) is increased.
Fig. 5.4(b) shows that the GO source design is optimal when VB = -1.7 V, since the
contours peak at larger values of the DG. (If the DG·1 dec > -LOV,S then the source doping
profile extends underneath the gate electrode, as in Fig. 5.3(b)). Note that the design window
for optimal performance is relatively wide. This is because tunneling occurs primarily within
the GO source region, so that ION is largely dependent on the extent of the gate-to-source
overlap: many combinations of the DG and LOV,S result in a similar overlap and hence
comparable ION ; ION falls off with increasing LOV,S when the short-channel effect becomes
significant.

Figure 5.4: Simulated ION /IOFF contour plots showing how GeOI TFET performance depends on the
source doping gradient and the gate-to-source overlap, for optimized peak source profile concentrations. (a)
NSRC = 2·1019 cm−3 and VB = 0 V, (b) NSRC = 4·1019 cm−3 and VB = -1.7 V.

As shown in Fig. 5.5, reverse back-biasing is beneficial for both source designs (using the
doping profiles optimized for LG = 30 nm), but more so for the GO design so that it becomes
superior to the GA design when VB < -0.25 V. ION /IOFF reaches a peak at VB = -1.7 V for
the GO design, whereas it does not reach a peak for the GA design within the range of VB
values studied. To elucidate the reasons for this, Fig. 5.6 shows log-scale contour plots of
the BTBT generation rate at VGS - VOFF = 0.25 V and VDS = 0.25 V, for four cases: the GA
design and the GO design each at VB = 0 V and VB = -1.7 V. The dashed line in each plot
indicates the horizontal position of the gate edge. The lower contours which extend to the
left beyond the gate edge indicate the hole generation rate, while the upper contours which
CHAPTER 5. DESIGN OPTIMIZATION OF HOMOJUNCTION TFETS WITH BACK
BIASING 62

Figure 5.5: Simulated impact of back bias voltage on ION /IOFF for the two GeOI TFET designs: gate-
aligned (GA) source and gate-overlapped (GO) source.

extend to the right under the gate electrode indicate the electron generation rate. For the
GA design (Figs. 5.6(a) and 5.6(b)), it can be seen that tunneling occurs primarily from the
source region to the channel inversion layer; the application of a reverse back-bias enhances
the vertical component of the electric field and thereby improves ION /IOFF . For the GO
design, it can be seen that tunneling occurs primarily within the overlapped source region.
With zero back bias, the GO design serves as poorly gated Zener diode (Fig. 5.6(c)). Since
reverse back-biasing enhances the vertical component of the electric field, resulting in BTBT
over a relatively wide region within the source underneath the gate electrode; the larger
tunneling area results in larger ION for the reverse-back-biased GO design (Fig. 5.6(d)).
For a fixed value of LG and a given drain doping profile, ION /IOFF for the GO design
reaches a peak near VB = -1.7 V. This is because a significant hole accumulation region forms
near the drain junction and thereby introduces significant series resistance which decreases
ION for VB < -1.7 V. (Although a similar peak is not observed for the GA design within the
range of VB values studied, increasing drain-side series resistance should eventually limit the
improvement in ION /IOFF for this design as well.) Further optimization of the drain doping
profile may lead to greater ION /IOFF improvement for large reverse back-bias voltages.
Fig. 5.7 compares the transfer characteristics for the two optimized source designs, with
and without reverse back-biasing. The GA design (optimized at NSRC = 2·1019 cm−3 , LOV,S
= 0 nm, and DG = 1 nm/dec) achieves ION /IOFF = 3.26·105 at VB = 0 V and ION /IOFF
= 1.03·106 at VB = -1.7 V, representing more than 3× improvement with reverse back-
CHAPTER 5. DESIGN OPTIMIZATION OF HOMOJUNCTION TFETS WITH BACK
BIASING 63

Figure 5.6: Simulated contour plots for GeOI TFET on-state (VGS - VOFF = 0.25 V, VDS = 0.25 V) BTBT
rate (log scale, arbitrary units) contour plots for (a) GA source design with VB = 0 V, (b) GA source design
with VB = -1.7 V, (c) GO source design with VB = 0 V, (d) GO source design with VB = -1.7 V. The arrows
indicate the general direction of tunneling electrons.

biasing. The GO design (optimized at NSRC = 4·1019 cm−3 , LOV,S = -10 nm, and DG = 20
nm/dec) achieves ION /IOFF = 1.22·105 at VB = 0 V and ION /IOFF = 4.24·106 at VB = -1.7
V, representing more than 34× improvement with reverse back-biasing. These results affirm
that the GA design is superior when there is no applied back bias (solid dark curve in Fig.
5.7), and that the GO design becomes superior if a significant reverse back-bias is applied
(grey dotted line in Fig. 5.7).
The off-state leakage current is slightly larger with VB = -1.7 V for both the GA and
GO designs, due to an increase in the volume of the space-charge region resulting in more
recombination- generation current. It should be noted that the turn-on voltage (VOFF ) in-
creases and that SS becomes steeper with reverse back-biasing. This is somewhat analogous
to the increase in VT and improved electrostatic integrity of a thin-body MOSFET with
reverse back-biasing.[10] For the GA design, a larger gate voltage is required to form an
inversion layer in the lightly doped channel region (to which carriers tunnel from the source
region) when a reverse back-bias is applied, and an enhanced electric field in the on state
provides for greater BTBT current. For the GO design, a larger gate voltage is also required
to invert the Ge surface (to allow BTBT to occur within the source region); however, since
the source has a graded doping profile, this increase in required gate voltage is not uniform
across the lateral extent of the source - it increases with decreasing dopant concentration.
Since a larger gate voltage is required to invert the surface of a more heavily doped semi-
conductor when VB = 0 V, the effect of the reverse back-bias is to induce a graded shift in
turn-on voltage so that band overlap occurs more uniformly across the source region and
hence the TFET switches more abruptly.
CHAPTER 5. DESIGN OPTIMIZATION OF HOMOJUNCTION TFETS WITH BACK
BIASING 64

Figure 5.7: Comparison of simulated GeOI TFET transfer characteristics for the GA and GO source
designs, with and without reverse back-biasing.

Short Channel Effect Mitigation

Fig. 5.8 shows how GeOI TFET performance depends on LG for the GA and GO source
designs optimized for LG = 30 nm. Note that there is no gate-length dependence for LG >
30 nm; in this regime, the drain bias has little influence on the BTBT rate. As LG decreases
below 30 nm, the lateral electric field induced at the tunneling junction by the drain voltage
increases sufficiently to cause BTBT to occur at a smaller gate voltage. This is manifested
as a decrease in VOFF with decreasing LG (Fig. 5.8(a), VB = 0 V). As a result, the influence
of the gate voltage is diminished, i.e. SS becomes less steep and hence ION /IOFF decreases
(Fig. 5.8(b), VB = 0 V). It is interesting to note that, although the GO design results in a
much shorter electrical channel length, degradation in ION /IOFF occurs only slightly earlier
(i.e. beginning at slightly longer LG ) because BTBT occurs in a more vertical direction so
that drain-induced BTBT is not much more significant than for the GA design, as can be
deduced from the comparison of drain-induced BTBT effect (DIBE) in Fig. 5.9.
Reverse back-biasing provides for more dominant gate control of the BTBT current and
thereby reduces the short-channel effect. As LG decreases below 30 nm, the average p-type
doping underneath the gate electrode increases so that the gate voltage required to induce
BTBT (i.e., VOFF ) increases. Also, for the GO design, ION /IOFF decreases with decreasing
LG due to decreased tunneling area. Re-optimizing the source and drain doping profiles for
CHAPTER 5. DESIGN OPTIMIZATION OF HOMOJUNCTION TFETS WITH BACK
BIASING 65

Figure 5.8: Dependence of (a) VOFF and (b) ION /IOFF on LG ≥ 10 nm for GeOI TFETs with gate-
overlapped (GO) or gate-aligned (GA) source designs, with or without reverse back bias. VOFF is defined as
VGS when ID = 100 fA/µm. Reverse back biasing mitigates the short channel effect and therefore improves
scalability. ION /IOFF (VB = -1.7 V) decreases with decreasing LG for the GO design due to a corresponding
decrease in the gate area overlapping the tunneling area. VOFF and ION /IOFF are not defined when ID never
falls below 100 fA/µm.

each value of LG < 30 nm can help to mitigate these short-channel effects.

Source Design Optimization for Vertical Tunneling

From Fig. 5.6 it can be deduced that the highest ION is achieved when BTBT occurs within
the source (i.e., in a more vertical direction), because the tunneling area can be readily
increased by increasing the gate-to-source overlap and/or applying a reverse back-bias, in
this case. Many combinations of DG and LOV,S result in the same overlap, but a closer
examination of Fig. 5.4(b) reveals that higher ION /IOFF is achieved with a more graded
source doping profile when a significant reverse back-bias is applied. For a fixed value of
DG·1 dec + LOV,S > 0 nm, higher ION /IOFF is achieved with larger DG rather than with
larger LOV,S , (i.e., with a graded source rather than with a uniform source). This is because
lighter source doping at the channel junction reduces the likelihood of lateral (source-to-
channel) BTBT which is associated with worse SS (ref. Fig. 5.7). To highlight this point,
the impact of NSRC is shown in Fig. 5.10, for the GA and GO source designs as well as a
CHAPTER 5. DESIGN OPTIMIZATION OF HOMOJUNCTION TFETS WITH BACK
BIASING 66

Figure 5.9: Comparison of the drain induced BTBT effect (DIBE) on a log scale for GA vs. GO source
designs, at various values of back bias voltage. DIBE is the change in VOFF (in mV) for 0.025 V ≤ VDS ≤
0.25 V. For LG = 30 nm, both designs show low DIBE (which disappears altogether for the GO design at VB
= -1.7 V). For LG = 10 nm, reverse back-biasing mitigates DIBE more effectively for the vertical tunneling
(GO) design than for the lateral tunneling (GA) design, since the latter is inherently more susceptible to the
influence of the drain bias on the lateral electric field.

uniformly doped source design with LOV,S = 10 nm and a DG = 1 nm/dec. (LG = 60 nm

in this figure only, to avoid the short channel effect for the uniformly doped source design.)
ION /IOFF for the uniformly doped source design dips below that for the GO source design
near NSRC = 1·1019 cm−3 as BTBT transitions from tunneling primarily within the source
(as for the GO source design) to tunneling primarily from the source to the channel (as for
the GA source design).
Fig. 5.11 shows the simulated GeOI TFET output characteristics for the GA and GO
source designs, with and without reverse back-biasing. The small-signal output resistance ro
is taken to be the inverse slope of a best-fit line from 0.20 V ≤ VDS ≤ 0.25 V for VGS − VOFF
= 0.25 V. Reverse back-biasing depletes the drain offset region, forming a barrier to electron
flow; this barrier (rather than BTBT at the source) is modulated by the drain bias, so that
ro is reduced when VB = -1.7 V. Despite this, intrinsic gain (gm ro , evaluated at VGS − VOFF
= VDS = 0.25 V) remains well above 1, decreasing from 13.0 to 5.7 for the GA design and
from 20.1 to 9.1 for the GO design when VB is changed from 0 V to -1.7 V. As can be seen
in Fig. 5.11, reverse back-biasing improves the linearity of the ID -VD characteristic at low
values of VDS , which is consistent with a reduction in DIBE (see Fig. 5.9).
CHAPTER 5. DESIGN OPTIMIZATION OF HOMOJUNCTION TFETS WITH BACK
BIASING 67

Figure 5.10: Impact of peak source dopant concentration (NSRC ) on ION /IOFF , for GeOI TFETs with
GA, GO, or uniform source (LOV,S = 10 nm and DG = 1 nm/dec) design. LG = 60 nm to avoid the short
channel effect. The uniformly doped source design transitions from tunneling within the source to tunneling
from source to channel near NSRC = 1019 cm−3 . The GO design outperforms the other designs at VB = -1.7
V, for NSRC ≥ 1019 cm−3 .

TGe Dependence
TGe should be sufficiently thick so as to avoid fully vertically depleting the source region
underneath the gate if vertical BTBT within the source is desired. (Also, if TGe is too
thin, quantum confinement effects can reduce the density of states for tunneling, even if
lateral BTBT from the source to the channel is desired.) For a source doping level of 2·1019
cm−3 , TGe should be at least 10 nm to avoid full vertical depletion. As shown in Fig. 5.12,
reverse-biased diode leakage is adequately suppressed at this thickness.
CHAPTER 5. DESIGN OPTIMIZATION OF HOMOJUNCTION TFETS WITH BACK
BIASING 68

Figure 5.11: Comparison of output current normalized to the maximum value at VGS − VOFF = 0.25 V
and VDS = 0.25 V, as a function of the drain-to-source voltage. The output characteristics have been offset
for clarity.

Figure 5.12: Off-state leakage current (ID at VGS = 0 V) in a GeOI TFET as a function of the Ge thickness,
for the different source designs with and without reverse back-biasing. Reverse diode leakage current (due to
BTBT at the drain junction) increases linearly with the diode area, and is dramatically enhanced by reverse
back-biasing to increase the electric field.
CHAPTER 5. DESIGN OPTIMIZATION OF HOMOJUNCTION TFETS WITH BACK
BIASING 69
5.4 Conclusion
With a proper design of the source doping profile, an optimal reverse back bias increases
the vertical tunneling component and results in greater than 30× enhancement in ION /IOFF
for a GeOI TFET. Reverse back bias for a lateral tunneling design, however, only yields
approximately 3× enhancement.
For the reverse back-biased vertical tunneling design, a graded source doping profile
provides for superior performance due to reduced short channel effect and more uniform band
overlap across the lateral extent of the source region. The results of this study indicate that
reverse back-biasing is a more effective performance booster for a GeOI TFET than for an
SOI TFET.[5] This is because band overlap can be induced across a shorter distance within
Ge, because of its smaller bandgap, so that more vertical tunneling can be induced with
reverse back-biasing in a thin-body Ge TFET vs. a thin-body Si TFET. (Likewise, the benefit
of reverse back-biasing should be greater for semiconductor materials with even smaller
bandgap.) Finally, reverse back-biasing is also beneficial for improving TFET scalability,
particularly if the source and drain doping profiles are co-optimized together with the gate
length.
 70

Bibliography

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Electron Device Letters, IEEE, vol. 27, no. 4, pp. 297 –300, Apr. 2006, issn: 0741-3106.
doi: 10.1109/LED.2006.871855.
[2] S. H. Kim, S. Agarwal, Z. Jacobson, P. Matheu, C. Hu, and T.-J. Liu, “Tunnel field
effect transistor with raised germanium source,” Electron Device Letters, IEEE, vol. 31,
no. 10, pp. 1107 –1109, Oct. 2010, issn: 0741-3106. doi: 10.1109/LED.2010.2061214.
[3] D. Kazazis, P. Jannaty, A. Zaslavsky, C. L. Royer, C. Tabone, L. Clavelier, and
S. Cristoloveanu, “Tunneling field-effect transistor with epitaxial junction in thin
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?APL/94/263508/1.
[4] L. Lattanzio, L. De Michielis, and A. Ionescu, “Complementary germanium electron-
hole bilayer tunnel FET for sub-0.5-V operation,” Electron Device Letters, IEEE, vol.
33, no. 2, pp. 167 –169, Feb. 2012, issn: 0741-3106. doi: 10.1109/LED.2011.2175898.
[5] A. Guo, P. Matheu, and T.-J. K. Liu, “SOI TFET ION /IOFF enhancement via back
biasing,” IEEE Transactions on Electron Devices, vol. 58, no. 10, pp. 3283 –3285, Oct.
2011, issn: 0018-9383. doi: 10.1109/TED.2011.2161480.
[6] E.-H. Toh, G. H. Wang, G. Samudra, and Y.-C. Yeo, “Device physics and design
of double-gate tunneling field-effect transistor by silicon film thickness optimization,”
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[7] T.-J. K. Liu, P. Matheu, Z. Jacobson, and S. H. Kim, “Steep-subthreshold-slope devices
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10.1109/SOI.2011.6081702.
[8] E. O. Kane, “Theory of tunneling,” Journal of Applied Physics, vol. 32, no. 1, pp. 83–
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?JAP/32/83/1.
[9] S. H. Kim, H. Kam, C. Hu, and T.-J. K. Liu, “Germanium-source tunnel field effect
transistors with record high ION /IOFF ,” in VLSI Technology, 2009 Symposium on, Jun.
2009, pp. 178 –179.
BIBLIOGRAPHY 71

[10] S. Balasubramanian, “Nanoscale thin-body MOSFETs: Technology and applications,”

Ph.D. University of California, Berkeley, 2006.
 72

Chapter 6

Conclusion

6.1 Summary of Contributions

Detailed electrical characterization for an enhanced Schottky-Barrier MOSFET (SB-
MOSFET) confirmed a steep subthreshold swing (SS) at low current with an operating
voltage window of 0.5 V. This enhanced SB-MOSFET structure utilized a steep doping pro-
file produced by dopant segregation from silicide. Silicidation processes most likely produce
a diffusion tail of metal impurity atoms beginning near the silicide/silicon interface and ex-
tending into the active region of the device.[1, 2] Despite the sub- kBqT ln (10) SS, electrostatic
simulation of the structure for the same operating voltages did not indicate any band overlap
in the device. Temperature dependent I-V measurements in addition to back bias dependent
characterization suggest a plausible operating mechanism where electronic trap states aug-
ment the source injection of carriers with a combination of tunneling to trap states followed
by thermal excitation of the carriers to produce sub-60 mV/dec SS at room temperature.
To further explore the role of traps in close proximity to the band-to-band tunneling
(BTBT) junction, erbium (Er) impurity atoms exhibiting deep level electronic trap behavior
in Si were introduced near the tunneling junction of p+ poly-Ge/Si heterodiodes. Comparing
the activation energy, EA , of p+-i-n+ heterodiodes with and without Er trap states confirms
a previously documented energy level of Er in Si of EC − ET = 0.6 eV.[3, 4] Exploring the
role of traps for a p+-n+ tunneling heterodiode, however, was limited without a control
device for comparison or an accurate trap-assisted tunneling model for semiconductor device
simulation.
An additional investigation of the role of trap states in BTBT included testing Er-based
trap-assisted TFETs (Er-TATFETs) fabricated on an SOI substrate. Isolating the role of
trap states is possible by significantly reducing the thermal generation-recombination current
in the device. Low temperature measurements helped identify the temperature range over
which the thermal generation rate due to traps is dramatically reduced. Er-TATFETs show
a slightly lower EA compared to p-i-n control TFETs for T ≤ 200K over a range of operation
within the subthreshold regime.
CHAPTER 6. CONCLUSION 73

Finally, a reverse back bias applied to planar SOI or GeOI homojunction TFETs improves
ION /IOFF by increasing the vertical component of BTBT. A conventional source design for a
planar p-i-n TFET typically calls for a steeply graded doping profile in order to take advan-
tage of the large built-in electric field provided by a nearly abrupt doping profile. Applying
a reverse back bias (VB < 0 V for an n-channel TFET), however, dramatically relaxes the
source doping gradient design window for BTBT in Ge at low power supply voltages. A gate-
overlapped graded source doping profile with reverse back bias shows significant improvement
in ION /IOFF due to BTBT within the source rather than from the source to the channel (as
is the case for a gate-aligned abrupt source profile). The use of a source-optimized profile
with reverse back bias also mitigates short channel effects. Further improvement in ION /IOFF
and aggressive scaling may be possible by co-optimizing the source and drain doping profiles
with a static reverse back bias.

6.2 TFET Design Challenges

Many challenges likely need to be addressed for further TFET development. A partial list
below highlights some of the more fundamental problems.

ˆ Fabrication complexity
- Homojunction versus heterojunction
- Semiconductor materials choice
- Non-conventional planar processing techniques
- Asymmetry in device design

ˆ BTBT Junction Design

- Density of States (DOS) switching versus tunneling barrier width modulation

ˆ BTBT semiconductor device modeling

- Empirical BTBT models
- Infinitely sharp band edges

Fabrication Complexity
Historically, each technology node advancement in transistor development introduces at most
only a few “radical” changes to the design of the final product. (One example would be the
transition to an alternate gate dielectric material with a metal gate within one generation.)
The successful co-integration of TFETs with MOSFET technology will likely require simple
TFET designs using proven processing techniques and materials. BTBT within homojunc-
tions are advantageous due to the material simplicity whereas BTBT with heterojunctions
may not be economically viable. Introducing a compound semiconductor heterostructure
CHAPTER 6. CONCLUSION 74

(e.g., a quantum well structure) further complicates the processing requirements for non-
similar devices such as MOSFETs. Finally, the inherent doping (and sometimes structural)
asymmetry in TFETs places additional demands on lithographic patterning and wafer real
estate.

BTBT Junction Design

One very simple conceptual requirement for BTBT is that a carrier must originate from
an occupied state and tunnel to an unoccupied state. A BTBT junction design where the
tunneling current is modulated by changing the barrier width only changes the tunneling
probability and varying the channel potential beyond strong inversion is similar to a law
of diminishing returns. A perhaps better junction design would utilize a large number of
available tunneling states at turn-on rather than simply trying to increase the tunneling
probability.

Semiconductor Device Modeling for BTBT

Most device simulation BTBT models make use of empirical equations for calculation at
a grid point. While numerically efficient, this approach does not account for wavefunction
overlap. While improved BTBT models make a dynamic calculation of the tunneling di-
rection, the models still rely on simplified material fitting parameters and are not always
accurate. For example, despite the dynamic nonlocal BTBT model in Synopsys Sentaurus,
Esaki tunneling diode simulations still do not account for experimentally observed excess
current. Simulation results are optimistic due to the infinitely sharp band edges assumed
in the band structure model. As such, many TFET structures in Synopsys Sentaurus show
steeper switching than when studied using atomistic models and a non-equilibrium Green’s
function approach.

6.3 Concluding Remarks

Future research for TFETs most likely must address these challenges and more in order to
present statistically significant experimental results. Additionally, this field in general is in
dire need of co-fabricated complementary TFETs that outperform complementary MOS-
FETs on some level. Since the field of semiconductor device research is often tied to the
semiconductor industry, compelling results are often those where industry (and presumably
the consumer) stand to benefit.
 75

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44.1673.
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[Online]. Available: http://jjap.jsap.jp/link?JJAP/43/5166/.
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grown silicon,” Applied Physics Letters, vol. 72, no. 4, pp. 468–470, 1998. doi: 10.
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1.358927. [Online]. Available: http://link.aip.org/link/?JAP/77/1256/1.
 76

Appendix A

Appendix: Process Flow Template

A general template for a TFET process flow is included in this appendix. Process steps are
specific to the UC Berkeley Microlab and UC Berkeley Nanolab.
APPENDIX A. APPENDIX: PROCESS FLOW TEMPLATE 77

Step Process Name Process Specification Equipment Comment

1.00 SOI wafers 6 inch prime SOI wafers Tsi = 100nm
1.01 labeling Label with diamond scribe
SOI thickness
1.02 measurement All wafers nanoduv Tbox = 200nm
Tsoi Thinning
1.03 preclean piranha, 120C, 10 min, QDR + SRD sink6
1.04 dry oxidation 2DRYOXA, 900C, variable time tystar2
piranha, 120C, 10 min, QDR, 10:1 HF,
1.05 oxide strip variable time sink6 surface dewets
SOI thickness If Tsoi is too large, repeat dry oxidation
1.06 measurement process nanoduv Tsoi = 25-45nm
PM Marks (Necessary for ASML Alignment)
2.00 preclean piranha, 120C, 10 min, QDR + SRD sink6
2.01 PR coat HMDS prime + DUV PR, recipes 1/2/1 svgcoat6

2.02 litho combi reticle mask; 22 mJ/cm2, std foc asml

2.03 develop PEB + DUV develop recipe 1/1 svgdev6
2.04 inspect uvscope
2.05 hard bake recipe U uvbake
2.06 PM etch etch Tsoi ~1200 A target timed etch lam8
2.07 PR ash standard recipe (250C/2.5 min) matrix
2.08 clean piranha, 120C, 10 min, QDR + SRD sink8
coat with PR, run active exposure for record wafer
2.09 test PM marks alignment test asml quality
2.10 PR ash standard recipe (250C/2.5 min) matrix
Active Area Definition
3.00 clean piranha, 120C, 10 min, QDR + SRD sink8
3.01 PR coat HMDS prime + DUV PR, recipes 1/2/1 svgcoat6
device group active mask; variable
3.02 litho energy/focus asml
3.03 develop PEB + DUV develop recipe 1/1 svgdev6
3.04 inspect uvscope
3.05 hard bake recipe U uvbake
target etch thickness is Tsoi + 30% over
3.06 active etch etch lam8
3.07 PR ash standard recipe (250C/2.5 min) matrix
3.08 inspect uvscope
3.09 inspect profilometry asiq
3.10 inspect Tbox and Tsoi nanoduv
3.11 clean piranha, 120C, 10 min, QDR + SRD sink8
Gate Stack Formation
piranha, QDR, 25:1 fresh HF (right side,
4.00 preclean ~10s), QDR, SRD sink6
APPENDIX A. APPENDIX: PROCESS FLOW TEMPLATE 78

1GATEOXA; 850C for 70 sec; 11' to ramp sandwich with

4.01 gate oxidation to 900C; 20' anneal at 900C tystar1 dummies
poly-si sandwich with
4.02 deposition 10SDPLYA; 3 hrs 37 min; target 150nm tystar10 LTO dummies
4.03 inspect tystar1 dummy for tox sopra tox ~ 3nm

4.04 inspect tystar1 dummy for Dit sca Dit quite variable
4.05 inspect tystar10 dummy for tpoly nanoduv tpoly ~150 nm
Gate Definition
5.00 preclean piranha, 120C, 10 min, QDR + SRD sink8
5.01 PR coat HMDS prime + DUV PR, recipes 1/2/1 svgcoat6
device group gate mask; variable
5.02 litho energy/focus asml
5.03 develop PEB + DUV develop recipe 1/1 svgdev6
5.04 inspect uvscope
5.05 hard bake recipe U uvbake
target etch thickness is tpoly + 30% over
5.06 gate etch etch lam8
5.07 inspect ensure poly is gone uvscope
5.08 inspect measure Tbox nanoduv
5.09 PR ash standard recipe (250C/2.5 min) matrix
5.10 clean piranha, 120C, 10 min, QDR + SRD sink8
Spacer Definition
piranha, QDR, 25:1 HF (right side, <10s),
6.00 preclean QDR, SRD sink6
1GATEOXA; 850C for 70 sec; 11' to ramp sandwich with
6.01 re-oxidation to 900C; 20' anneal at 900C tystar1 dummies
sandwich with
6.02 SiN deposition 9SNITA, 3 min 10 sec, target 15nm tystar9 LTO dummies
6.03 inspect measure tox on a tystar1 dummy sopra
6.04 inspect measure tSiN on a tystar9 dummy nanoduv
etch tSiN target thickness + 10-20% over oxide left on top
6.05 spacer etch etch centura-mxp of Si
Asymmetric Source Implant
7.00 clean piranha, 120C, 10 min, QDR + SRD sink8
7.01 PR coat HMDS prime + DUV PR, recipes 1/2/1 svgcoat6
device group TFET mask source; variable
7.02 litho energy/focus asml
7.03 develop PEB + DUV develop recipe 1/1 svgdev6
7.04 inspect uvscope
7.05 hard bake recipe U uvbake

7.06 CoreSystems Dose 1.5E15/cm2; 20 keV; tilt = 7 for As send out

7.07 PR ash standard recipe (250C/2.5 min) matrix
7.08 clean piranha, 120C, 10 min, QDR + SRD sink8
APPENDIX A. APPENDIX: PROCESS FLOW TEMPLATE 79

7.09 preclean piranha, 100:1 HF for 10 s sink6

2LTANNLA; load at 400C; 550C/4hrs;
7.10 SPER unload at 375C tystar2
2nd Spacer (with LTO)
8.00 preclean piranha, 100:1 HF for 10 s sink6
sandwich with
8.01 LTO deposition 11SULTOA for 2' 15", target is 35nm tystar11 dummies
8.02 inspect measure tystar11 dummy for tLTO nanoduv
MXP-OX-VAR; 9.5 sec (ER ~30.5 A/s);
8.03 spacer etch 60/120sccm CH3F/Ar; 200 mT; 500W centura-mxp
Asymmetric Drain Implant
9.00 PR coat HMDS prime + DUV PR, recipes 1/2/1 svgcoat6
device group TFET mask source; variable
9.01 litho energy/focus asml
9.02 develop PEB + DUV develop recipe 1/1 svgdev6
9.03 inspect uvscope
9.04 hard bake recipe U uvbake
9.05 CoreSystems Dose 5E15/cm2; 10 keV; tilt = 7 for B send out
9.06 PR ash standard recipe (250C/2.5 min) matrix
9.07 clean piranha, 120C, 10 min, QDR + SRD sink8
9.08 preclean piranha, 100:1 HF for 10 s sink6
2LTANNLA; load at 400C; 550C/4hrs;
9.09 SPER unload at 375C tystar2