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AVLSI for vtu

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14 views

Module_4 (1)

AVLSI for vtu

Uploaded by

Akash
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Advanced VLSI(21EC71)

By
Dr. Parameshwara M. C.
Associate Professor & HoD, Department of ECE,
Vemana Institute of Technology, Koramangala,
Bengaluru-560034

Prof. Parameshwara M. C. Dept. of ECE, Vemana IT, Bangalore 1


MODULE-4
Procedural Statements and Routines:
Procedural statements,
Tasks, Functions and void functions,
Task and function overview,
Routine arguments, returning from a routine,
Local data storage, time values.
Connecting the test bench and design:
Separating the test bench and design,
The interface construct, Stimulus timing,
Interface driving and sampling,
System Verilog assertions.

Dept. of ECE, Vemana IT, Bangalore 2


Procedural Statements and Routines:
Procedural Statements:
• SystemVerilog adopts many operators and statements from C and C++.
• We can declare a loop variable inside a for loop.
• The increment ++ and decrement -- operators are available in both pre- and post- form.
• a label on a begin or fork statement can be used, you can put the same label on the matching end or join
statement.
• a label on other SystemVerilog end statements such as endmodule, endtask, endfunction can be used.

Dept. of ECE, Vemana IT, Bangalore 3


Procedural Statements and Routines:
Procedural Statements:

Dept. of ECE, Vemana IT, Bangalore 4


Procedural Statements and Routines:
Procedural Statements:
• Two new statements help with loops.
• First, if you are in a loop, but want to skip over rest of the statements and do the next iteration, use
continue.
• If you want to leave the loop immediately, use break.

Dept. of ECE, Vemana IT, Bangalore 5


Procedural Statements and Routines:
Tasks, Functions, and Void Functions
• Verilog makes a very clear differentiation between tasks and functions.
• The most important difference is that a task can consume time while a function cannot.
• Additionally, a Verilog function must return a value, and the value must be used, as in an assignment
statement.
• In SystemVerilog, if you want to call a function and ignore its return value, cast the result to void.

• If you have a SystemVerilog task that does not consume time, you should make it a void function
that is a function that does not return a value.

Dept. of ECE, Vemana IT, Bangalore 6


Procedural Statements and Routines:
Task and Function Overview
• SystemVerilog makes several small improvements to tasks and functions to make them look more
like C or C++ routines.
1. Routine begin...end removed
The task / endtask and function / endfunction keywords are enough to define the routine boundaries.

Dept. of ECE, Vemana IT, Bangalore 7


Procedural Statements and Routines:
Routine Arguments
Many of the SystemVerilog improvements for routine make it easier to declare arguments and expand
the ways you can pass values to and from a routine.
• C-style Routine Arguments
SystemVerilog and Verilog-2001 allow you to declare task and function arguments more cleanly and
with less repetition.

Dept. of ECE, Vemana IT, Bangalore 8


Procedural Statements and Routines:
Routine Arguments
Many of the SystemVerilog improvements for routine make it easier to declare arguments and expand
the ways you can pass values to and from a routine.
• Advanced Argument Types
In SystemVerilog, you can specify that an argument is passed by reference, rather than copying its
value. This argument type, ref, has several benefits over input, output, and inout. First, you can now
pass an array into a routine.

Dept. of ECE, Vemana IT, Bangalore 9


Procedural Statements and Routines:
Routine Arguments
Many of the SystemVerilog improvements for routine make it easier to declare arguments and expand
the ways you can pass values to and from a routine.
• Default Argument Values
In SystemVerilog you can specify a default value that is used if you leave out an argument in the call.

Dept. of ECE, Vemana IT, Bangalore 10


Procedural Statements and Routines:
Returning from a Routine
• SystemVerilog adds the return statement to make it easier for you to control the flow in your
routines.
• The following task needs to return early because of error checking. Otherwise, it would have to use
an else clause, that would cause more indentation and be harder to read.

Dept. of ECE, Vemana IT, Bangalore 11


Procedural Statements and Routines:
Local Data Storage
• In SystemVerilog, routines still use static storage by default, for both modules and program blocks.
You should always make program blocks (and their routines) use automatic storage by putting the
automatic keyword in the program statement.

• You can call this task multiple times concurrently, as the addr and expect_data arguments are stored
separately for each call. Without the automatic modifier, if you called wait_for_mem a second time
while the first was still waiting, the second call would overwrite the two arguments.

Dept. of ECE, Vemana IT, Bangalore 12


Procedural Statements and Routines:
Time Values
• SystemVerilog has several new constructs to allow you to unambiguously specify time values in your
system.
• Time units and precision
• Time literals
• When you rely on the ‘timescale compiler directive, you must compile the files in the proper order
to be sure all the delays use the proper scale and precision.
• The timeunit and timeprecision declarations eliminate this ambiguity by precisely specifying the
values for every module.

Dept. of ECE, Vemana IT, Bangalore 13


Procedural Statements and Routines:
Time Literals
• SystemVerilog allows you to unambiguously specify a time value plus units. Your code can use delays
such as 0.1ns or 20ps. Just remember to use timeunit and timeprecision or ‘timescale.
• You can even make even more time aware by using the classic Verilog $timeformat and $realtime
routines.

Dept. of ECE, Vemana IT, Bangalore 14

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