ELECTRONICS AND SUBJECT: CEC370

COMMUNICATION LOW POWER IC DESIGN

ENGINEERING

YEAR SEMESTER UNIT NO. : 01

III V FUNDAMENTALS OF LOW
POWER CIRCUITS

Downloadable at
Ms.G VIJAYAKUMARI,AP/ ECE
tiny.cc/npsb-elearning
 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

OUTLINE

Need for Low Power Circuit Design, Sources of Power Dissipation –

Switching Power Dissipation, Short Circuit Power Dissipation, Leakage
Power Dissipation, Glitching Power Dissipation, Short Channel Effects –
Drain Induced Barrier Lowering and Punch Through, Surface Scattering,
Velocity Saturation, Impact Ionization, Hot Electron Effect.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 2

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Need for Low Power Circuit Design

• The need for low-power design is also becoming a major issue in high-
performance digital systems, such as microprocessors, digital signal processors
(DSPs) and other applications.
• Increasing chip density and higher operating speed lead to the design of very
complex chips with high clock frequencies.
• If the clock frequency of the chip increases then the power dissipation of the
chip, and thus, the temperature, increase linearly.
• Since the dissipated heat must be removed effectively to keep the chip
temperature at an acceptable level, the cost of packaging, cooling and heat
removal becomes a significant factor.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 3

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Need for Low Power Circuit Design

• Several high-performance microprocessor chips designed in the early 1990s

(e.g., Intel Pentium, DEC Alpha, PowerPC) operate at clock frequencies in the
range of 100 to 300 MHz, and their typical power consumption is between 20
and 50 W.
• ULSI reliability is yet another concern which points to the need for low-power
design. There is a close correlation between the peak power dissipation of digital
circuits and reliability problems such as electro migration and hot-carrier induced
device degradation.
• Thermal stress caused by heat dissipation on chip is a major reliability concern.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 4

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Need for Low Power Circuit Design

•The methodologies which are used to achieve low power consumption in digital
systems span a wide range, from device/process level to algorithm level. Device
characteristics (e.g., threshold voltage), device geometries and interconnect properties
are significant factors in lowering the power consumption.
•Circuit-level measures such as the proper choice of circuit design styles, reduction of
the voltage swing and clocking strategies can be used to reduce power dissipation at
the transistor level.
•Architecture-level measures include smart power management of various system
blocks, utilization of pipelining and parallelism, and design of bus structures.
• Finally, the power consumed by the system can be reduced by a proper selection of
the data processing algorithms, specifically to minimize the number of switching
events for a given task.
UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 5
 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Sources of Power Dissipation

The average power dissipation in conventional CMOS digital circuits can be
classified into three main components,

(1)The dynamic (switching) power dissipation

(2)The short-circuit power dissipation and
(3)The leakage power dissipation.

If the system or chip includes circuits other than conventional CMOS gates that have
continuous current paths between the power supply and the ground, a fourth (static)
power component should also be considered

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 6

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Switching Power Dissipation

Switching Power Dissipation represents the power dissipation during a switching
event.
This means that the output node voltage of a CMOS logic gate makes a power
consuming transition.
In digital CMOS circuits, dynamic power is dissipated when energy is drawn from the
power supply to charge up the output node capacitance.
During the charge-up phase, the output node voltage typically makes a full transition
from 0 to VDD, and the energy used for the transition is relatively independent of the
function performed by the circuit.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 7

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Switching Power Dissipation

Two - input NOR gate drives two NAND gates, through interconnection lines.
The total capacitive load at the output of the NOR gate consists of
(1) The output capacitance of the gate itself
(2) The total interconnect capacitance, and
(3) The input capacitances of the driven gates.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 8

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Output capacitance:
The output capacitance of the gate consists mainly of the junction parasitic capacitances,
which are due to the drain diffusion regions of the MOS transistors in the circuit. So, the
size of the total drain diffusion area determines the amount of parasitic capacitance.

Total interconnect capacitance:

The interconnect lines between the gates contribute to the total interconnect capacitance.
Input capacitances:
The input capacitances are mainly due to gate oxide capacitances of the transistors
connected to the input terminal. Again, the amount of the gate oxide capacitance is
determined primarily by the gate area of each transistor.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 9

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Generic representation of a CMOS logic gate

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 10

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

The average power dissipation of the CMOS logic gate, driven by a periodic input
voltage waveform with ideally zero rise- and fall-times, can be calculated from the
energy required to charge up the output node to VDD and charge down the total output
load capacitance to ground level.

Simplifying this integral gives the well-known expression for the average dynamic
(switching) power consumption in CMOS logic circuits.

• The average dynamic power dissipation is proportional to the square of the power
supply voltage; hence, any reduction of VDD will significantly reduce the power
consumption.
• Another way to limit the dynamic power dissipation of a CMOS logic gate is to
reduce the amount of switched capacitance at the output.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 11

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Effect of reducing the power supply voltage VDD on switching power dissipation

Assuming that the power supply voltage is being scaled down while all other variables
are kept constant, it can be seen that the propagation delay time will increase.
The dependence of circuit speed on the power supply voltage may also influence the
relationship between the dynamic power dissipation and the supply voltage.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 12

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Effect of reducing the power supply voltage VDD on switching power dissipation

To better represent this behavior, we will introduce T (node transition factor), which
is the effective number of power-consuming voltage transitions experienced per clock
cycle. Then, the average switching power dissipation becomes

There is a parasitic node capacitance associated with each internal node, these
internal transitions contribute to the overall power dissipation of the circuit. In fact,
an internal node may face several transitions while the output node voltage of the
circuit remains unchanged,

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 13

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Effect of reducing the power supply voltage VDD on switching power dissipation

the average switching power dissipation can be written as

Where Ci represents the parasitic capacitance associated with each node and αTi
represents the corresponding node transition factor associated with that node.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 14

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Short-Circuit Power Dissipation

• The switching power dissipation discussed above is purely due to the energy
required to charge up the parasitic capacitances in the circuit, and the
switching power is independent of the rise and fall times of the input signals.
• Now, if a CMOS inverter (or a logic gate) is driven with input voltage
waveforms with finite rise and fall times, both the nMOS and the pMOS
transistors in the circuit may conduct simultaneously for a short amount of
time during switching, forming a direct current path between the power
supply and the ground

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 15

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Short-Circuit Power Dissipation

Short-circuit current component is the current component which passes through

both the nMOS and the pMOS devices during switching. It does not contribute to the
charging of the capacitances in the circuit.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 16

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Short-Circuit Power Dissipation

• The nMOS transistor in the circuit starts conducting when the rising input voltage
exceeds the threshold voltage VT,n.
• The pMOS transistor remains on until the input reaches the voltage level (VDD -
|VT,p|). Thus, there is a time window during which both transistors are turned on. As the
output capacitance is discharged through the nMOS transistor, the output voltage starts
to fall.
• The drain-to-source voltage drop of the pMOS transistor becomes nonzero, which
allows the pMOS transistor to conduct as well. The short circuit current is terminated
when the input voltage transition is completed and the pMOS transistor is turned off.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 17

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Short-Circuit Power Dissipation

For a simple analysis consider a symmetric CMOS inverter with k = kn = kp and
VT = VT,n = |VT,p|, and with a very small capacitive load. If the inverter is driven with
an input voltage waveform with equal rise and fall times (t = trise = tfall), it can be
derived that the time- averaged short circuit current drawn from the power supply is

Hence, the short-circuit power dissipation becomes

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 18

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Short-Circuit Power Dissipation

Short-circuit power dissipation is linearly proportional to the input signal rise and
fall times, and also to the transconductance of the transistors. Hence, reducing the input
transition times will obviously decrease the short circuit current component.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 19

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Short-Circuit Power Dissipation

• Short-circuit power dissipation is linearly proportional to the input signal rise and
fall times, and also to the transconductance of the transistors. Hence, reducing the input
transition times will obviously decrease the short circuit current component.
• The short-circuit power dissipation can be reduced by making the output voltage
transition times larger and/or by making the input voltage transition times smaller.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 20

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Leakage Power Dissipation

The nMOS and pMOS transistors used in a CMOS logic gate generally have nonzero
reverse leakage and sub threshold currents. In a CMOS VLSI chip containing a very
large number of transistors, these currents can contribute to the overall power
dissipation even when the transistors are not undergoing any switching event. The
magnitude of the leakage currents is determined mainly by the processing parameters.

Two main leakage current components found in a MOSFET are

(1) Reverse diode leakage current
(2) Sub threshold leakage current

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 21

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Reverse diode leakage current:

•The reverse diode leakage occurs when the pn-junction between the drain and the bulk of
the transistor is reversely biased.
•The reverse-biased drain junction then conducts a reverse saturation current which is
eventually drawn from the power supply.
•Consider a CMOS inverter with a high input voltage, where the nMOS transistor is turned
on and the output node voltage is discharged to zero.
•Although the pMOS transistor is turned off, there will be a reverse potential difference of
VDD between its drain and the n-well, causing a diode leakage through the drain junction.
• The n-well region of the pMOS transistor is also reverse-biased with VDD, with respect
to the p-type substrate. Therefore, another significant leakage current component exists due
to the n-well junction

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 22

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Reverse diode leakage current:

when the input voltage is equal to zero, and the output voltage is charged up to VDD through
the pMOS transistor. Then, the reverse potential difference between the nMOS drain region
and the p-type substrate causes a reverse leakage current which is also drawn from the
power supply (through the pMOS transistor).
The magnitude of the reverse leakage current of a pn-junction is given by the following
expression

Vbias is the magnitude of the reverse bias voltage across the junction
JS is the reverse saturation current density and the A is the junction area.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 23

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Subthreshold leakage current:

Leakage currents which occur in CMOS circuits is the subthreshold current, which is
due to carrier diffusion between the source and the drain region of the transistor in weak
inversion.
An MOS transistor in the subthreshold operating region behaves similar to a bipolar
device and the subthreshold current exhibits an exponential dependence on the gate
voltage.
The amount of the subthreshold current may become significant when the gate- to
source voltage is smaller than, but very close to the threshold voltage of the device. In
this case, the power dissipation due to subthreshold leakage can become comparable in
magnitude to the switching power dissipation of the circuit.
UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 24
 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Subthreshold leakage current:

The sub threshold leakage current also occurs when there is no switching activity in
the circuit, and this component must be carefully considered for estimating the total
power dissipation in the stand-by operation mode. The sub threshold current
expression is

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 25

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

GLITCH POWER DISSIPATION:

• The glitching power dissipation occurs due to finite delay. This Power dissipated in
the intermediate transitions during the evaluation of the logic function of the circuit.
• In multi-level logic circuits, the finite propagation delay from one logic block to the
next can cause spurious signal transitions, or glitches as a result of critical races or
dynamic hazards.
• In general, if all input signals of a gate change simultaneously, no glitching occurs.
But a dynamic hazard or glitch can occur if input signals change at different times.
• Thus, a node can exhibit multiple transitions in a single clock cycle before settling
to the correct logic level.
• In some cases, the signal glitches are only partial, i.e., the node voltage does not
make a full transition between the ground and VDD levels, yet even partial glitches
can have a significant contribution to dynamic power dissipation.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 26

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

GLITCH POWER DISSIPATION:

• Glitches occur primarily due to a mismatch or imbalance in the path lengths

in the logic network. Such a mismatch in path length results in a mismatch of
signal timing with respect to the primary inputs.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 27

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

GLITCH POWER DISSIPATION:

Assuming that all XOR blocks have the same delay in Fig.(a) will suffer from
glitching due to the wide disparity between the arrival times of the input signals for the
gates.
In the network shown in Fig.(b), all arrival times are identical because the delay paths
are balanced. Such redesign can significantly reduce the glitching transitions, and
consequently, the dynamic power dissipation in complex multi-level networks. Results in
smaller overall propagation delay. Finally, it should be noted that glitching is not a
significant issue in multi-level dynamic CMOS logic circuits, since each node undergoes at
most one transition per clock cycle.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 28

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Short-Channel Effects:
Short-Channel Devices:
A MOSFET device is considered to be short when the channel length is the same order of
magnitude as the depletion-layer widths (xdD, xdS) of the source and drain junction. As
the channel length L is reduced to increase both the operation speed and the number of
components per chip, the so-called short-channel effects arise.
Short-Channel Effects
The short-channel effects are attributed to two physical phenomena:
1.The limitation imposed on electron drift characteristics in the channel,

2.The modification of the threshold voltage due to the shortening channel length.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 29

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Short-Channel Effects:

Five different short-channel effects can be distinguished:

1. Drain-induced barrier lowering and punch through
2. Surface scattering
3. Velocity saturation
4. Impact ionization
5. Hot electron effect

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 30

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Drain-induced barrier lowering:

The expressions for the drain and source junction widths are:

Where VSB and VDB are source-to-body and drain-to-body voltages

•There exists a potential barrier between source and drain which is to be lowered by
applying gate voltage.
•In short channel devices in addition to the gate voltage, drain voltage also has a
significant effect on reducing this barrier.
•As the source & drain get closer, they become electrostatically coupled, so that the
drain bias can affect the potential barrier to carrier flow at the source junction. As a
result, sub threshold current increases.
•As the drain depletion region continues to increase with the bias, it can actually
interact with the source to channel junction and hence lowers the potential barrier. This
problem is known as Drain Induced Barrier Lowering (DIBL).
UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 31
 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Drain-induced barrier lowering:

• When the source junction barrier is reduced, electrons are easily injected into the
channel and the gate voltage has no longer any control over the drain current.
• In long channel devices, the source and drain are separated far enough that their
depletion regions have no effect on the potential or field pattern in most part of the
device.
• Hence, for such devices, the threshold voltage is virtually independent of the
channel length and drain bias. DIBL is enhanced at high drain voltages and shorter
channel lengths.
UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 32
 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Punch through:
• When the drain is at high enough voltage with respect to the source, the depletion
region around the drain may extend to the source, causing current to flow irrespective
of gate voltage (i.e. even if gate voltage is zero). This is known as Subsurface
Punchthrough as it takes place away from the gate oxide and substrate interface.

• So when channel length L decreases (i.e. short channel length case), punch through
voltage rapidly decreases.

• In short-channel devices, due to the proximity of the drain and the source, the
depletion regions at the drain-substrate and source- substrate junctions extend into the
channel.

• As the channel length is reduced, if the doping is kept constant, the separation

between the depletion region boundaries decreases.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 33
 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Punch through:
• An increase in the reverse bias across the junctions also pushes the junctions nearer to
each other. When the combination of channel length and reverse bias leads to the
merging of the depletion regions, punchthrough is said to have occurred.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 34

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Surface scattering:
As the channel length becomes smaller due to the lateral extension of the depletion layer
into the channel region, the longitudinal electric field component εy increases, and the
surface mobility becomes field-dependent. Since the carrier transport in a MOSFET is
confined within the narrow inversion layer, and the surface scattering that is the
collisions suffered by the electrons that are accelerated toward the interface by εx) causes
reduction of the mobility, the electrons move with great difficulty parallel to the
interface, so that the average surface mobility, even for small values of εy, is about half
as much as that of the bulk mobility.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 35

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Velocity saturation:
•The performance short-channel devices are also affected by velocity saturation, which
reduces the transconductance in the saturation mode.
• At low εy, the electron drift velocity vde in the channel varies linearly with the electric
field intensity.
• However, as εy increases above 104 V/cm, the drift velocity tends to increase more
slowly, and approaches a saturation value of vde(sat)=107 cm/s around εy =105 V/cm at
300 K.
•Note that the drain current is limited by velocity saturation instead of pinchoff.
•This occurs in short channel devices when the dimensions are scaled without lowering
the bias voltages. Using vde(sat), the maximum gain possible for a MOSFET can be
defined as

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 36

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Impact ionization
•Another undesirable short-channel effect, especially in NMOS, occurs due to the high
velocity of electrons in presence of high longitudinal fields that can generate electron-
hole (e-h) pairs by impact ionization.
•It happens as follow: normally, most of the electrons are attracted by the drain, while the
holes enter the substrate to form part of the parasitic substrate current.
•If the aforementioned holes are collected by the source, and the corresponding hole
current creates a voltage drop in the substrate material of the order of 0.6V, the normally
reversed-biased substrate-source pn junction will conduct appreciably.
•Then electrons can be injected from the source to the substrate, similar to the injection
of electrons from the emitter to the base. They can gain enough energy as they travel
toward the drain to create new electron hole pairs.
•The situation can worsen if some electrons generated due to high fields escape the drain
field to travel into the substrate, thereby affecting other devices on a chip.
UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 37
 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Hot electron effect:

•Another problem, related to high electric fields, is caused by so-called hot electrons.
• These high energy electrons can enter the oxide, where they can be trapped, giving rise
to oxide charging that can accumulate with time and degrade the device performance by
increasing VT and affect adversely the gate’s control on the drain current.

UNIT 1:FUNDAMENTALS OF LOW POWER CIRCUITS Ms. G VIJAYAKUMARI, AP/ ECE 38