VLSI
VLSI
1. Write short notes on of the following (i) Dynamic CMOS logic families (ii) classify various fault models (iii)
low power CMOS VLSI designs Techniques 10
2. Define the terns Controllability and Observability 4
3. Discuss the operation of SRAM OR DRAM cell with suitable CMOS circuits 4
4. Design an adiabatic 2 input AND/NAND gate and explain it 4
5. What do you understand from BIST? Explain PRPG and ORA 4
6. Discuss the operation of single stage shift register circuits Design a SR flip-flop using CMOS circuits. 4
1. Write short notes on of the following (i) Dynamic CMOS logic families (ii) classify various fault models (iii)
low power CMOS VLSI designs Techniques 10
2. Define the terns Controllability and Observability 4
3. Discuss the operation of SRAM OR DRAM cell with suitable CMOS circuits 4
4. Design an adiabatic 2 input AND/NAND gate and explain it 4
5. What do you understand from BIST? Explain PRPG and ORA 4
6. Discuss the operation of single stage shift register circuits Design a SR flip-flop using CMOS circuits. 4
1. Write short notes on of the following (i) Dynamic CMOS logic families (ii) classify various fault models (iii)
low power CMOS VLSI designs Techniques 10
2. Define the terns Controllability and Observability 4
3. Discuss the operation of SRAM OR DRAM cell with suitable CMOS circuits 4
4. Design an adiabatic 2 input AND/NAND gate and explain it. 4
5. What do you understand from BIST? Explain PRPG and ORA 4
6. Discuss the operation of single stage shift register circuits Design a SR flip-flop using CMOS circuits. 4
Printed Pages: 0
B.Tech.
(SEM VII) ODD SEMESTER THEORY EXAMINATION 2018-19
VLSI DESIGN
Time: [3] Hour Maximum. Marks: [100]
Note- Attempt All Questions. All Questions carry equal marks:-
Q.1. Attempt all parts of the following:- (10*2=20)
a) Explain VLSI design methodology with Y chart and CAD Tools.
b) Draw a MOS circuit with all capacitance. Explain constant field scaling and constant voltage
scaling.
c) Discuss the layout design process of CMOS inverter. Draw a stick diagram of 2 input CMOS
NOR gate.
OR
Derive the expression of ratio between Zpu and Zpd when an inverter is to be driven by another
inverter.
d) In NMOS transistor operating at 300k, VG=4V, VDS=5V, VSB= 2.6V, ID= 148mA. the process
parameters are, W/L=1 , tox= 500A |2qf|=0.68v and Na = 1.2*10 16 /cm3. find the threshold
voltage,
OR
For an n channel MOS transistor with µn = 60cm2µA/V-s, Cox = 7.10-8 F/cm2, W = 20µm, L=2µm
and VT0 = 1.0V. Examine the relationship between the drain current and the terminal voltages
Q.2. Attempt all parts of the following:- (10*2=20)
a) Consider a CMOS inverter circuit with following parameters: VDD= 1.2V, VT0n=0.48V, VT0p= -
0.46V, kn=982uA/V2, kp=653 µA/V2. Calculate the noise margin of the circuit.
b) Design a CMOS buffer to drive a 20 pF capacitive load from the inverter with size of (9/3). The
tpHL + tpLH should be less than 11ns. Calculate the number of stages N, area factor A and total
delay for this buffer. Assuming C’ox = 800aF/µm2; channel length = 2µm; sheet resistance of
nMOS & p MOS i.e. R’n =12 kΩ/µm2 and R’p =36 kΩ/µm2.
OR
Design a five stage Ring oscillator from the inverter with size of Wn = Wp = 10μm. Assuming
C’ox = 800aF/μm2, channel length =2μm, sheet resistance of nMOS & pMOS i.e. R’n = 12kΩ/sq,
R’p = 36kΩ/sq and calculate the oscillation frequency and power delay product.
Q.3. Attempt all parts of the following:- (10x2=20)
W
a) Determine the rations of the nMOS and the pMOS transistors such that the switching
L
threshold is Vth = 1.5V for a CMOS inverter, with the following device parameters, VDD =3.3V,
VTon= 0.6V, VTop =-0.7V , µnCox =60µA/V2, µpCox= 20µA/V2, λ= 0.
b) Calculate the intrinsic propagation delays, tpHL + tpLH, of a three input NAND gate made using
minimum size transistors. Estimate the delay when the gate is driving load capacitance of 100fF.
Assume the inputs are tied together.
OR
(i) Draw a CMOS full adder using CMOS AOI logic.
(ii)Draw a 4X1 multiplexer/demultiplexer using pass transistor CMOS logic
.
(ii) Discuss the operation of DRAM cell with suitable CMOS circuits
OR
Write a short note on Ad Hoc Testable Design Techniques,
(d) Explain the concept of Adiabatic CMOS logic. Draw a 2 input NAND gate circuit using Adiabatic
CMOS Logic.
OR
Explain the concept of low power MTCMOS VLSI design techniques.
Page 1
ELECTRONICS AND COMMUNICATION ENGINEERING
SECOND MID SEMESTER EXAMINATION 2020-21
REC 702 VLSI DESIGN
TIME: 1 HOUR MAX MARKS:30
* Attempt Any 6 Questions
Odd Question for Odd Roll Number and Even Question for Even Roll Number
Q. Question Paper Based On Course Outcomes According To Bloom's Cognitive Level
1. Draw a CMOS inverter circuit and explain its transfer characteristics. If the change over
between logic levels in symmetrical, show that the width to length ratio of the p-device
is approximately three times of that of the n-device.
2. Define the terms Controllability and Observability.
3. Describe the working of DRAM with its circuit diagram.
4. Implement CMOS edge triggered Master slave D flip flop and explain its working with
input and output waveforms.
W
1.0V, µnCox = 20µA/V2, 10 .
L n
10. Design the circuit described by the Boolean function Y A.(B C)(D E ) using CMOS logic.
Calculate the equivalent CMOS inverter circuit for simultaneous switching of all inputs assuming
W W
that 10 for pMOS transistor and 5 for all nMOS transistor.
L L
11. Discuss the operation of single stage shift register circuits. Design a SR flip-flop using CMOS
circuits.
12. Explain the implementation of Built-In Self Test (BIST) design techniques for VLSI circuit
testing.
13. Enlist the Layout design process and design rules of CMOS circuit. Draw a stick diagram of
CMOS NOR gate.
14. Consider a CMOS inverter circuits with the following parameters VDD = 3.3V, VTon = 0.6V,
VTop= -0.7V, kn = 200µA/V2, kp= 80µA/V2, kR = 2.5 Calculate the noise margin of the circuits.
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW
Name of
VLSI DESIGN Semester 7
Subject
Name Of
Dr. SUBODH WAIRYA
Faculty
Subject Name of the Subject
L T P CT TA Total ESE Credit
Code Subject Total
REC 702 VLSI Design 3 0 0 20 10 30 70 100 3
1 REC702.1 Discover Different kinds of VLSI Design Methodologies, VLSI Design Flow,
Design Hierarchy, Concepts of Regularity, Modularity and Locality .MOSFET
Fabrication. Scaling and Small geometry effects and capacitances
2 REC702.2 Demonstration of MOS Inverters like Resistive Load and CMOS Inverter and its
switching Characteristics.
3 REC702.3 Analysis of Combinational MOS Logic Circuits with CMOS transmission gates
(pass gates) and Sequential MOS Logic Circuits and CMOS D latch and edge
triggered FF.
4 REC702.4 Illustration of basic principle of pass transistor Circuits and introduction of
Semiconductor memories like DRAM, SRAM, ROM, flash memory.
5 REC702.5 Discuss MOS concepts and also introduction of Low – Power CMOS Logic Circuits
and Design for Testability.
Course Outcomes:
REC702.1 (CO1) basic VLSI design technologies and Scaling
Describe and apply fundamentals
and small scale geometry effects.
REC702.2 (CO2) Demonstrate MOS Inverters like Resistive Load and CMOS Inverter and its
switching Characteristics.
REC702.3 (CO3) Solve Combinational and Sequential MOS Logics and SR latch circuits, clocked latch and
FF circuits, CMOS D latch and edge triggered FF.
REC702.4 (CO4) Classify and explain pass transistors and Semiconductor memories.
REC702.5 (CO5) Summarize MOS concepts and invent Low – Power CMOS Logic Circuits and assemble
the knowledge for testing of design.
1 REC 702 VLSI Design Establish the correlation between the courses and the Program Outcomes
(POs)& Program Specific Outcomes
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW
CO2 with PO3 The students can be able to design basic MOS inverters and its switching characteristics.
CO2 with PO4 The students can attempt to solve complex problems pertaining to MOS inverters and its
switching characteristics.
CO3 with PO1 The students will have a proper knowledge of Combinational MOS Logic Circuits and
Sequential MOS Logic Circuits.
CO3 with PO2 The students can analyse problems with respect to Combinational MOS Logic Circuits and
Sequential MOS Logic Circuits.
CO3 with PO3 The students can design efficient Combinational MOS Logic Circuits and Sequential MOS
Logic Circuits.
CO3 with PO4 The students can develop complex models and solve problems relating to Combinational
MOS Logic Circuits and Sequential MOS Logic Circuits.
CO4 with PO1 The students will learn basic principle of pass transistor Circuits and introduction of
Semiconductor memories like DRAM, SRAM, ROM, flash memory.
CO4 with PO2 Students can solve basic problems relating to pass transistors.
CO4 with PO3 The students can be able to design CMOS transmission gates (pass gates),SR latch circuits,
clocked latch and FF circuits, CMOS D latch and edge triggered FF.
CO4 with PO4 The students can calculate complex problem of Sequential MOS Logic Circuits like
Dynamic CMOS circuits.
CO5 with PO1 The students can be able to test different types of digital systems and Fault types and
models.
CO5 with PO2 The students can be able to design Low – Power CMOS Logic Circuits.
CO5with PO3 The students can be able to design the needful MOS circuits and their power consumption
techniques.
CO5with PO7 The students can design low power MOS circuits and better power consumption techniques
for sustainability of environment
CO5with PO12 Life long learning of VLSI design
2 REC 702 VLSI Design Establish the correlation between the courses and the Program Outcomes
(POs)& Program Specific Outcomes
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW
REC702.1 (CO1) 3 - 2
REC702.2 (CO2) 3 3 2
REC702.3 (CO3) - 3 -
REC702.4 (CO4) - - 2
REC702.5 (CO5) - - 3
Average 3 3 2.25
3 REC 702 VLSI Design Establish the correlation between the courses and the Program Outcomes
(POs)& Program Specific Outcomes
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW
4 REC 702 VLSI Design Establish the correlation between the courses and the Program Outcomes
(POs)& Program Specific Outcomes
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW
Reference Books:
1. D. A. Pucknell and K. Eshraghian,"Basic VLSI Design: Systems and circuits", PHI
2. W. Wolf, Modern VLSI Design: System on Chip, Pearson.
3.Rabaey,Pedram,“LowPowerDesignMethodologies”KluwerAcademic,1997
5 REC 702 VLSI Design Establish the correlation between the courses and the Program Outcomes
(POs)& Program Specific Outcomes
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW
6 REC 702 VLSI Design Establish the correlation between the courses and the Program Outcomes
(POs)& Program Specific Outcomes
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW
Establish the correlation between the courses and the Program Outcomes(POs)& Program Specific
Outcomes
(Program Outcomes as mentioned in Annexure I and Program Specific Outcomes as defined by the Program)
PO1 Engineering Knowledge: Apply knowledge of mathematics and science, with fundamentals
of Electronics and Communication Engineering to be able to solve complex engineering
problems related to ECE.
PO2 Problem Analysis: Identify, Formulate, review research literature and analyze complex
engineering problems related to ECE and reaching substantiated conclusions using first
principles of mathematics, natural sciences and engineering sciences.
PO3 Design/Development of solutions: Design solutions for complex engineering problems related to
ECE and design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety and the cultural societal and environmental
considerations.
PO4 Conduct Investigations of Complex problems: Use research–based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
PO5 Modern Tool Usage: Create, Select and apply appropriate techniques, resources and modern
engineering and IT tools including prediction and modeling to Electronics Engineering related
complex engineering activities with an understanding of the limitations.
PO6 The Engineer and Society: Apply Reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
ECE professional Engineering practice.
PO7 Environment and Sustainability: Understand the impact of the ECE professional
engineering solutions in societal and environmental contexts and demonstrate the knowledge
of, and need for sustainable development
PO8 Ethics: Apply Ethical Principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
PO9 Individual and Team Work: Function effectively as an individual and as a member or leader in
diverse teams and in multidisciplinary Settings
PO10 Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large such as able to comprehend and with write
effective reports and design documentation, make effective presentations and give and receive
PO11 Project Management and Finance: Demonstrate knowledge and understanding of the
engineering management principles and apply these to one’s own work, as a member and leader in
a team, to manage projects and in multi-disciplinary environments.
PO12 Life-Long Learning: Recognize the need for and have the preparation and ability to
engage in independent and life-long learning the broadest context of technological change.
• List of PSO’s
PSO1 An ability to understand the concepts of basic Electronics & Communication Engineering and to
apply them to various areas like Signal processing, VLSI, Embedded systems, Communication
Systems, Digital & Analog Devices, etc
PSO2 An ability to solve complex Electronics and Communication Engineering problems, using latest
hardware and software tools, along with analytical skills to arrive cost effective and appropriate
solutions.
PSO3 Wisdom of social and environmental awareness along with ethical responsibility to have a
successful career and to sustain passion and zeal for real-world applications using optimal
resources as an Entrepreneur
7 REC 702 VLSI Design Establish the correlation between the courses and the Program Outcomes
(POs)& Program Specific Outcomes
ELECTRONICS AND COMMUNICATION ENGINEERING
SECOND MID SEMESTER EXAMINATION 2022-23
KEC072 VLSI Design
TIME: 1 HOUR MAX MARKS:30
Note: Attempt Any 6 Questions. All questions carry equal marks.
1. Draw a CMOS inverter circuit and explain its transfer characteristics. If the
change over between logic levels in symmetrical, show that the width to length
ratio of the p-device is approximately three times of that of the n-device.
2. Implement CMOS edge triggered Master slave D flip flop and explain its
working with input and output waveforms.
B.Tech.
(SEM VII) ODD SEMESTER BACK PAPER EXAMINATION 2019-20
VLSI DESIGN
[TIME: 3 hrs.] [Max. Marks: 100]
Note:Attempt All Questions. All Question carry equal marks.
Q1. Answer ALL parts. Marks
(a) State the Moores Law and its limitation. Explain VLSI design methodology with Y chart 5
(b) Explain the concepts of regularity, modularity and locality. Write a short note on 5
CAD Tools for VLSI Design
(c) Draw a MOS circuit with all capacitance. Explain constant field scaling and constant 5
voltage scaling.
OR
Explain the CMOS Inverter Switching characteristics using digital model. Draw the
Sizing curve of the CMOS inverter
(d) Describe the term Design Rules. Discuss the layout design rules in VLSI 5
OR
Draw a stick diagram of NOR gate with color coding.
Q2. Answer ALL parts.
(a) Determine the W/L rations of the nMOS and the pMOS transistors such that the 10
switching threshold is Vth = 1.5V for a CMOS inverter, with the following device
parameters, VDD =3.3V, VTon= 0.6V, VTop =-0.7V , µnCox =60µA/V2, µpCox=
20µA/V2, λ= 0.
(b) Describe the working of ring oscillator. Estimate the oscillation frequency and power 10
delay product of a five stage ring oscillator from the inverter with size of Wn = Wp =
10 μm. Assuming C’ox = 800 aF/μm2, channel length = 2 μm, sheet resistance of
nMOS & pMOS i.e. R’n = 12 kΩ/sq, R’p = 36 kΩ/sq .
OR
Design a CMOS buffer to drive a 20 pF capacitive load from the inverter with size of
(9/3). The tpHL + tpLH should be less than 11ns. Calculate the number of stages N,
area factor A and total delay for this buffer. Assuming C’ox = 800 aF/µm2; channel
length = 2µm; sheet resistance of nMOS & pMOS i.e. R’n = 12 kΩ/µm2 and R’p =
36 kΩ/µm2.
Q3. Answer ALL parts.
(a) Draw the implementation of Edge triggered (Master Slave) D flip-flop using TG 10
logic gates.
(b) Elaborate how domino CMOS logic overcomes charge sharing problem. Draw a 10
Domino CMOS diagram circuit that implements the following equation Z=
(A+B+C+D)(E+F+G)(H+I) . Assume that only A,E,H inputs are high and other
inputs are low, then draw and equivalent circuit for this case by using (W/L)=20/2
for all transistors.
OR
Design circuit described by the boolean function Y=A.(B+C+D)(E+F) using CMOS
logic. Calculate equivalent CMOS inverter circuit for simultaneous switching of all
inputs assuming that (W/L)=20 for all pMOS transistor and (W/L)=10 for all nMOS
transistors.
Q4. Answer ALL parts.
(a) Calculate the intrinsic propagation delays, tpHL + tpLH, of a three input NAND gate 10
made using minimum size transistors. Estimate the delay when the gate is driving
load capacitance of 100fF. Assume the inputs are tied together.
(b) What are the advantages of NORA CMOS logic circuit? Explain NORA CMOS 10
logic circuit with suitable example.
OR
Distinguish between SRAM and DRAM. Discuss the operation of CMOS DRAM
with concept of leakage current and refresh option.
Q5. Answer ALL parts.
(a) Define the terms controllability and observability. 5
(b) Explain different Fault types and their models. 5
(c) Write a note on Ahoc testable design techniques. 5
OR
Explain the concept of low power MTCMOS VLSI design techniques
(d) Explain the implementation of Built in Self Test (BIST) design techniques for VLSI 5
Circuits.
OR
Write a note on adiabatic CMOS logic. Design an adiabatic 2 input NAND/AND
gate.
ELECTRONICS AND COMMUNICATION ENGINEERING
FIRST MID SEMESTER (CLASS TEST) EXAMINATION 2018-19
EC 703 VLSI DESIGN
TIME: 1 HOUR MAX MARKS: 20
Ques Question Paper Based On Course Outcomes According To Bloom's Marks CO BL
No. Cognitive Level
1 (a) Discuss VLSI design methodology (Y Chart) & MOS Scaling 2 CO1 L2
(b) Write short notes on CAD Tools for VLSI Design 2 L3
2 Calculate the noise margin of the circuits. Consider a CMOS inverter 2+2 CO2 L4
circuits with the following parameters VDD = 3.3V, VTon = 0.6V, VTop= -0.7V,
kn = 200µA/V2, kp=80µA/V2, kR = 2.5
3 W 4 CO2 L3
Determine the rations of the nMOS and the pMOS transistors such
L
that the switching threshold is Vth = 1.5V for a CMOS inverter, with the
following device parameters, VDD =3.V, VTon= 0.6V, VTop =-0.7V , µnCox
=60µA/V2, µpCox= 20µA/V2, λ= 0.
4 Discuss the operation of five stage Ring Oscillator circuits & determine the 1+3 CO2 L2
oscillation frequency with PDP (Rn=8kΩ, Rp=24kΩ, Coutn =4.8fF, VDD =5V). L3
Estimate the intrinsic propagation delay tPHL+tPLH of a three-input NOR gate 3+1 CO2 L5
5 using minimum size transistor (Rn=8kΩ, Rp=24kΩ and Coutn =4.8fF).
Calculate the circuit delay also when the gate is driving a load capacitance of
100fF.
EEC-703
Roll No.
B.Tech.
(SEM VII) ODD SEMESTER THEORY EXAMINATION, 2013-14
VLSI DESIGN
(a) Consider a CMOS inverter circuits with the following parameters VDD = 3.3V, VTon = 0.6V,
VTop= -0.7V, kn = 200µA/V2, kp= 80µA/V2, kR = 2.5 Calculate the noise margin of the circuits.
(b) Consider a CMOS inverter, with the following device parameters, VDD = 3.V, VTon = 0.6V, VTop
W
= -0.7V , µnCox = 60µA/V2, µpCox = 20µA/V2, λ= 0. Determine the rations of the nMOS
L
and the pMOS transistors such that the switching threshold is Vth = 1.5V.
(c) Design the circuit described by the Boolean function Y A.(B C)(D E ) using CMOS logic.
Calculate the equivalent CMOS inverter circuit for simultaneous switching of all inputs assuming
W W
that 5 for pMOS transistor and 2 for all nMOS transistor.
L L
(a) Discuss the classification of Dynamic CMOS logic families. Discuss the operation of pass transistor
in dynamic logic circuit..
(b) Explain the CMOS inverter switching characteristic using the digital model and explain the
definitions of delays and transition times.
(c) Estimate the intrinsic propagation delay tPHL+tPLH of a three-input NOR gate using minimum size
transistor (Rn=8kΩ, Rp=24kΩ and Coutn =4.8fF).Estimate the circuit delay also when the gate is
driving a load capacitance of 100fF.
Q.4. Attempt any two parts of the following 10X2
1314/R/BT/00 Page 1
(a) Discuss the Elmore Delay. In a CMOS inverter power supply VDD =5V, determine the fall time,
which is define as the time elapsed between the time point at which Vout=V90% = 4.5V and the time
point at which Vout=V10% =0.5. The output load capacitance is 1pF. The nMOS transistor parameters
W
are as follows: VTn = 1.0V, µnCox = 20µA/V2, 10 .
L n
(a) For an n channel MOS transistor with µn = 60cm2µA/V-s, Cox = 7.10-8 F/cm2, W = 20µm,
L=2µm and VT0 = 1.0V. Examine the relationship between the drain current and the terminal
voltages
(a) Define the terns Controllability and Observability. Explain the implementation of Built-In Self Test
(BIST) design techniques for VLSI circuit testing.
(b) Write short notes on Adiabatic CMOS logic. Discuss the low power MTCMOS VLSI designs
techniques.
(c) Discuss the operation of CMOS SRAM cell circuit.
1213/R/BT/135 Page 2
BTECH
W
d) Determine the rations of the nMOS and the pMOS transistors such that the switching
L
threshold is Vth = 1.5V for a CMOS inverter, with the following device parameters, VDD =3.3V,
VTon= 0.6V, VTop =-0.7V , µnCox =60µA/V2, µpCox= 20µA/V2, λ= 0.
a) Calculate the intrinsic propagation delays, tpHL + tpLH, of a three input NAND gate made using
minimum size transistors. Estimate the delay when the gate is driving load capacitance of
100fF. Assume the inputs are tied together.
b) Implement CMOS edge triggered Master slave D flip flop and explain its working with
input and output waveforms.
c) Design circuit described by the boolean function Y=A.(B+C+D)(E+F) using CMOS logic.
Calculate equivalent CMOS inverter circuit for simultaneous switching of all inputs assuming
that (W/L)=20 for all pMOS transistor and (W/L)=10 for all nMOS transistors.
3. Discuss the classification of Dynamic CMOS logic families. Discuss the operation of pass
transistor in dynamic logic circuit. Draw a Domino CMOS diagram circuit that implements the
following equation Z= (A+B+C+D)(E+F+G)(H+I) . Assume that only A,E,H inputs are high and
other inputs are low, then draw and equivalent.
4. Discuss the Elmore Delay. In a CMOS inverter power supply VDD =5V, determine the fall time,
which is define as the time elapsed between the time point at which Vout=V90% = 4.5V and the
time point at which Vout=V10% =0.5. The output load capacitance is 1pF. The nMOS transistor
W
parameters are as follows: VTn = 1.0V, µnCox = 20µA/V2, 10 .
L n
5. Discuss the operation of single stage shift register circuits. Design a D flip-flop using TG CMOS
logic circuits
6. Discuss the working in terms of CMOS implementation of DRAM & SRAM
EC-703
ASSIGNMENT-1
1. With the help of IC process flow diagram, describe briefly, the basic considerations for IC
processing for an n-channel, polysilicon MOS.
2. What are the processing steps in p-well process of CMOS fabrication? Summarise only.
3. Explain twin-tub process with suitable sketch.
4. Explain all the steps of nMOS fabrication.
5. Describe the operation of basic MOS inverter. Derive the expression for pull-up to pull-down
ratio for an NMOS inverter driven by another NMOS inverter.
6. Explain briefly the Design Considerations of CMOS circuits.
7. Draw the different type of MOS inverter circuits and their transfer characteristics compare
their relative advantages and disadvantages.
8. Draw a CMOS inverter circuit and explain its transfer characteristics. If the change over
between logic levels in symmetrical, show that the width to length ratio of the p-device is
approximately three times of that of the n-device.
INSTITUTE OF ENGINEERING AND TECHNOLOGY,
LUCKNOW
VLSI DESIGN Branch: EC
EC-703
ASSIGNMENT-2
1. Explain CMOS inverter VTC with a neat diagram. What are the criteria for voltage threshold
for high and low level in inverter characteristics?
2. Explain the characteristics of CMOS Inverter.
3. Describe the nMOS NAND gate ratio determination.
4. Write the advantages and disadvantages of nMOS depletion load inverter.
5. Describe the operation of basic MOS Inverter. Derive the expression for pull-up to pull-down
ratio for an NMOS inverter driven by another NMOS inverter.
6. Draw the different type of MOS inverter circuits and their transfer characteristics compare
their relative advantage and disadvantages.
7. Drive he expression for VIH, VIL, NML and NMH for CMOS inverter.
8. Draw and explain NMOS inverter with enhancement mode pull-up and its transfer
characteristics. Why depletion load is preferred compared to enhancement load.
9. Explain the CMOS static transfer characteristics.
INSTITUTE OF ENGINEERING AND TECHNOLOGY,
LUCKNOW
VLSI DESIGN Branch: EC
EC-703
ASSIGNMENT-3
5. Draw the timing diagram for 2nd, 3rd and 4th questions.
6. For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give
the output for a square pulse input going from 0 to VDD.
INSTITUTE OF ENGINEERING AND TECHNOLOGY,
LUCKNOW
VLSI DESIGN Branch: EC
EC-703
ASSIGNMENT-4
1. Name the different modes of operation of DRAM. Explain each mode with the help
of timing diagram.
2. Draw a 6-T SRAM Cell and explain the Read and Write operations
3. How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s
performance?
4. What’s the critical path in a SRAM?
5. Draw the timing diagram for a SRAM Read. What happens if we delay the enabling
of Clock signal?
6. Give a big picture of the entire SRAM Layout showing your placements of SRAM
Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
7. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit
Lines? Why?
8. How can you model a SRAM at RTL Level?
INSTITUTE OF ENGINEERING AND TECHNOLOGY,
LUCKNOW
VLSI DESIGN Branch: EC
EC-703
ASSIGNMENT-5
1. Summarized all type of faults that can cause the chip failure.
3. Draw a schematic which can show the physical defect in NOR2 fabrication as well as
4. For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and
Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant
logic).
5. Give a logic circuit example in which stuck-at-1 fault and stuck-at-0 fault are
indistinguishable.
6. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you
B.Tech
(SEM VII) EXAMINATION 2011
VLSI DESIGN
(b)Design the circuit described by the Boolean function Y A.( B C )( D E ) using CMOS logic.
Calculate the equivalent CMOS inverter circuit for simultaneous switching of all inputs assuming that
W W
5 for pMOS transistor and 2 for all nMOS transistor.
L L
(c) Define the terns Controllability and Observability.
4. Attempt any Two parts of the following
Write short notes on of the following
(i) Dynamic CMOS logic families
(ii)
(iii) Low power CMOS VLSI designs Techniques
5. (a)What do you understand from BIST? Explain PRPG and ORA.
(b)Discuss the operation of single stage shift register circuits Design a SR flip-flop using CMOS circuits.
(c) Classify various fault models
Printed Pages: 1
EEC-703
Roll No.
B.Tech.
(SEM VII) SEMESTER THEORY EXAMINATION, 2014-15
VLSI DESIGN
(a) Consider a CMOS inverter circuits with the following parameters VDD = 3.3V, VTon = 0.6V,
VTop= -0.7V, kn = 200µA/V2, kp= 80µA/V2, kR = 2.5 Calculate the noise margin of the circuits.
(b) Consider a CMOS inverter, with the following device parameters, VDD = 3.V, VTon = 0.6V, VTop
W
= -0.7V , µnCox = 60µA/V2, µpCox = 20µA/V2, λ= 0. Determine the rations of the nMOS
L
and the pMOS transistors such that the switching threshold is Vth = 1.5V.
(c) Design the circuit described by the Boolean function Y A.(B C)(D E ) using CMOS logic.
Calculate the equivalent CMOS inverter circuit for simultaneous switching of all inputs assuming
W W
that 5 for pMOS transistor and 2 for all nMOS transistor.
L L
(a) Discuss the classification of Dynamic CMOS logic families. Discuss the operation of pass transistor
in dynamic logic circuit..
(b) Explain the CMOS inverter switching characteristic using the digital model and explain the
definitions of delays and transition times.
(c) Estimate the intrinsic propagation delay tPHL+tPLH of a three-input NOR gate using minimum size
transistor (Rn=8kΩ, Rp=24kΩ and Coutn =4.8fF).Estimate the circuit delay also when the gate is
driving a load capacitance of 100fF.
1314/R/BT/00 Page 1
Q.4. Attempt any two parts of the following 10X2
(c) In a logic Design logic function is Z A.B.C A BC B implemented with
(i) CMOS circuit diagram
(ii) Domino CMOS circuits diagram
(a) Define the terns Controllability and Observability. Explain the implementation of Built-In Self Test
(BIST) design techniques for VLSI circuit testing.
(b) Write short notes on low power CMOS VLSI designs Techniques.
(c) Discuss the operation of CMOS SRAM cell circuit.
1213/R/BT/135 Page 2
PAPER ID EEC-703
EEC-703
Roll No.
B.Tech.
(SEM VII) SEMESTER THEORY EXAMINATION, 2014-15
VLSI DESIGN
(a) Enlist the Layout design process and design rules of CMOS circuit. Draw a stick diagram of CMOS
NOR gate.
(b) Consider a CMOS inverter circuits with the following parameters VDD = 3.3V, VTon = 0.6V,
VTop= -0.7V, kn = 200µA/V2, kp= 80µA/V2, kR = 2.5 Calculate the noise margin of the circuits.
(c) Consider a CMOS inverter, with the following device parameters, VDD = 5V, VTon = 0.6V, VTop =
W
-0.7V , µnCox = 60µA/V2, µpCox = 20µA/V2, λ= 0. Determine the rations of the nMOS and
L
the pMOS transistors such that the switching threshold is Vth = 2.5V.
Page 1
Q.3. Attempt any four parts of the following 5X4
(a) In a CMOS inverter power supply VDD =5V, determine the fall time, which is define as the time
elapsed between the time point at which Vout=V90% = 4.5V and the time point at which Vout=V10%
=0.5. The output load capacitance is 1pF. The nMOS transistor parameters are as follows: VTn =
W
1.0V, µnCox = 20µA/V2, 10 .
L n
(b) Design the circuit described by the Boolean function Y A.(B C)(D E ) using CMOS logic.
Calculate the equivalent CMOS inverter circuit for simultaneous switching of all inputs assuming
W W
that 10 for pMOS transistor and 5 for all nMOS transistor.
L L
(c) Discuss the operation of single stage shift register circuits. Design a SR flip-flop using CMOS
circuits.
Page 2
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW
Name of
VLSI DESIGN Semester 7
Subject
Name Of
Dr. SUBODH WAIRYA
Faculty
Subject Name of the Subject
L T P CT TA Total ESE Credit
Code Subject Total
REC 702 VLSI Design 3 0 0 20 10 30 70 100 3
1 REC702.1 Discover Different kinds of VLSI Design Methodologies, VLSI Design Flow,
Design Hierarchy, Concepts of Regularity, Modularity and Locality .MOSFET
Fabrication. Scaling and Small geometry effects and capacitances
2 REC702.2 Demonstration of MOS Inverters like Resistive Load and CMOS Inverter and its
switching Characteristics.
3 REC702.3 Analysis of Combinational MOS Logic Circuits with CMOS transmission gates
(pass gates) and Sequential MOS Logic Circuits and CMOS D latch and edge
triggered FF.
4 REC702.4 Illustration of basic principle of pass transistor Circuits and introduction of
Semiconductor memories like DRAM, SRAM, ROM, flash memory.
5 REC702.5 Discuss MOS concepts and also introduction of Low – Power CMOS Logic Circuits
and Design for Testability.
Course Outcomes:
REC702.1 (CO1) basic VLSI design technologies and Scaling
Describe and apply fundamentals
and small scale geometry effects.
REC702.2 (CO2) Demonstrate MOS Inverters like Resistive Load and CMOS Inverter and its
switching Characteristics.
REC702.3 (CO3) Solve Combinational and Sequential MOS Logics and SR latch circuits, clocked latch and
FF circuits, CMOS D latch and edge triggered FF.
REC702.4 (CO4) Classify and explain pass transistors and Semiconductor memories.
REC702.5 (CO5) Summarize MOS concepts and invent Low – Power CMOS Logic Circuits and assemble
the knowledge for testing of design.
1 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)& Program
Specific Outcomes
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW
Course PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
Outcomes
REC702.1 3 1 1 - - - - - - - - -
(CO1)
REC702.2 2 2 2 1 - - - - - - - -
(CO2)
REC702.3 2 3 1 2 2 - - - - - - -
(CO3)
REC702.4 2 2 3 3 - - - - - - - -
(CO4)
REC702.5 2 2 2 - - - 2 - - - - 2
(CO5)
Average 2 2 2 2.5 2 - 2 - - - - 2
Course PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
Outcomes
REC702.1 H L L - - - - - - - - -
(CO1)
REC702.2 M M M L - - - - - - - -
(CO2)
REC702.3 M H L M M - - - - - - -
(CO3)
REC702.4 M M H H - - - - - - - -
(CO4)
REC702.5 M M M - - - M - - - - M
(CO5)
Average M M M M M - M - - - - M
CO1 with PO2 The students can solve basic problems pertaining to MOS
CO1 with PO3 The students can be able to design proper design flow of circuits.
CO2 with PO1 The students will gain knowledge of basic MOS inverters and its switching
characteristics.
CO2 with PO2 The students can solve problems basic MOS inverters and its switching
characteristics.
CO2 with PO3 The students can be able to design basic MOS inverters and its switching
characteristics.
CO2 with PO4 The students can attempt to solve complex problems pertaining to MOS
inverters and its switching characteristics.
CO3 with PO1 The students will have a proper knowledge of Combinational MOS Logic
Circuits and Sequential MOS Logic Circuits.
2 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)& Program
Specific Outcomes
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW
CO3 with PO2 The students can analyse problems with respect to Combinational MOS
Logic Circuits and Sequential MOS Logic Circuits.
CO3 with PO3 The students can design efficient Combinational MOS Logic Circuits and
Sequential MOS Logic Circuits.
CO3 with PO4 The students can develop complex models and solve problems relating to
Combinational MOS Logic Circuits and Sequential MOS Logic Circuits.
CO4 with PO1 The students will learn basic principle of pass transistor Circuits and
introduction of Semiconductor memories like DRAM, SRAM, ROM, flash
memory.
CO4 with PO2 Students can solve basic problems relating to pass transistors.
CO4 with PO3 The students can be able to design CMOS transmission gates (pass gates),SR
latch circuits, clocked latch and FF circuits, CMOS D latch and edge
triggered FF.
CO4 with PO4 The students can calculate complex problem of Sequential MOS Logic
Circuits like Dynamic CMOS circuits.
CO5 with PO1 The students can be able to test different types of digital systems and Fault
types and models.
CO5 with PO2 The students can be able to design Low – Power CMOS Logic Circuits.
CO5with PO3 The students can be able to design the needful MOS circuits and their power
consumption techniques.
CO5with PO7 The students can design low power MOS circuits and better power
consumption techniques for sustainability of environment
CO5with PO12 Life long learning of VLSI design
REC702.1 (CO1) 3 - 2
REC702.2 (CO2) 3 3 2
REC702.3 (CO3) - 3 -
REC702.4 (CO4) - - 2
REC702.5 (CO5) - - 3
Average 3 3 2.25
3 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)& Program
Specific Outcomes
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW
PSO3 Wisdom of social and environmental awareness along with ethical responsibility
to have a successful career and to sustain passion and zeal for real-world
applications using optimal resources as an Entrepreneur
4 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)& Program
Specific Outcomes
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW
5 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)& Program
Specific Outcomes
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW
6 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)& Program
Specific Outcomes
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW
Establish the correlation between the courses and the Program Outcomes(POs)& Program Specific
Outcomes
7 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)& Program
Specific Outcomes
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW
(Program Outcomes as mentioned in Annexure I and Program Specific Outcomes as defined by the Program)
PO1 Engineering Knowledge: Apply knowledge of mathematics and science, with fundamentals
of Electronics and Communication Engineering to be able to solve complex engineering
problems related to ECE.
PO2 Problem Analysis: Identify, Formulate, review research literature and analyze complex
engineering problems related to ECE and reaching substantiated conclusions using first
principles of mathematics, natural sciences and engineering sciences.
PO3 Design/Development of solutions: Design solutions for complex engineering problems related to
ECE and design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety and the cultural societal and environmental
considerations.
PO4 Conduct Investigations of Complex problems: Use research–based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
PO5 Modern Tool Usage: Create, Select and apply appropriate techniques, resources and modern
engineering and IT tools including prediction and modeling to Electronics Engineering related
complex engineering activities with an understanding of the limitations.
PO6 The Engineer and Society: Apply Reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
ECE professional Engineering practice.
PO7 Environment and Sustainability: Understand the impact of the ECE professional
engineering solutions in societal and environmental contexts and demonstrate the knowledge
of, and need for sustainable development
PO8 Ethics: Apply Ethical Principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
PO9 Individual and Team Work: Function effectively as an individual and as a member or leader in
diverse teams and in multidisciplinary Settings
PO10 Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large such as able to comprehend and with write
effective reports and design documentation, make effective presentations and give and receive
PO11 Project Management and Finance: Demonstrate knowledge and understanding of the
engineering management principles and apply these to one’s own work, as a member and leader in
a team, to manage projects and in multi-disciplinary environments.
PO12 Life-Long Learning: Recognize the need for and have the preparation and ability to
engage in independent and life-long learning the broadest context of technological change.
• List of PSO’s
PSO1 An ability to understand the concepts of basic Electronics & Communication Engineering and to
apply them to various areas like Signal processing, VLSI, Embedded systems, Communication
Systems, Digital & Analog Devices, etc
PSO2 An ability to solve complex Electronics and Communication Engineering problems, using latest
hardware and software tools, along with analytical skills to arrive cost effective and appropriate
solutions.
PSO3 Wisdom of social and environmental awareness along with ethical responsibility to have a
successful career and to sustain passion and zeal for real-world applications using optimal
resources as an Entrepreneur
8 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)& Program
Specific Outcomes
Printed Pages: 1
EEC-703
Roll No.
B.Tech.
(SEM VII) SEMESTER THEORY EXAMINATION, 2014-15
VLSI DESIGN
(a) VLSI design methodology (Y Chart) & MOS Scaling and CAD Tools for VLSI Design
(b) Layout design process of CMOS inverter. Draw a stick diagram of CMOS NOR gate.
(c) For an n channel MOS transistor with µn = 60cm2µA/V-s, Cox = 7.10-8 F/cm2, W = 20µm,
L=2µm and VT0 = 1.0V. Examine the relationship between the drain current and the terminal
voltages
(a) Consider a CMOS inverter circuits with the following parameters VDD = 3.3V, VTon = 0.6V,
VTop= -0.7V, kn = 200µA/V2, kp= 80µA/V2, kR = 2.5 Calculate the noise margin of the circuits.
(b) Consider a CMOS inverter, with the following device parameters, VDD = 3.V, VTon = 0.6V, VTop
W
= -0.7V , µnCox = 60µA/V2, µpCox = 20µA/V2, λ= 0. Determine the rations of the nMOS
L
and the pMOS transistors such that the switching threshold is Vth = 1.5V.
(c) Design the circuit described by the Boolean function Y (A C)(B C)(D E ) using CMOS
logic. Calculate the equivalent CMOS inverter circuit for simultaneous switching of all inputs
W W
assuming that 10 for pMOS transistor and 5 for all nMOS transistor.
L L
(a) Discuss the classification of Dynamic CMOS logic families. Discuss the operation of pass transistor
in dynamic logic circuit..
(b) Explain the CMOS inverter switching characteristic using the digital model and explain the
definitions of delays and transition times.
1314/R/BT/00 Page 1
(c) Estimate the intrinsic propagation delay tPHL+tPLH of a three-input NOR gate using minimum size
transistor (Rn=8kΩ, Rp=24kΩ and Coutn =4.8fF).Estimate the circuit delay also when the gate is
driving a load capacitance of 100fF.
(a) Discuss the Elmore Delay. In a CMOS inverter power supply VDD =5V, determine the
fall time, which is define as the time elapsed between the time point at which Vout=V90%
= 4.5V and the time point at which Vout=V10% =0.5. The output load capacitance is 1pF.
The nMOS transistor parameters are as follows: VTn = 1.0V, µnCox = 20µA/V2,
W
10 .
L n
(b) Discuss the operation of single stage shift register circuits Design a D flip-flop using
CMOS circuits.
(c) In a logic Design logic function is Z A B C D E F G H I implemented
with inputs (A,E,H) are high and other inputs are low
(i) Draw a full CMOS circuit diagram
(ii) Draw a domino CMOS circuits diagram with implements Z.
1213/R/BT/135 Page 2
Printed Pages: 1
EC-703
Roll No.
B.Tech.
(SEM VII) SEMESTER THEORY EXAMINATION, 2017-18
VLSI DESIGN
(a) Discuss the classification of CMOS logic families. Discuss the operation of pass transistor in
dynamic logic circuit.
(b) Draw Y Chart (VLSI design methodology) and explain MOS Scaling. CAD Tools for VLSI Design
in brief
(c) For an n channel MOS transistor with µn = 60cm2µA/V-s, Cox = 7.10-8 F/cm2, W = 20µm,
L=2µm and VT0 = 1.0V. Examine the relationship between the drain current and the terminal
voltages.
(d) Draw a 4X1 Multiplexer using Transmission Gate (TG).
(e) Discuss the operation of CMOS 6T SRAM cell circuit.
(a) Consider a CMOS inverter circuits with the following parameters VDD = 3.3V, VTon = 0.6V,
VTop= -0.7V, kn = 200µA/V2, kp= 80µA/V2, kR = 2.5 Calculate the noise margin of the circuits.
(b) Consider a CMOS inverter, with the following device parameters, VDD = 3.V, VTon = 0.6V, VTop
W
= -0.7V , µnCox = 60µA/V2, µpCox = 20µA/V2, λ= 0. Determine the rations of the nMOS
L
and the pMOS transistors such that the switching threshold is Vth = 1.5V.
(c) Design the circuit described by the Boolean function Y (A C)(B C)(D E ) using CMOS
logic. Calculate the equivalent CMOS inverter circuit for simultaneous switching of all inputs
W W
assuming that 10 for pMOS transistor and 5 for all nMOS transistor.
L L
Page 1
Q.3. Attempt any two parts of the following 10X2
(a) Explain the CMOS inverter switching characteristic using the digital model. Estimate the
propagation delay of a minimum size inverter driving a 100fF capacitor Wp=Wn= 3µm Lp=Ln=
2µm. Cox=800aF/µm2 Rn=12kΩ and Rp=36kΩ
(b) Estimate the intrinsic propagation delay tPHL+tPLH of a three-input NAND gate using minimum size
transistor (Rn=8kΩ, Rp=24kΩ and Coutn =4.8fF).Estimate the circuit delay also when the gate is
driving a load capacitance of 100fF.
(c) Design a five stage ring oscillator with Wn =Wp=10µm. determine the oscillation frequency
(a) Discuss the operation of single stage shift register circuits Design a D flip-flop using CMOS
circuits.
(b) Discuss the Elmore Delay. In a CMOS inverter power supply VDD =5V, determine the fall
time, which is define as the time elapsed between the time point at which Vout=V90% = 4.5V
and the time point at which Vout=V10% =0.5. The output load capacitance is 1pF. The nMOS
W
transistor parameters are as follows: VTn = 1.0V, µnCox = 20µA/V2, 10 .
L n
(c) In a domino CMOS circuits logic function Z is implemented with inputs (A,E,H) are high and
(a) Classify various fault models. Define the terns Controllability and Observability.
(b) Discuss the operation of DRAM cell with suitable CMOS circuits
(c) What do you understand from BIST? Explain PRPG and ORA
(d) Write short notes on Adiabatic CMOS logic. Design an adiabatic 2 input AND/NAND gate
(e) Discuss the low power MTCMOS VLSI designs techniques.
(f) Draw a stick diagram of CMOS NAND logic gate.
1213/R/BT/135 Page 2
ELECTRONICS AND COMMUNICATION ENGINEERING
SECOND MID SEMESTER EXAMINATION 2018-19
EC 703 VLSI DESIGN
TIME: 1 HOUR MAX MARKS:30
* Attempt Any 6 Questions
Q. Question Paper Based On Course Outcomes According To Bloom's Cognitive Level Marks CO BL
1 Elaborate how domino CMOS logic overcomes charge sharing problem with a suitable 5 CO4 L4
example.
2 Discuss transmission gates.Implement a 4*1 multiplexer using transmission gate. 5 CO3 L4
3 Design circuit described by the boolean function Y=A.(B+C)(D+E) using CMOS 5 CO3 L4
logic.Calculate equivalent CMOS inverter circuit for simultaneous switching of all inputs
assuming that (W/L)=10 for all pMOS transistor and (W/L)= 5 for all nMOS transistor.
4 Draw a Domino CMOS diagram circuit that implements the following equation Z= 5 CO3 L4
(A+B+C+D)(E+F+G)(H+I) . Assume that only A,E,H inputs are high and other inputs are
low, then draw and equivalent circuit for this case by using (W/L)=30/2 for all transistors.
5 Discuss the operation of CMOS SRAM with its circuit diagram 5 CO4 L2
6 Consider CMOS inverter circuit with lumped output capacitance having VDD = 3.3 V. The I-V 5 CO2 L4
characteristics of the nMOS transistor are specified as follows: when VGS = 3.3 V, the drain
current reaches its saturation level Isat = 2 mA for VDS ≥2.5 V. The input signal applied is a
step pulse that switches instantaneously from 0 V to 3.3 V. Calculate the delay time necessary
for the output to fall from its initial value of 3.3 V to 1.65 V, assuming an output load
capacitance of 300 fF.
7 Draw the digital model of CMOS inverter and derive the expression for delay times. 5 CO2 L3
8 Define the terms Controllability and Observability. Write a short note on built in self 5 CO5 L1
test(BIST) technique
EEC-703
Roll No.
B.Tech.
(SEM VII) SEMESTER THEORY EXAMINATION, 2014-15
VLSI DESIGN
(a) Define VLSI design methodology (Y Chart) & MOS Scaling and CAD Tools for VLSI Design
(b) Discuss the classification of CMOS digital logic families. Draw a 4X1 Multiplexer using
Transmission Gate (TG).
(c) Explain the CMOS inverter switching characteristic and explain the definitions of delays and
transition times.
(a) Enlist the Layout design process and design rules of CMOS circuit. Draw a stick diagram of CMOS
NOR gate.
(b) Consider a CMOS inverter circuits with the following parameters VDD = 3.3V, VTon = 0.6V,
VTop= -0.7V, kn = 200µA/V2, kp= 80µA/V2, kR = 2.5 Calculate the noise margin of the circuits.
(c) Consider a CMOS inverter, with the following device parameters, VDD = 5V, VTon = 0.6V, VTop =
W
-0.7V , µnCox = 60µA/V2, µpCox = 20µA/V2, λ= 0. Determine the rations of the nMOS and
L
the pMOS transistors such that the switching threshold is Vth = 2.5V.
Q.3. Attempt any two parts of the following 10X2
(a) Discuss the classification of Dynamic CMOS logic families. Discuss the operation of pass
transistor in dynamic logic circuit.
(b) In a logic Design logic function is Z A B C D E F G H I implemented
with domino CMOS circuits diagram with implements Z.
(c) Estimate the intrinsic propagation delay tPHL+tPLH of a three-input NOR gate using minimum
size transistor (Rn=8kΩ, Rp=24kΩ and Coutn =4.8fF).Estimate the circuit delay also when
the gate is driving a load capacitance of 100fF.
Page 1
Q.4. Attempt any two parts of the following 10X2
(a) In a CMOS inverter power supply VDD =5V, determine the fall time, which is define as the time
elapsed between the time point at which Vout=V90% = 4.5V and the time point at which Vout=V10%
=0.5. The output load capacitance is 1pF. The nMOS transistor parameters are as follows: VTn =
W
1.0V, µnCox = 20µA/V2, 10 .
L n
(b) Design the circuit described by the Boolean function Y A.(B C)(D E ) using CMOS logic.
Calculate the equivalent CMOS inverter circuit for simultaneous switching of all inputs assuming
W W
that 10 for pMOS transistor and 5 for all nMOS transistor.
L L
(c) Discuss the operation of single stage shift register circuits. Design a SR flip-flop using CMOS
circuits.
Page 2
Electronics Engineering Department
B.Tech VII (EC) Second Mid Semester Examination
VLSI Design (EEC-703)
Time: 1.30 Hours Max Marks 30
1. Write short notes on of the following (i) Dynamic CMOS logic families (ii) classify various fault models (iii)
low power CMOS VLSI designs Techniques 10
2. Define the terns Controllability and Observability 4
3. Discuss the operation of SRAM OR DRAM cell with suitable CMOS circuits 4
4. Design an adiabatic 2 input AND/NAND gate and explain it 4
5. What do you understand from BIST? Explain PRPG and ORA 4
6. Discuss the operation of single stage shift register circuits Design a SR flip-flop using CMOS circuits. 4
1. Write short notes on of the following (i) Dynamic CMOS logic families (ii) classify various fault models (iii)
low power CMOS VLSI designs Techniques 10
2. Define the terns Controllability and Observability 4
3. Discuss the operation of SRAM OR DRAM cell with suitable CMOS circuits 4
4. Design an adiabatic 2 input AND/NAND gate and explain it 4
5. What do you understand from BIST? Explain PRPG and ORA 4
6. Discuss the operation of single stage shift register circuits Design a SR flip-flop using CMOS circuits. 4
1. Write short notes on of the following (i) Dynamic CMOS logic families (ii) classify various fault models (iii)
low power CMOS VLSI designs Techniques 10
2. Define the terns Controllability and Observability 4
3. Discuss the operation of SRAM OR DRAM cell with suitable CMOS circuits 4
4. Design an adiabatic 2 input AND/NAND gate and explain it. 4
5. What do you understand from BIST? Explain PRPG and ORA 4
6. Discuss the operation of single stage shift register circuits Design a SR flip-flop using CMOS circuits. 4
Syllabus for First Mid Semester
Subject: VLSI Design Subject Code: KEC 072
B.Tech.
(SEM VII) ODD SEMESTER THEORY EXAMINATION 2018-19
VLSI DESIGN
Time: [3] Hour Maximum. Marks: [100]
Note- Attempt All Questions. All Questions carry equal marks:-
Q.1. Attempt all parts of the following:- (10*2=20)
a) Explain VLSI design methodology with Y chart and CAD Tools.
b) Draw a MOS circuit with all capacitance. Explain constant field scaling and constant voltage
scaling.
c) Discuss the layout design process of CMOS inverter. Draw a stick diagram of 2 input CMOS
NOR gate.
OR
Derive the expression of ratio between Zpu and Zpd when an inverter is to be driven by another
inverter.
d) In NMOS transistor operating at 300k, VG=4V, VDS=5V, VSB= 2.6V, ID= 148mA. the process
parameters are, W/L=1 , tox= 500A |2qf|=0.68v and Na = 1.2*10 16 /cm3. find the threshold
voltage,
OR
For an n channel MOS transistor with µn = 60cm2µA/V-s, Cox = 7.10-8 F/cm2, W = 20µm, L=2µm
and VT0 = 1.0V. Examine the relationship between the drain current and the terminal voltages
Q.2. Attempt all parts of the following:- (10*2=20)
a) Consider a CMOS inverter circuit with following parameters: VDD= 1.2V, VT0n=0.48V, VT0p= -
0.46V, kn=982uA/V2, kp=653 µA/V2. Calculate the noise margin of the circuit.
b) Design a CMOS buffer to drive a 20 pF capacitive load from the inverter with size of (9/3). The
tpHL + tpLH should be less than 11ns. Calculate the number of stages N, area factor A and total
delay for this buffer. Assuming C’ox = 800aF/µm2; channel length = 2µm; sheet resistance of
nMOS & p MOS i.e. R’n =12 kΩ/µm2 and R’p =36 kΩ/µm2.
OR
Design a five stage Ring oscillator from the inverter with size of Wn = Wp = 10μm. Assuming
C’ox = 800aF/μm2, channel length =2μm, sheet resistance of nMOS & pMOS i.e. R’n = 12kΩ/sq,
R’p = 36kΩ/sq and calculate the oscillation frequency and power delay product.
Q.3. Attempt all parts of the following:- (10x2=20)
W
a) Determine the rations of the nMOS and the pMOS transistors such that the switching
L
threshold is Vth = 1.5V for a CMOS inverter, with the following device parameters, VDD =3.3V,
VTon= 0.6V, VTop =-0.7V , µnCox =60µA/V2, µpCox= 20µA/V2, λ= 0.
b) Calculate the intrinsic propagation delays, tpHL + tpLH, of a three input NAND gate made using
minimum size transistors. Estimate the delay when the gate is driving load capacitance of 100fF.
Assume the inputs are tied together.
OR
(i) Draw a CMOS full adder using CMOS AOI logic.
(ii)Draw a 4X1 multiplexer/demultiplexer using pass transistor CMOS logic
.
(ii) Discuss the operation of DRAM cell with suitable CMOS circuits
OR
Write a short note on Ad Hoc Testable Design Techniques,
(d) Explain the concept of Adiabatic CMOS logic. Draw a 2 input NAND gate circuit using Adiabatic
CMOS Logic.
OR
Explain the concept of low power MTCMOS VLSI design techniques.
Page 1
Assignment- -4
KEC 072
Q. Question Paper Based On Course Outcomes According To Bloom's Cognitive
Level
1. Describe the working of ring oscillator. Estimate the oscillation frequency and
power delay product of a five stage ring oscillator from the inverter with size of
Wn = Wp = 10 μm. Assuming C’ox = 800 aF/μm2, channel length = 2 μm, sheet
resistance of nMOS & pMOS i.e. R’n = 12 kΩ/sq, R’p = 36 kΩ/sq .
2. Design a CMOS buffer to drive a 20 pF capacitive load from the inverter with size
of (9/3). The tpHL + tpLH should be less than 11ns. Calculate the number of
stages N, area factor A and total delay for this buffer. Assuming C’ox = 800
aF/µm2; channel length = 2µm; sheet resistance of nMOS & pMOS i.e. R’n = 12
kΩ/µm2 and R’p = 36 kΩ/µm2.
3. Calculate the intrinsic propagation delays, tpHL + tpLH, of a three input NAND gate
made using minimum size transistors. Estimate the delay when the gate is driving
load capacitance of 100fF. Assume the inputs are tied together.
4. Consider CMOS inverter circuit with lumped output capacitance having VDD =
3.3 V. The I-V characteristics of the nMOS transistor are specified as follows:
when VGS = 3.3 V, the drain current reaches its saturation level Isat = 2 mA for
VDS ≥2.5 V. The input signal applied is a step pulse that switches instantaneously
from 0 V to 3.3 V. Calculate the delay time necessary for the output to fall from
its initial value of 3.3 V to 1.65 V, assuming an output load capacitance of 300 fF.
5. Distinguish between SRAM and DRAM. Discuss the operation of CMOS DRAM
with concept of leakage current and refresh option.
6. Discuss the operation of CMOS SRAM with its circuit diagram. Discuss the
operation of CMOS 6T SRAM cell circuit.
7. Discuss the various sources of power dissipation in CMOS logic circuits?
8. Explain the concept of low power MTCMOS VLSI design techniques
9. Write a note on adiabatic CMOS logic. Design an adiabatic 2 input NAND/AND
gate.
10. Using AOI logic Implement the logic function Z A BC CD
Assignment- 3
KEC 072
Q. Question Paper Based On Course Outcomes According To Bloom's Cognitive
Level
1. Discuss transmission gates. Implement a 4*1 multiplexer using transmission gate.
2. Draw a CMOS inverter circuit and explain its transfer characteristics. If the
change over between logic levels in symmetrical, show that the width to length
ratio of the p-device is approximately three times of that of the n-device.
3. Implement CMOS edge triggered Master slave D flip flop and explain its working
with input and output waveforms.
4. Discuss the operation of single stage shift register circuits. Design a SR flip-flop
using CMOS circuits.
5. Elaborate how domino CMOS logic overcomes charge sharing problem with a
suitable example.
6. Elaborate the working of NORA CMOS logic with example.
7. Design circuit described by the boolean function Y’=A.(B+C+D)(E+F) using
CMOS logic. Calculate equivalent CMOS inverter circuit for simultaneous
switching of all inputs assuming that (W/L)=20 for all pMOS transistor and
(W/L)=10 for all nMOS transistors.
8. Discuss Elmore delay. In CMOS inverter power supply VDD=5V, determine the
fall time when Vout=V90%=4.5V AND VOUT=V10%=0.5V, the output load
capacitance is 1pF. The MOS transistor parameters are VTn=1V, unCox=20uA/V2,
(W/L)n=10
9. In a CMOS inverter power supply VDD =5V, determine the fall time, which is
define as the time elapsed between the time point at which Vout=V90% = 4.5V and
the time point at which Vout=V10% =0.5. The output load capacitance is 1pF. The
nMOS transistor parameters are as follows: VTn = 1.0V, µnCox = 20µA/V2,
W
10 .
L n
10. Design the circuit described by the Boolean function Y A.(B C)(D E) using
CMOS logic. Calculate the equivalent CMOS inverter circuit for simultaneous