Assignment 1

1. Explain VLSI design methodology

2. Define Y chart
3. Explain CAD Tools.
4. Draw a MOS circuit capacitance.
5. Explain constant field scaling and constant voltage scaling.
6. In NMOS transistor operating at 300k , vg=4v, vds=5v, vsb= 2.6v, id= 148mA. the
process parameters are, w/l=1 , tox= 500A |2qf|=0.68v and Na = 1.2*10 16 /cm3. find
the threshold voltage,
7. For an n channel MOS transistor with µn = 60cm2µA/V-s, Cox = 7.10-8 F/cm2, W =
20µm, L=2µm and VT0 = 1.0V. Examine the relationship between the drain current
and the terminal voltages
8. Discuss the layout design process of CMOS inverter.
9. Draw a stick diagram of CMOS NOR gate.
10. Derive the expression of ratio between Zpu and Zpd when an inverter is to be driven
by another inverter.
11. Draw the digital model of CMOS inverter and derive the expression for delay times.
12. Consider a CMOS inverter circuit with following parameters: V DD= 1.2V,
VT0n=0.48V, VT0p= -0.46V,kn=982uA/V2, kp=653 uA/V2. Calculate the noise margin
of the circuit.
13. Design a CMOS buffer to drive a 20 pF capacitive load from the inverter with size of
(9/3). The tpHL + tpLH should be less than 11ns. Calculate the number of stages N, area
factor A and total delay for this buffer. Assuming C’ ox = 800 aF/µm2; channel length =
2 µm; sheet resistance of n & p MOS i.e. R’n = 12 kΩ/µm2 and R’p = 36 kΩ/µm2.
14. Estimate the oscillation frequency and power delay product of a five stage ring
oscillator from the inverter with size of Wn = Wp = 10 μm. Assuming C’ ox = 800
aF/μm2, channel length = 2 μm, sheet resistance of n & pMOS i.e. R’n = 12 kΩ/sq,
R’p = 36 kΩ/sq .

15. Determine the

( WL ) rations of the nMOS and the pMOS transistors such that the
switching threshold is Vth = 1.5V for a CMOS inverter, with the following device
parameters, VDD =3.3V, VTon= 0.6V, VTop =-0.7V , µnCox =60µA/V2, µpCox= 20µA/V2,
λ= 0.
16. Calculate the intrinsic propagation delays, t pHL + tpLH, of a three input NAND gate
made using minimum size transistors. Estimate the delay when the gate is driving load
capacitance of 100fF. Assume the inputs are tied together.
 EEC 703

B.Tech
(SEM VII) EXAMINATION 2011
VLSI DESIGN

Time : 2 Hours Total Marks : 50

Note: (1) Attempt all questions

(2) All questions carry equal marks:

1. Attempt any Two parts of the following: 5X2

Write short notes on of the following
(i) VLSI design methodology (Y Chart)
(ii) MOS Scaling
(iii) CAD Tools for VLSI Design
Enlist the classification of CMOS digital logic families
2. (a) Explain the layout design process of CMOS inverter. Draw a stick diagram of CMOS NAND gate.
(b) Consider a CMOS inverter circuits with the following parameters VDD = 3.3V, VTon = 0.6V, VTop = -
0.7V, kn = 200µA/V2, kp= 80µA/V2, kR = 2.5 Calculate the noise margin of the circuits.
(c) Consider a CMOS inverter, with the following device parameters, VDD = 3.V, VTon = 0.6V,
VTop = -0.7V , µnCox = 60µA/V2, µpCox = 20µA/V2, λ= 0. Determine the (W/L) rations of the nMOS and the
pMOS transistors such that the switching threshold is Vth = 1.5V.

(b)Design the circuit described by the Boolean function Y = A .( B+C )( D+E ) using CMOS logic.
Calculate the equivalent CMOS inverter circuit for simultaneous switching of all inputs assuming that

( WL )=5 for pMOS transistor and

( WL )=2 for all nMOS transistor.
(c) Define the terns Controllability and Observability.
4. Attempt any Two parts of the following
Write short notes on of the following
(i) Dynamic CMOS logic families
(ii)
(iii) Low power CMOS VLSI designs Techniques
5. (a)What do you understand from BIST? Explain PRPG and ORA.
(b)Discuss the operation of single stage shift register circuits Design a SR flip-flop using CMOS circuits.
(c) Classify various fault models

EEC-703
Roll No.

B.Tech.
(SEM VII) SEMESTER THEORY EXAMINATION, 2014-15
VLSI DESIGN
 Time: 3 Hours Maximum Marks:100
Note: Attempt all questions.
All questions carry equal marks

Q.1. Write a short notes on any two of the following

(a) VLSI design methodology (Y Chart) & MOS Scaling

(b) CAD Tools for VLSI Design
(c) Layout design process of CMOS inverter. Draw a stick diagram of CMOS NOR gate.
Q.2. Attempt any two parts of the following 10X2

(a) Consider a CMOS inverter circuits with the following parameters V DD = 3.3V, VTon = 0.6V, VTop=
-0.7V, kn = 200µA/V2, kp= 80µA/V2, kR = 2.5 Calculate the noise margin of the circuits.
(b) Consider a CMOS inverter, with the following device parameters, V DD = 3.V, VTon = 0.6V, VTop =
W
( )
-0.7V , µnCox = 60µA/V2, µpCox = 20µA/V2, λ= 0. Determine the L rations of the nMOS and
the pMOS transistors such that the switching threshold is Vth = 1.5V.

(c) Design the circuit described by the Boolean function Y = A .( B+C )( D+E ) using CMOS logic.
Calculate the equivalent CMOS inverter circuit for simultaneous switching of all inputs assuming

that
( W
L ) =5 (
for pMOS transistor and L
W
)=2 for all nMOS transistor.
Q.3. Attempt any two parts of the following 10X2

(a) Discuss the classification of Dynamic CMOS logic families. Discuss the operation of pass transistor
in dynamic logic circuit..
(b) Explain the CMOS inverter switching characteristic using the digital model and explain the
definitions of delays and transition times.
(c) Estimate the intrinsic propagation delay t PHL+tPLH of a three-input NOR gate using minimum size
transistor (Rn=8kΩ, Rp=24kΩ and Coutn =4.8fF).Estimate the circuit delay also when the gate is
driving a load capacitance of 100fF.
Q.4. Attempt any two parts of the following 10X2

(a) Discuss the Elmore Delay.

(b) Discuss the operation of single stage shift register circuits Design a SR flip-flop using CMOS
circuits.

(c) In a logic Design logic function is Z=( A . B .C ) ( A +B ) (C +B ) implemented with

(i) CMOS circuit diagram
(ii) Domino CMOS circuits diagram

Q. 5. Attempt any four parts of the following 5X4

(a) Define the terns Controllability and Observability. Explain the implementation of Built-In Self Test
(BIST) design techniques for VLSI circuit testing.

(b) Write short notes on low power CMOS VLSI designs Techniques.
(c) Discuss the operation of CMOS SRAM cell circuit.

EEC-703
Roll No.

B.Tech.
(SEM VII) SEMESTER THEORY EXAMINATION, 2014-15
VLSI DESIGN

Time: 3 Hours Maximum Marks:100

Note: Attempt all questions.
All questions carry equal marks

Q.1. Attempt any four parts of the following 5X4

(a) Define VLSI design methodology (Y Chart) & MOS Scaling

(b) Explain the CAD Tools for VLSI Design
(c) Discuss the classification of CMOS digital logic families.
(d) Draw a 4X1 Multiplexer using Transmission Gate (TG).
(e) For an n channel MOS transistor with µ n = 60cm2µA/V-s, Cox = 7.10-8 F/cm2, W = 20µm, L=2µm
and VT0 = 1.0V. Examine the relationship between the drain current and the terminal voltages.
(f) Explain the CMOS inverter switching characteristic and explain the definitions of delays and
transition times.

Q.2. Attempt any two parts of the following 10X2

(a) Enlist the Layout design process and design rules of CMOS circuit. Draw a stick diagram of CMOS
NOR gate.
(b) Consider a CMOS inverter circuits with the following parameters V DD = 3.3V, VTon = 0.6V, VTop=
-0.7V, kn = 200µA/V2, kp= 80µA/V2, kR = 2.5 Calculate the noise margin of the circuits.
(c) Consider a CMOS inverter, with the following device parameters, V DD = 5V, VTon = 0.6V, VTop =
W
( )
-0.7V , µnCox = 60µA/V2, µpCox = 20µA/V2, λ= 0. Determine the L rations of the nMOS and
the pMOS transistors such that the switching threshold is Vth = 2.5V.
Q.3. Attempt any four parts of the following 5X4

(a) Discuss the Elmore Delay.

(b) Discuss the classification of Dynamic CMOS logic families.
(c) Discuss the operation of pass transistor in dynamic logic circuit.

(d) In a logic Design logic function is Z=( A + B+C+ D )( E+ F +G ) ( H + I ) implemented with

domino CMOS circuits diagram with implements Z.
(e) Discuss the overview of Power Consumption in CMOS logic circuits.
(f) Design 2 input EXOR Logic Gate using CMOS Transmission Gate.
Q.4. Attempt any two parts of the following 10X2

(a) In a CMOS inverter power supply VDD =5V, determine the fall time, which is define as the time
elapsed between the time point at which V out=V90% = 4.5V and the time point at which Vout=V10% =0.5.
The output load capacitance is 1pF. The nMOS transistor parameters are as follows: V Tn = 1.0V,

V2
µnCox = 20µA/ ,
W
L n
( )
=10
.

(b) Design the circuit described by the Boolean function Y = A .( B+C )( D+E ) using CMOS logic.
Calculate the equivalent CMOS inverter circuit for simultaneous switching of all inputs assuming

that
( WL )=10 for pMOS transistor and
( WL )=5 for all nMOS transistor.
(c) Discuss the operation of single stage shift register circuits. Design a SR flip-flop using CMOS
circuits.

Q. 5. Attempt any four parts of the following 5X4

(a) Define the terns Controllability and Observability.

(b) Explain the implementation of Built-In Self Test (BIST) design techniques for VLSI circuit testing.
(c) Design a D flip-flop using CMOS Transmission Gate circuits.
(d) Discuss the operation of CMOS SRAM cell circuit.
(e) Write short notes on Adiabatic CMOS logic. Design an adiabatic 2 input AND/NAND
(f) Discuss the low power MTCMOS VLSI designs techniques.
 ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

SESSION- 2020-21(ODD Semester)

REC 702 VLSI DESIGN

Name of
VLSI DESIGN Semester 7
Subject
Name Of
Dr. SUBODH WAIRYA
Faculty
Subject Name of the Subject
L T P CT TA Total ESE Credit
Code Subject Total
REC 702 VLSI Design 3 0 0 20 10 30 70 100 3

Course Objective: student will be able to:

1. Attain knowledge about the basic concepts of VLSI and its circuit
designing.
2. Understand the MOS inverters and its characteristics.
3. Implement and analyze combinational and sequential CMOS logic circuits.
4. Gain the knowledge of Dynamic logic circuits and semiconductor memories.
5. Develop the knowledge of low power VLSI designing and testing (design)
techniques.

S. No. Course outcomes according to Bloom’s cognitive Level

1 REC702. Discover Different kinds of VLSI Design Methodologies, VLSI Design Flow,
1 Design Hierarchy, Concepts of Regularity, Modularity and
Locality .MOSFET Fabrication. Scaling and Small geometry effects and
capacitances

2 REC702. Demonstration of MOS Inverters like Resistive Load and CMOS Inverter and its
2 switching Characteristics.

3 REC702. Analysis of Combinational MOS Logic Circuits with CMOS transmission gates
3 (pass gates) and Sequential MOS Logic Circuits and CMOS D latch and edge
triggered FF.
4 REC702. Illustration of basic principle of pass transistor Circuits and introduction of
4 Semiconductor memories like DRAM, SRAM, ROM, flash memory.

5 REC702. Discuss MOS concepts and also introduction of Low – Power CMOS Logic Circuits
5 and Design for Testability.

Course Outcomes:
REC702.1 basic VLSI design technologies and Scaling
Describe and apply fundamentals
(CO1)
and small scale geometry effects.
REC702.2 Demonstrate MOS Inverters like Resistive Load and CMOS Inverter and its
(CO2) switching Characteristics.
REC702.3 Solve Combinational and Sequential MOS Logics and SR latch circuits, clocked
(CO3) latch and FF circuits, CMOS D latch and edge triggered FF.
REC702.4 Classify and explain pass transistors and Semiconductor memories.
(CO4)
REC702.5 Summarize MOS concepts and invent Low – Power CMOS Logic Circuits and assemble
(CO5) the knowledge for testing of design.

1 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)&
Program Specific Outcomes
 ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW

2 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)&
Program Specific Outcomes
 ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW

Mapping Course Outcomes with Program Outcomes

Correlation Matrix Note: Enter numbers 1, 2 or 3, where the correlation levels are matching
1. Slightly (Low), 2. Moderately (Medium), 3. Substantially (High).
If there is no correlation, the cell is to be left blank or put -).

Course PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
Outcomes
REC702.1 3 1 1 - - - - - - - - -
(CO1)
REC702.2 2 2 2 1 - - - - - - - -
(CO2)
REC702.3 2 3 1 2 2 - - - - - - -
(CO3)
REC702.4 2 2 3 3 - - - - - - - -
(CO4)
REC702.5 2 2 2 - - - 2 - - - - 2
(CO5)
Average 2 2 2 2.5 2 - 2 - - - - 2

Course PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
Outcomes
REC702.1 H L L - - - - - - - - -
(CO1)
REC702.2 M M M L - - - - - - - -
(CO2)
REC702.3 M H L M M - - - - - - -
(CO3)
REC702.4 M M H H - - - - - - - -
(CO4)
REC702.5 M M M - - - M - - - - M
(CO5)
Average M M M M M - M - - - - M

Justification of CO-PO Mapping:

CO1 with PO1 The students will have a proper knowledge of VLSI Design Methodologies.

CO1 with PO2 The students can solve basic problems pertaining to MOS
CO1 with PO3 The students can be able to design proper design flow of circuits.

CO2 with PO1 The students will gain knowledge of basic MOS inverters and its switching
characteristics.
CO2 with PO2 The students can solve problems basic MOS inverters and its switching
characteristics.
CO2 with PO3 The students can be able to design basic MOS inverters and its switching
characteristics.
CO2 with PO4 The students can attempt to solve complex problems pertaining to MOS
inverters and its switching characteristics.
CO3 with PO1 The students will have a proper knowledge of Combinational MOS Logic
Circuits and Sequential MOS Logic Circuits.

3 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)&
Program Specific Outcomes
 ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW

CO3 with PO2 The students can analyse problems with respect to Combinational MOS
Logic Circuits and Sequential MOS Logic Circuits.
CO3 with PO3 The students can design efficient Combinational MOS Logic Circuits and
Sequential MOS Logic Circuits.
CO3 with PO4 The students can develop complex models and solve problems relating to
Combinational MOS Logic Circuits and Sequential MOS Logic Circuits.
CO4 with PO1 The students will learn basic principle of pass transistor Circuits and
introduction of Semiconductor memories like DRAM, SRAM, ROM, flash
memory.
CO4 with PO2 Students can solve basic problems relating to pass transistors.

CO4 with PO3 The students can be able to design CMOS transmission gates (pass gates),SR
latch circuits, clocked latch and FF circuits, CMOS D latch and
edge triggered FF.
CO4 with PO4 The students can calculate complex problem of Sequential MOS Logic
Circuits like Dynamic CMOS circuits.
CO5 with PO1 The students can be able to test different types of digital systems and Fault
types and models.
CO5 with PO2 The students can be able to design Low – Power CMOS Logic Circuits.

CO5with PO3 The students can be able to design the needful MOS circuits and their power
consumption techniques.
CO5with PO7 The students can design low power MOS circuits and better power
consumption techniques for sustainability of environment
CO5with PO12 Life long learning of VLSI design

Mapping Course Outcomes with Program Specific Outcomes:

Course Outcomes Program Specific Outcomes
PSO1 PSO2 PSO3

REC702.1 (CO1) 3 - 2
REC702.2 (CO2) 3 3 2
REC702.3 (CO3) - 3 -
REC702.4 (CO4) - - 2
REC702.5 (CO5) - - 3
Average 3 3 2.25

 Degree ( Program) Outcomes (Program Specific Outcomes as defined by the

Degree course)

PSO An ability to understand the concepts of basic Electronics & Communication

1 Engineering and to apply them to various areas like Signal processing, VLSI,
Embedded systems, Communication Systems, Digital & Analog Devices, etc
PSO An ability to solve complex Electronics and Communication Engineering
2 problems, using latest hardware and software tools, along with analytical skills to
arrive cost effective and appropriate solutions.

4 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)&
Program Specific Outcomes
 ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW

PSO Wisdom of social and environmental awareness along with ethical responsibility
3 to have a successful career and to sustain passion and zeal for real-world
applications using optimal resources as an Entrepreneur

5 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)&
Program Specific Outcomes
 ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW

Justification of CO-PSO Mapping:

CO1 with PSO1 The students can be able to apply the concepts basic VLSI design
methods and Scaling and small scale geometry effects.
CO2 with PSO1 The students can implement the various basic design of MOS inverters
and its switching characteristics.
CO2 with PSO2 The students can solve andapply the knowledge of MOS circuits on
Combinational and Sequential MOS Logics..
CO3 with PSO2 The students can solve complex CMOS transmission gates (pass
gates),SR latch circuits, clocked latch and FF circuits, CMOS
D latch and edge triggered FF.
CO4 with PSO3 The students can integrate all the knowledge regarding MOS circuits on
integrated with its implementation.
CO5 with PSO3 The students can assemble all the information of low power dissipation
which is the necessity of real world applications.
Contribution to Outcomes will be achieved through content delivery:
Modes of content delivery:
i Classroom Teaching v Self-Learning Online Resources ix Industry Visit
ii Assignment/Tutorial vi Slides x Group Discussion
iii Remedial Coaching vii Simulations/Demonstrations xi Seminar/Oral
iv Lab Experiment viii Expert Lecture xii Case Study

CO Mapping With Content

Modes of Delivery
S. Course i ii iii iv v vi vii viii ix x xi xii
No Outcomes
1 REC702.1 x x
(CO1)
2 REC702.2 x x x x
(CO2)
3 REC702.3 x x
(CO3)
4 REC702.4 x x
(CO4)
5 REC702.5 x x x
(CO5)

6 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)&
Program Specific Outcomes
 ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW

EC 703 VLSI DESIGN 3 1 0

Unit Topics Lectures
Introduction: Overview of VLSI Design Methodologies, VLSI Design Flow, 8
Design Hierarchy, Concepts of Regularity, Modularity and Locality MOSFET
Fabrication: Fabrication process flow, NMOS and CMOS fabrication, layout
I design rules, stick diagram and mask layout design.
MOS Transistor : MOS Structure, The MOS System under external bias,
Operation of MOSFET, MOSFET - Current /Voltage Characteristics, Scaling
and Small geometry effects and capacitances
MOS Inverters: Introduction, Resistive Load Inverter, Inverters 8
with n-type
MOSFET load, CMOS Inverter.
MOS Inverters - Switching Characteristics: Introduction, Delay –
II
Time
Definitions, Calculation of Delay Times, and Inverter Design with
Delay
Constraints.
Combinational MOS Logic Circuits: Introduction, MOS logic 8
circuits with
depletion NMOS Loads, CMOS logic circuits, complex logic
circuits, CMOS
III
Transmission gates (pass gates).Sequential MOS Logic Circuits:
Introduction, behavior bistable elements SR latch circuits,
clocked latch and FF circuits, CMOS D latch and edge triggered
FF..
Dynamic logic circuits: Introduction, basic principle of pass transistor 8
circuits, synchronous dynamic circuit techniques, dynamic CMOS circuit
IV
Techniques, domino CMOS logic. Semiconductor memories: Introduction,
DRAM, SRAM, ROM, flash memory.
Low – Power CMOS Logic Circuits: Introduction, Overview of Power 8
Consumption, Low – Power Design through voltage scaling, Estimation and
Optimization of switching activity, Reduction of Switched Capacitance and
V
Adiabatic Logic Circuits. Design for Testability: Introduction, Fault Types and
Models, Controllability and Observability, Ad Hoc Testable Design Techniques,
Scan Based and BIST Techniques
Content beyond the Syllabus:
1. Students will be encourage to simulate the MOS structureson PSPICE software.
2.Design of innovative application oriented MOS (Combinational and Sequential) circuitsusing
Hobby Circuits.
3. Industry based applicationof VLSI and embedded system is encouraged.
Text Book:
1. Sung-Mo Kang & Yosuf Leblebici, “CMOS Digital Integrated Circuits: Analysis
&Design”, TMH, 3rd Edition.
Reference Books:
1. D. A. Pucknell and K. Eshraghian, “Basic VLSI Design: Systems and
Circuits”,PHI, 3rd Ed., 1994.
2. W.Wolf, Modern VLSI Design: System on Chip, Third Edition, Pearson, 2002.
3. Rabaey,Pedram,“LowPowerDesignMethodologies”KluwerAcademic,1997

Action Words For Bloom’s Taxonomy

7 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)&
Program Specific Outcomes
 ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW

Knowledge Understand Apply Analyze Evaluate Creat

e
Define Explain Solve Analyze Reframe Design
Identify Describe Apply Compare Criticize Compose
Describe Interpret Illustrate Classify Evaluate Create
Label Paraphrase Modify Contrast Order Plan
List Summarize Use Distinguish Appraise Combine
Name Classify Calculate Infer Judge Formulate
State Compare Change Separate Support Invent
Match Differentiate Choose Explain Compare Hypothesize
Recognize Discuss Demonstrate Select Decide Substitute
Select Distinguish Discover Categorize Discriminate Write
Examine Extend Experiment Connect Recommend Compile
Locate Predict Relate Differentiate Summarize Construct
Memorize Associate Show Discriminate Assess Develop
Quote Contrast Sketch Divide Choose Generalize
Recall Convert Complete Order Convince Integrate
Reproduce Demonstrate Construct Point Out Defend Modify
Tabulate Estimate Dramatize Prioritize Estimate Organize
Tell Express Interpret Subdivide Find Errors Prepare
Copy Identify Manipulate Survey Grade Produce
Discover Indicate Paint Advertise Measure Rearrange
Duplicate Infer Prepare Appraise Predict Rewrite
Enumerate Relate Produce Break Down Rank Role-Play
Listen Restate Report Calculate Score Adapt
Observe Select Teach Conclude Select Anticipate
Omit Translate Act Correlate Test Arrange
Read Ask Administer Criticize Argue Assemble
Recite Cite Articulate Deduce Conclude Choose
Record Discover Chart Devise Consider Collaborate
Repeat Generalize Collect Diagram Critique Collect
Retell Give Compute Dissect Debate Devise
Visualize Examples Determine Estimate Distinguish Express
Group Develop Evaluate Editorialize Facilitate
Illustrate Employ Experiment Justify Imagine
Judge Establish Focus Persuade Infer
Observe Examine Illustrate Rate Intervene
Order Explain Organize Weigh Justify
Report Interview Outline Make
Represent Judge Plan Manage
Research List Question Negotiate
Review Operate Test Originate
Rewrite Practice Propose
Show Predict Reorganize
Trace Record Report
Transform Schedule Revise
Simulate Schematize
Transfer Simulate
Write Solve
Speculate
Structure
Support
Test
Validate

8 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)&
Program Specific Outcomes
 ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW

Establish the correlation between the courses and the Program Outcomes(POs)& Program Specific
Outcomes
(Program Outcomes as mentioned in Annexure I and Program Specific Outcomes as defined by the Program)

PO1 Engineering Knowledge: Apply knowledge of mathematics and science, with fundamentals
of Electronics and Communication Engineering to be able to solve complex engineering
problems related to ECE.
PO2 Problem Analysis: Identify, Formulate, review research literature and analyze complex
engineering problems related to ECE and reaching substantiated conclusions using first
principles of mathematics, natural sciences and engineering sciences.
PO3 Design/Development of solutions: Design solutions for complex engineering problems related to
ECE and design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety and the cultural societal and environmental
considerations.
PO4 Conduct Investigations of Complex problems: Use research–based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
PO5 Modern Tool Usage: Create, Select and apply appropriate techniques, resources and modern
engineering and IT tools including prediction and modeling to Electronics Engineering related
complex engineering activities with an understanding of the limitations.
PO6 The Engineer and Society: Apply Reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
ECE professional Engineering practice.
PO7 Environment and Sustainability: Understand the impact of the ECE professional
engineering solutions in societal and environmental contexts and demonstrate the knowledge
of, and need for sustainable development
PO8 Ethics: Apply Ethical Principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
PO9 Individual and Team Work: Function effectively as an individual and as a member or leader in
diverse teams and in multidisciplinary Settings
PO10 Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large such as able to comprehend and with write
effective reports and design documentation, make effective presentations and give and receive
PO11 Project Management and Finance: Demonstrate knowledge and understanding of the
engineering management principles and apply these to one’s own work, as a member and leader in
a team, to manage projects and in multi-disciplinary environments.
PO12 Life-Long Learning: Recognize the need for and have the preparation and ability to
engage in independent and life-long learning the broadest context of technological change.

 List of PSO’s
PSO1 An ability to understand the concepts of basic Electronics & Communication Engineering and to
apply them to various areas like Signal processing, VLSI, Embedded systems, Communication
Systems, Digital & Analog Devices, etc
PSO2 An ability to solve complex Electronics and Communication Engineering problems, using latest
hardware and software tools, along with analytical skills to arrive cost effective and appropriate
solutions.
PSO3 Wisdom of social and environmental awareness along with ethical responsibility to have a
successful career and to sustain passion and zeal for real-world applications using optimal
resources as an Entrepreneur

EEC-703
Roll No.

B.Tech.

9 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)&
Program Specific Outcomes
 ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW

(SEM VII) SEMESTER THEORY EXAMINATION, 2014-15

VLSI DESIGN

Time: 3 Hours Maximum Marks:100

Note: Attempt all questions.
All questions carry equal marks

Q.1. Write a short notes on any two of the following

(a) VLSI design methodology (Y Chart) & MOS Scaling and CAD Tools for VLSI Design
(b) Layout design process of CMOS inverter. Draw a stick diagram of CMOS NOR gate.
(c) For an n channel MOS transistor with µn = 60cm2µA/V-s, Cox = 7.10-8 F/cm2, W = 20µm,
L=2µm and VT0 = 1.0V. Examine the relationship between the drain current and the terminal
voltages

Q.2. Attempt any two parts of the following

10X2

(a) Consider a CMOS inverter circuits with the following parameters V DD = 3.3V, VTon = 0.6V,
VTop= -0.7V, kn = 200µA/V2, kp= 80µA/V2, kR = 2.5 Calculate the noise margin of the circuits.
(b) Consider a CMOS inverter, with the following device parameters, V DD = 3.V, VTon = 0.6V,

VTop = -0.7V , µnCox = 60µA/V2, µpCox = 20µA/V2, λ= 0. Determine the

( WL ) rations of the
nMOS and the pMOS transistors such that the switching threshold is Vth = 1.5V.

(c) Design the circuit described by the Boolean function Y =( A+C )( B+C )( D+E ) using
CMOS logic. Calculate the equivalent CMOS inverter circuit for simultaneous switching of

all inputs assuming that

( WL )=10 for pMOS transistor and
( WL )=5 for all nMOS
transistor.

Q.3. Attempt any two parts of the following

10X2

(a) Discuss the classification of Dynamic CMOS logic families. Discuss the operation of pass
transistor in dynamic logic circuit..
(b) Explain the CMOS inverter switching characteristic using the digital model and explain the
definitions of delays and transition times.
(c) Estimate the intrinsic propagation delay t PHL+tPLH of a three-input NOR gate using minimum size
transistor (Rn=8kΩ, Rp=24kΩ and Coutn =4.8fF).Estimate the circuit delay also when the gate is
driving a load capacitance of 100fF.

Q.4. Attempt any two parts of the following

10X2

10 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)&
Program Specific Outcomes
 ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW

(a) Discuss the Elmore Delay. In a CMOS inverter power supply V DD =5V, determine
the fall time, which is define as the time elapsed between the time point at which
Vout=V90% = 4.5V and the time point at which V out=V10% =0.5. The output load
capacitance is 1pF. The nMOS transistor parameters are as follows: V Tn = 1.0V,

µnCox = 20µA/V2,
( WL ) =10
n .
(b) Discuss the operation of single stage shift register circuits Design a D flip-flop using
CMOS circuits.

(c) In a logic Design logic function is Z=( A + B+C+ D )( E+ F +G ) ( H + I )

implemented with inputs (A,E,H) are high and other inputs are low
(i) Draw a full CMOS circuit diagram
(ii) Draw a domino CMOS circuits diagram with implements Z.

Q. 5. Attempt any four parts of the following 5X4

(a) Define the terns Controllability and Observability

(b) Discuss the operation of DRAM cell with suitable CMOS circuits
(c) What do you understand from BIST? Explain PRPG and ORA
(d) Write short notes on Adiabatic CMOS logic. Design an adiabatic 2 input AND/NAND gate
(e) Discuss the low power MTCMOS VLSI designs techniques.

EC-703
Roll No.

B.Tech.
(SEM VII) SEMESTER THEORY EXAMINATION, 2017-18
VLSI DESIGN

Time: 3 Hours Maximum Marks:100

Note: Attempt all questions.
All questions carry equal marks

Q.1. Write a short notes on any two of the following

(a) Discuss the classification of CMOS logic families. Discuss the operation of pass transistor in
dynamic logic circuit.

11 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)&
Program Specific Outcomes
 ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW

(b) Draw Y Chart (VLSI design methodology) and explain MOS Scaling. CAD Tools for VLSI
Design in brief
(c) For an n channel MOS transistor with µn = 60cm2µA/V-s, Cox = 7.10-8 F/cm2, W = 20µm,
L=2µm and VT0 = 1.0V. Examine the relationship between the drain current and the terminal
voltages.
(d) Draw a 4X1 Multiplexer using Transmission Gate (TG).
(e) Discuss the operation of CMOS 6T SRAM cell circuit.

(f) Using AOI logic Implement the logic function Z=A +B C+CD

Q.2. Attempt any two parts of the following

10X2

(a) Consider a CMOS inverter circuits with the following parameters V DD = 3.3V, VTon = 0.6V,
VTop= -0.7V, kn = 200µA/V2, kp= 80µA/V2, kR = 2.5 Calculate the noise margin of the circuits.
(b) Consider a CMOS inverter, with the following device parameters, V DD = 3.V, VTon = 0.6V,

VTop = -0.7V , µnCox = 60µA/V2, µpCox = 20µA/V2, λ= 0. Determine the

( WL ) rations of the
nMOS and the pMOS transistors such that the switching threshold is Vth = 1.5V.

(c) Design the circuit described by the Boolean function Y =( A+C )( B+C )( D+E ) using
CMOS logic. Calculate the equivalent CMOS inverter circuit for simultaneous switching of

all inputs assuming that

( WL )=10 for pMOS transistor and
( WL )=5 for all nMOS
transistor.

12 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)&
Program Specific Outcomes
 ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT, IET LUCKNOW

Q.3. Attempt any two parts of the following

10X2

(a) Explain the CMOS inverter switching characteristic using the digital model. Estimate the
propagation delay of a minimum size inverter driving a 100fF capacitor W p=Wn= 3µm Lp=Ln=
2µm. Cox=800aF/µm2 Rn=12kΩ and Rp=36kΩ
(b) Estimate the intrinsic propagation delay t PHL+tPLH of a three-input NAND gate using minimum
size transistor (Rn=8kΩ, Rp=24kΩ and Coutn =4.8fF).Estimate the circuit delay also when the gate
is driving a load capacitance of 100fF.
(c) Design a five stage ring oscillator with Wn =Wp=10µm. determine the oscillation frequency

Q.4. Attempt any two parts of the following

10X2

(a) Discuss the operation of single stage shift register circuits Design a D flip-flop using
CMOS circuits.
(b) Discuss the Elmore Delay. In a CMOS inverter power supply V DD =5V, determine the
fall time, which is define as the time elapsed between the time point at which V out=V90% =
4.5V and the time point at which V out=V10% =0.5. The output load capacitance is 1pF. The

2
nMOS transistor parameters are as follows: VTn = 1.0V, µnCox = 20µA/V ,
W
L n
=10
.
( )
(c) In a domino CMOS circuits logic function Z is implemented with inputs (A,E,H) are high and

other inputs are low. Z=( A + B+C+ D )( E+ F +G ) ( H + I )

Q. 5. Attempt any four parts of the following 5X4

(a) Classify various fault models. Define the terns Controllability and Observability.
(b) Discuss the operation of DRAM cell with suitable CMOS circuits
(c) What do you understand from BIST? Explain PRPG and ORA
(d) Write short notes on Adiabatic CMOS logic. Design an adiabatic 2 input AND/NAND gate
(e) Discuss the low power MTCMOS VLSI designs techniques.
(f) Draw a stick diagram of CMOS NAND logic gate.

13 EC 703 Establish the correlation between the courses and the Program Outcomes (POs)&
Program Specific Outcomes
 ELECTRONICS AND COMMUNICATION ENGINEERING
SECOND MID SEMESTER EXAMINATION 2018-19
EC 703 VLSI DESIGN
TIME: 1 HOUR MAX MARKS:30
* Attempt Any 6 Questions
Q. Question Paper Based On Course Outcomes According To Bloom's Cognitive Level Marks CO BL
1 Elaborate how domino CMOS logic overcomes charge sharing problem 5 CO4 L4
with a suitable example.
2 Discuss transmission gates.Implement a 4*1 multiplexer using 5 CO3 L4
transmission gate.
3 Design circuit described by the boolean function Y= A . ¿B+C)(D+E) using CMOS 5 CO3 L4
logic.Calculate equivalent CMOS inverter circuit for simultaneous switching of all inputs
assuming that (W/L)=10 for all pMOS transistor and (W/L)= 5 for all nMOS transistor.
4 Draw a Domino CMOS diagram circuit that implements the following equation Z= 5 CO3 L4
(A+B+C+D)(E+F+G)(H+I) . Assume that only A,E,H inputs are high and other inputs are
low, then draw and equivalent circuit for this case by using (W/L)=30/2 for all transistors.
5 Discuss the operation of CMOS SRAM with its circuit diagram 5 CO4 L2
6 Consider CMOS inverter circuit with lumped output capacitance having V DD = 3.3 V. The I-V 5 CO2 L4
characteristics of the nMOS transistor are specified as follows: when V GS = 3.3 V, the drain
current reaches its saturation level Isat = 2 mA for V DS ≥2.5 V. The input signal applied is a
step pulse that switches instantaneously from 0 V to 3.3 V. Calculate the delay time necessary
for the output to fall from its initial value of 3.3 V to 1.65 V, assuming an output load
capacitance of 300 fF.
7 Draw the digital model of CMOS inverter and derive the expression for delay times. 5 CO2 L3
8 Define the terms Controllability and Observability. Write a short note on built in self 5 CO5 L1
test(BIST) technique

ELECTRONICS AND COMMUNICATION ENGINEERING

SECOND MID SEMESTER EXAMINATION 2018-19
EC 703 VLSI DESIGN
TIME: 1 HOUR MAX MARKS: 30
* Attempt Any 6 Questions
Q. Question Paper Based On Course Outcomes According To Bloom's Cognitive Level Marks CO BL
1 Elaborate how domino CMOS logic overcomes charge sharing problem 5 CO4 L4
with a suitable example.
2 Discuss transmission gates. Implement a 4*1 multiplexer using 5 CO3 L4
transmission gate.
3 Design circuit described by the boolean function Y= A . ¿B+C)(D+E) using CMOS 5 CO3 L4
logic.Calculate equivalent CMOS inverter circuit for simultaneous switching of all inputs
assuming that (W/L)=10 for all pmos transistor and (W/L)= 5 for all nmos transistor.
4 Draw a Domino CMOS diagram circuit that implements the following equation Z= 5 CO3 L4
(A+B+C+D)(E+F+G)(H+I) . Assume that only A,E,H inputs are high and other inputs are
low, then draw and equivalent circuit for this case by using (W/L)= 30/2 for all transistors.
5 Discuss the operation of CMOS SRAM with its circuit diagram 5 CO4 L2
6 Consider CMOS inverter circuit with lumped output capacitance having V DD = 3.3 V. The I-V 5 CO2 L4
characteristics of the nMOS transistor are specified as follows: when V GS = 3.3 V, the drain
current reaches its saturation level Isat = 2 mA for V DS ≥2.5 V. The input signal applied is a
step pulse that switches instantaneously from 0 V to 3.3 V. Calculate the delay time necessary
for the output to fall from its initial value of 3.3 V to 1.65 V, assuming an output load
capacitance of 300 fF.
7 Draw the digital model of CMOS inverter and derive the expression for delay times. 5 CO2 L3
8 Define the terms Controllability and Observability. Write a short note on built in self 5 CO5 L1
test(BIST) technique
EEC-703
Roll No.

B.Tech.
(SEM VII) SEMESTER THEORY EXAMINATION, 2014-15
VLSI DESIGN

Time: 3 Hours Maximum Marks:100

Note: Attempt all questions.
All questions carry equal marks

Q.1. Attempt any two parts of the following 10X2

(a) Define VLSI design methodology (Y Chart) & MOS Scaling and CAD Tools for VLSI Design
(b) Discuss the classification of CMOS digital logic families. Draw a 4X1 Multiplexer using
Transmission Gate (TG).
(c) Explain the CMOS inverter switching characteristic and explain the definitions of delays and
transition times.

Q.2. Attempt any two parts of the following 10X2

(a) Enlist the Layout design process and design rules of CMOS circuit. Draw a stick diagram of CMOS
NOR gate.
(b) Consider a CMOS inverter circuits with the following parameters V DD = 3.3V, VTon = 0.6V, VTop=
-0.7V, kn = 200µA/V2, kp= 80µA/V2, kR = 2.5 Calculate the noise margin of the circuits.
(c) Consider a CMOS inverter, with the following device parameters, V DD = 5V, VTon = 0.6V, VTop =

-0.7V , µnCox = 60µA/V2, µpCox = 20µA/V2, λ= 0. Determine the

( WL ) rations of the nMOS and
the pMOS transistors such that the switching threshold is Vth = 2.5V.
Q.3. Attempt any two parts of the following 10X2

(a) Discuss the classification of Dynamic CMOS logic families. Discuss the operation of pass
transistor in dynamic logic circuit.

(b) In a logic Design logic function is Z=( A + B+C+ D )( E+ F +G ) ( H + I ) implemented

with domino CMOS circuits diagram with implements Z.
(c) Estimate the intrinsic propagation delay t PHL+tPLH of a three-input NOR gate using minimum
size transistor (Rn=8kΩ, Rp=24kΩ and Coutn =4.8fF).Estimate the circuit delay also when the
gate is driving a load capacitance of 100fF.
Q.4. Attempt any two parts of the following 10X2

(a) In a CMOS inverter power supply VDD =5V, determine the fall time, which is define as the time
elapsed between the time point at which V out=V90% = 4.5V and the time point at which Vout=V10% =0.5.
The output load capacitance is 1pF. The nMOS transistor parameters are as follows: V Tn = 1.0V,

V2
µnCox = 20µA/ ,
W
L n
( )
=10
.

(b) Design the circuit described by the Boolean function Y = A .( B+C )( D+E ) using CMOS logic.
Calculate the equivalent CMOS inverter circuit for simultaneous switching of all inputs assuming

that
( WL )=10 for pMOS transistor and
( WL )=5 for all nMOS transistor.
(c) Discuss the operation of single stage shift register circuits. Design a SR flip-flop using CMOS
circuits.

Q. 5. Attempt any four parts of the following 5X4

(a) Define the terns Controllability and Observability.

(b) Explain the implementation of Built-In Self Test (BIST) design techniques for VLSI circuit testing.
(c) Design a D flip-flop using CMOS Transmission Gate circuits.
(d) Discuss the operation of CMOS SRAM cell circuit.
(e) Write short notes on Adiabatic CMOS logic. Design an adiabatic 2 input AND/NAND
(f) Discuss the low power MTCMOS VLSI designs techniques.
 Electronics Engineering Department
B.Tech VII (EC) Second Mid Semester Examination
VLSI Design (EEC-703)
Time: 1.30 Hours Max Marks 30

1. Write short notes on of the following (i) Dynamic CMOS logic families (ii) classify various fault models (iii)
low power CMOS VLSI designs Techniques 10
2. Define the terns Controllability and Observability 4
3. Discuss the operation of SRAM OR DRAM cell with suitable CMOS circuits 4
4. Design an adiabatic 2 input AND/NAND gate and explain it 4
5. What do you understand from BIST? Explain PRPG and ORA 4
6. Discuss the operation of single stage shift register circuits Design a SR flip-flop using CMOS circuits. 4

Electronics Engineering Department

B.Tech VII (EC) Second Mid Semester Examination
VLSI Design (EEC-703)
Time: 1.30 Hours Max Marks 30

1. Write short notes on of the following (i) Dynamic CMOS logic families (ii) classify various fault models (iii)
low power CMOS VLSI designs Techniques 10
2. Define the terns Controllability and Observability 4
3. Discuss the operation of SRAM OR DRAM cell with suitable CMOS circuits 4
4. Design an adiabatic 2 input AND/NAND gate and explain it 4
5. What do you understand from BIST? Explain PRPG and ORA 4
6. Discuss the operation of single stage shift register circuits Design a SR flip-flop using CMOS circuits. 4

Electronics Engineering Department

B.Tech VII (EC) Second Mid Semester Examination
VLSI Design (EEC-703)
Time: 1.30 Hours Max Marks 30

1. Write short notes on of the following (i) Dynamic CMOS logic families (ii) classify various fault models (iii)
low power CMOS VLSI designs Techniques 10
2. Define the terns Controllability and Observability 4
3. Discuss the operation of SRAM OR DRAM cell with suitable CMOS circuits 4
4. Design an adiabatic 2 input AND/NAND gate and explain it. 4
5. What do you understand from BIST? Explain PRPG and ORA 4
6. Discuss the operation of single stage shift register circuits Design a SR flip-flop using CMOS circuits. 4