2014 IEEE Ninth International Conference on Intelligent Sensors, Sensor Networks and Information Processing (ISSNIP)

Symposium on Sensing, Propagation, and Wireless Networks for Healthcare Applications

Singapore, 21–24 April 2014

An Efficient Power Control Scheme for a 2.4GHz

Class-E PA in 0.13-μm CMOS
Luis A. Andia Montes, Kumarasamy Raja, FUHG Wong and Minkyu Je
Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research)
Singapore
[email protected], [email protected], [email protected], [email protected]

Abstract— A novel circuit technique that does not Conventional method of varying the bias of cascoded
compromise the efficiency, while varying the output power of element, implies significant degradation in efficiency at low
power amplifiers, suitable for wireless sensor networks is power levels. Therefore [2] proposes to independently vary
reported in this paper. For robustness sake, the technique allows
to distribute the voltage swing among three cascoded transistors.
two control variables based on a lookup table of supply and
While PA voltage supply is swept for power level control, one of cascode bias voltages. However, in order to reduce the voltage
its common gate transistors conduction angle is varied through a stress over the cascoded transistor, it uses a differential
mirrored current source to guarantee high efficiency at all power structure which in turn needs an external balun. In this work,
levels. To validate the concept, a self-biased triple cascode class E we propose a novel topology of SMPA based on a triple
power amplifier for Bluetooth Class 1 has been designed using a cascode transistor that considerably reduces the stress on the
0.13μm CMOS process. Measurements show that the power
added efficiency (PAE) decreases only by 17.2% from the
active devices while guarantying good power conversion
maximum value of 59.2% over an 18dB power control range with efficiency over a wide power range. The power control is
+20dBm maximum output power. Compared to other state of the exercised by modifying the self-biased structure in [3]. In
work, proposed technique demonstrates a PAE improvement of order to prove the concept, Bluetooth Class 1 application is
15.6% at the highest power, 35% when operated at the lowest selected which requires a maximum power of +20dBm, and
power. employs GFSK modulation scheme that tolerates non-linearity
Keywords— PA efficiency, power control, CMOS class E PA of the class E PA, for energy efficiency. The class E PA
topology is the desired choice for other constant envelope
I. INTRODUCTION modulation schemes such as GMSK in GSM as well [5].
Wireless sensor networks (WSNs) impose stringent emitted
II. POWER AMPLIFIER TOPOLOGY
power level (Po) control techniques to avoid possible
interference and to decrease the wastage of battery power (Pdc) A. Class E Power Amplifier
when the maximum transmitter power is not required from the Figure 1 shows class E SMPA basic topology, while Table I
sensor nodes (SNs). Switch-mode power amplifiers (SMPA) resumes its generalized design equations [4]. The variable q
achieve, theoretically, a power conversion efficiency of 100%. in the equations refers to the quality factor of the parallel tank
In practice, efficiency of about 50% is achieved using highly circuit involving Ld and is defined as,
integrated CMOS technologies in few GHz ranges [1]. The 1
maximum efficiency is attained at maximum output power q= (1)
level, which corresponds to the maximum specified wireless ω LdCsh
range. However, the SNs are closer than the maximum Two parameters are of particular interest for a RF class E
wireless range for most of the time, and if Po is not reduced, it SMPA design. (i) The maximum operation frequency (fmax),
which is the highest frequency at which the transistor behavior
causes (i) receiver saturation, (ii) interference to other wireless
is close to that of a lossless switch, and (ii) the maximum
links in the adjacent channels and (iii) increased dc power
output power (Pmax) for a given voltage supply VDD and load
consumption. The first two damages the link, resulting in R. fmax is a function of the shunt capacitance Csh and R. The
repeated transmissions, wasting the battery energy. Therefore best fmax is obtained by maximizing the expression KC which
Po needs to be controlled with reasonable reduction in dc yields the values q to be 1.468. Pmax is a function of VDD and
power at reduced output power levels, which is normally R, therefore q value for Pmax is obtained by maximizing the
measured by the power efficiency or energy efficiency. expression KP and is 1.412. Since both expression (KC and KP)
However, the published techniques hitherto do not strive for are function of R, a compromise is obtained maximizing the
the best efficiency at lower power levels, at which the PA is product KP*KC for q = 1.442. Table II provides the design
expected to operate most of the time statistically. Therefore, a expressions for this value of q in this design. As stated in
power control technique that does not compromise efficiency Section I, in class-E PA, drain voltage swing is high
significantly across the output power level is required. (=3.56VDD). Hence, for CMOS PAs with watt level output

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978-1-4799-2843-9/14/$31.00 © 2014 IEEE
power, the circuit in figure 1 cannot be used as it is due to
reliability concerns.

Fig. 1. Class E SMPA basic topology. 5

TABLE I
DESIGN EQUATIONS FOR 1.0 < q < 1.65
Design Expression Equation Fig. 3. Self-biased class E SMPA with power level control.
KL = ȦLd /R
2
8.085q – 24.53q + 19.23
KC = ȦCshR -6.97q3 + 25.93q2 – 31.071q + 12.48
2
KP = PoutR/VDD -11.9q3 + 8.8q2 – 10.2q + 5.02
KX = X/R -2.9q3 + 8.8q2 – 10.2q + 19.7

Fig. 4. Self-biased class E triple cascode gate and drain voltage waveforms.
TABLE II
DESIGN EQUATIONS FOR q = 1.442
(a) KL KC KP KX
0.689 0.698 1.355 -0.082

B. Self-Biased Cascode Power Amplifier

The classic cascode stacks two identical transistors, the
hybrid solution combine a high voltage (HV) transistor M2
with a RF suited thin gated M1, to obtain watt levels output
power at GHz range frequencies. This arrangement degrades
PA RF performances due to low transition frequency (fT) of
high breakdown transistors (usually thick oxide) as shown in
[3]. Hence, [3] proposed the self-biased cascode topology as a
means to make gate-drain signal swings equal for the common
gate and common source transistors. Figure 2(a) shows the
circuit topology and figure 2(b) shows the transistors gate
(VGi) and drain (VDi) transient voltage waveforms,
respectively. However, this topology does not allow, efficient
(b)
Fig. 2. Self-biased class E SMPA (a) topology, and (b) Simulated potential power control, since the gate bias of M2 follows the drain and
differences of VD1, VG1, VD2, VG2. cannot be independently varied.
C. Power Control Scheme
To ensure efficient power control and better circuit
reliability by suitably distributing voltage swing among

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transistors of a cascoded PA, freedom to independently vary low enough (up to 10μA) so that it is not significant to the PA
cascode bias voltage and supply voltage is desirable. To total current consumption budget. All capacitors are standard
overcome this impasse, while guarantying hybrid self-biased metal-insulator-metal (MIM) structures. Inductances Ld and L0
cascode class E performance (to ensure good RF and power are composed by bond-wires and external inductors.
output capabilities), a third cascode active element, M3 in
Figure 3, is introduced. Conduction angle of M3 is controlled IV. MEASUREMENT RESULTS
by the gate bias derived from the diode connected MOSFET The circuit has been fabricated in a six metal layer 0.13μm
M4. M4 drain current is controlled by a current digital to CMOS technology from Global Foundries. The process
analog converter (I-DAC). The variable (often programmable) supports MIM capacitor option. A photo of the die is shown in
current from I-DAC termed as ICTRL, determines the gate bias Figure 5. It occupies an area of (430 x 270) μm2, while the die
of M3, determining the conduction angle. Therefore PA output size including the test pads for on-wafer and guard ring is (910
power level is set by the combination of supply voltage (VDD) x 660) μm2. In order to assure low ground parasitic
and I-DAC current, ICTRL. The right combination leads to the inductance, six DC ground pads had been implemented in the
optimal PAE throughout the output power range. The gate bias circuit.
of M5 is denoted as VREF, since in a complete transceiver,
this voltage is derived from the bandgap circuit

III. CIRCUIT DESIGN

The PA is designed around two stages. The first stage is a
classic inverter driver formed by multi-finger N-MOS and P-
MOS transistors. It helps to increase the signal swing almost
from VDD to ground, from a weak input signal. Thus, the swing
is enough to drive M1, so that it acts like a switch of the class
E SMPA.
SMPA circuit is shown in Figure 3. M2 is a thick oxide
3.3V device. It has high drain to source breakdown voltage,
BVds >10V at 125°C. Transistors M1 and M3 are thin oxide
MOSFETs designed to work with a 1.5V voltage supply, they
exhibit a BVds >3.5V at 125°C. As the PA is intended, in a
Fig. 5. Chip photograph.
future application, to be fully integrated in a system on chip
(SoC), all N-MOSFET transistors are placed over a deep n-
SMPA was operated with a supply voltage of 3.3V.
well structure. Deep n-well structure help isolate the PA,
Common gate transistor, M2, gate bias voltage (VGG) has
reducing substrate noise in the SoC without degrading
been set to 2.8V and the bias voltage VREF is set to 480mV.
transistor RF performances or modifying its AC and DC
VGG and VREF current consumption is negligible and
behavior. Circuit transistors M1, M2 and M3 voltage swing
therefore has very limited influence on PA power conversion
magnitude dynamics (maximum and minimum) are controlled
efficiency. SMPA input and output were matched to 50ȍ. It
by the low pass filter formed by R1, R2, Rb and Cb. Therefore
has been tested under a continuous wave (CW) input signal in
this values are chosen in order not to overpass transistors
the Bluetooth frequency band from 2.4 to 2.4835GHz.
respective BVds. At the same time, M3 output impedance is
Figure 6 shows measurements results of the maximum
dimensioned to match transistor M2 input impedance.
output power, +20dBm, as a function of the frequency for a
To ensure device reliability, simulations are conducted to
constant input power of -2dBm. Power gain and output power
validate the drain voltage swing maximum amplitude for M1,
(Pout) remain almost flat all over the frequency band. PAE
M2 and M3. Figure 4, shows simulated gate and drain
variation is only 1% across the band. The SMPA draws 51mA
voltages for all three transistors at maximum output power,
from 3.3V supply, while the inverter driver draws 11mA from
+20dBm. It shows all transistors have Vds less than the
a 1.5V supply.
maximum breakdown voltage allowed.
In order to provide a better picture of the advantage in terms
The design expressions contained in Table II are used to
of power conversion efficiency, of the technique proposed in
obtain the value of class E network elements, Csh, and Ld. The
the present paper, the PAE of the SMPA under three different
load R is kept constant and equal to 50ȍ. High efficiency class
output power control techniques has been measured for
E operation is based on the capability of the passive element
different output power levels while keeping a constant input
network, more precisely Csh, to absorb active element(s)
power of -2dBm. Using the first control technique, dynamic
parasitic drain-to-source capacitance, CDS. Special care had be
supply (DS), the output power is varied from +2 to +20dBm
attached to calculate, through simulations, the equivalent
sweeping VDD from 0.7V to 3.3V while keeping ICTRL
parasitic capacitance CDS of M2 and subtract it from the
constant and equal to 10μA. Using the second technique,
calculated Csh one to account for it. Control current ICTRL is

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dynamic cascode bias (DCB), the output power level is Table III provides a comparison between the performances
controlled in the same range, from +2 to +20dBm, sweeping of the proposed PA topology together with the implemented
ICTRL from 2μA to 10μA while keeping VDD constant and power control technique and some of the most representative
equal to 3.3V. For the third control technique, which is the one alternatives in the same frequency band and with similar
proposed in the present paper and is a combination of the two maximum output power levels and targetted Class I Bluetooth
previous ones (DS+DCB), the combination of ICTRL and VDD applications. Compared to the best among the state of the art
that leads to maximum PAE has been used to obtain the curve [2], proposed technique demonstrates a PAE improvement of
reported in Figure 7. 15.6% at the highest power. To make a fair comparison at
Figure 7 compares the evolution of the power amplifier PAE lowest power, PAE of [2] at a power level of 5 dBm, is
for the same output power levels range for all three described comapared. [2] shows a PAE of 7% at 5 dBm output power
power control techniques. A difference of around 12% PAE is and therefore the improvement in efficiency at the lowest
observed between DS and DS+ DCB techniques for the lowest power level is 35%.
power level of the range. All three techniques have been
applied to the same fabricated circuit. . V. CONCLUSION
A new power control technique for highly efficient wide
power range cascode power amplifier meant for wireless
sensor networks (WSNs) is demonstrated in 0.13μm CMOS.
The technique does not use any power combining technique or
differential topology to distribute the voltage stress within a
single-ended SMPA, and does not need an external balun.
Measurement results show a degradation of no more than 17%
PAE over 18dB output power range, with the dual use of
dynamic voltage supply and current bias. While employing
low-Q inductors, it demonstrates a PAE improvement of
15.6% at the highest power, and the improvement is 35%,
when operated at the lowest power, when compared to the
state of the art, which increases the battery life of sensor nodes
in WSNs.
Fig. 6. Measured Pout, Gain and PAE versus frequency.
ACKNOWLEDGMENT
Authors would like to thank IME’s Integrated Circuits &
Systems (ICS) staff members for fruitful discussions and CAD
support team for drawing the mask.

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