RISC-V; CALL

CS110 Discussion 5

Suting Chen
 RISC-V Instructions
Di erent types
ff
RISC-V Instructions
What are those?

• func7, func3, opcode — Help CPU identify type of instruction

• rd — The place to “write to”

• rs1, rs2 — The place to “read from”

• imm — “Numbers”
RISC-V Instructions
R-type

• add, sub, xor, or, and — addition/substract/bit ops

• sll, srl, sra — bit shiftings

• slt, sltu — comparisons

RISC-V Instructions
R-type — add, sub, xor, or, and

add rd rs1 rs2

sub rd rs1 rs2
xor rd rs1 rs2
or rd rs1 rs2
and rd rs1 rs2
RISC-V Instructions
R-type — add, sub, xor, or, and

t3 = t1 + t2 add t3 t1 t2

a1 = a6 - a0 sub a1 a6 a0

a7 += a4 add a7 a7 a4
RISC-V Instructions
R-type — sll, srl, sra

• shift left logical

• shift right logical
• shift right arithmetical
RISC-V Instructions
R-type — What are “logical” and “arithmetical”

• Assume a 4-bit register: 0b1001

• Shift left: 0b0010
• Shift right: 0b0100
• Any other possible shifts?
RISC-V Instructions
Most Signi cant Bit

• 0b11001010 — 1
• 0b01100011 — 0

• Often have special usages (sign bit)

• Opposed to LSB (Least Signi cant Bit)
fi
fi
RISC-V Instructions
R-type — What are “logical” and “arithmetical”

• Assume a 4-bit register: 0b1001 # t1 = 0xFFFFFFFF

# t2 = 4
• Shift left: 0b0010
• Shift right: 0b0100 sll t3 t1 t2
srl t4 t1 t2
• “Arithmetical”: 0b1100
sra t5 t1 t2
RISC-V Instructions
R-type — slt, sltu

• Set less than

• Set less than (unsigned)

RISC-V Instructions
R-type — Set less than

int32_t a = 0x1234; # t1 = 0x1234

int32_t b = 0x0040; # t2 = 0x0040

c = (a < b) ? 1 : 0; slt t3 t1 t2
RISC-V Instructions
R-type — Set less than

int32_t a = 0xFFFFFFFF; # t1 = 0xFFFFFFFF

int32_t b = 0x02b66240; # t2 = 0x02b66240

c = (a < b) ? 1 : 0; slt t3 t1 t2
RISC-V Instructions
R-type — Set less than (unsigned)

uint32_t a = 0x1234; # t1 = 0x1234

uint32_t b = 0x0040; # t2 = 0x0040

c = (a < b) ? 1 : 0; sltu t3 t1 t2
RISC-V Instructions
R-type — Set less than (unsigned)

uint32_t a = 0xFFFFFFFF; # t1 = 0xFFFFFFFF

uint32_t b = 0x02b66240; # t2 = 0x02b66240

c = (a < b) ? 1 : 0; sltu t3 t1 t2
RISC-V Instructions
R-type — Conclusion
RISC-V Instructions
I-type

• addi, xori, ori, andi, slli, srli, srai — Basis

• slti, sltiu — Set less than

• lb, lw, lu, lbu, lhu — Load from main memory

• jalr, ecall, ebreak

RISC-V Instructions
I-type — addi, xori, ori, andi, slli, srli, srai

addi rd rs1 imm rd = rs1 addi imm

xori rd rs1 imm rd = rs1 xori imm
ori rd rs1 imm rd = rs1 ori imm
andi rd rs1 imm rd = rs1 andi imm
slli rd rs1 imm rd = rs1 slli imm
srli rd rs1 imm rd = rs1 srli imm
srai rd rs1 imm rd = rs1 srai imm
RISC-V Instructions
I-type — slti, sltiu

• Set less than imm

• Set less than imm (unsigned)

RISC-V Instructions
I-type — Set less than imm

int32_t a = 0x1234; # t1 = 0x1234

c = (a < 0x0040) ? 1 : 0; slti t3 t1 0x0040

RISC-V Instructions
I-type — Set less than imm

int32_t a = 0xFFFFFFFF; # t1 = 0xFFFFFFFF

c = (a < 0x6240) ? 1 : 0; slti t3 t1 0x6240

RISC-V Instructions
I-type — Set less than imm (unsigned)

uint32_t a = 0x1234; # t1 = 0x1234

c = (a < 0x0040) ? 1 : 0; sltiu t3 t1 0x0040

RISC-V Instructions
I-type — Set less than imm (unsigned)

uint32_t a = 0xFFFFFFFF; # t1 = 0xFFFFFFFF

c = (a < 0x6240) ? 1 : 0; sltiu t3 t1 0x6240

RISC-V Instructions
I-type — lb, lw, lu, lbu, lhu

lb rd imm(rs1)
lw rd imm(rs1)
lu rd imm(rs1)
lbu rd imm(rs1)
lhu rd imm(rs1)
RISC-V Instructions
I-type — lb, lw, lu, lbu, lhu

load byte rd imm(rs1)

load word rd imm(rs1)
load unsigned rd imm(rs1)
load byte unsigned rd imm(rs1)
load halfword unsigned rd imm(rs1)
RISC-V Instructions
I-type — lb, lw, lu, lbu, lhu

.data
number:
.word 0x01234567 0x89ABCDEF

.text
la t0 number
lw t1 0(t0)
lb t1 0(t0)
lb t1 3(t0)
lh t1 1(t0)
RISC-V Instructions
I-type — lb, lw, lu, lbu, lhu

.text
la t0 number 89 AB CD EF
lw t1 0(t0)
lb t1 0(t0)
lb t1 3(t0) 01 23 45 67
lh t1 1(t0)
RISC-V Instructions
I-type — lb, lw, lu, lbu, lhu

.text
la t0 number 89 AB CD EF
lw t1 0(t0)
lb t1 0(t0)
lb t1 3(t0) 01 23 45 67
lh t1 1(t0)

0x01234567
RISC-V Instructions
I-type — lb, lw, lu, lbu, lhu

.text
la t0 number 89 AB CD EF
lw t1 0(t0)
lb t1 0(t0)
lb t1 3(t0) 01 23 45 67
lh t1 1(t0)

0x00000067
RISC-V Instructions
I-type — lb, lw, lu, lbu, lhu

.text
la t0 number 89 AB CD EF
lw t1 0(t0)
lb t1 0(t0)
lb t1 3(t0) 01 23 45 67
lh t1 1(t0)

0x00000001
RISC-V Instructions
I-type — lb, lw, lu, lbu, lhu

.text
la t0 number 89 AB CD EF
lw t1 0(t0)
lb t1 0(t0)
lb t1 3(t0) 01 23 45 67
lh t1 1(t0)

0x00002345
RISC-V Instructions
I-type — lb, lw, lu, lbu, lhu (Strange cases)

.text
la t0 number
89 AB CD EF
lw t1 3(t0)
lhu t1 5(t0)
lh t1 5(t0)
lbu t1 7(t0)
01 23 45 67
lb t1 7(t0)
0xABCDEF01
RISC-V Instructions
I-type — lb, lw, lu, lbu, lhu (Strange cases)

.text
la t0 number
89 AB CD EF
lw t1 3(t0)
lhu t1 5(t0)
lh t1 5(t0)
lbu t1 7(t0)
01 23 45 67
lb t1 7(t0)
0x0000ABCD
RISC-V Instructions
I-type — lb, lw, lu, lbu, lhu (Strange cases)

.text
la t0 number
89 AB CD EF
lw t1 3(t0)
lhu t1 5(t0)
lh t1 5(t0)
lbu t1 7(t0)
01 23 45 67
lb t1 7(t0)
0xFFFFABCD
RISC-V Instructions
I-type — lb, lw, lu, lbu, lhu (Strange cases)

.text
la t0 number
89 AB CD EF
lw t1 3(t0)
lhu t1 5(t0)
lh t1 5(t0)
lbu t1 7(t0)
01 23 45 67
lb t1 7(t0)
0x00000089
RISC-V Instructions
I-type — lb, lw, lu, lbu, lhu (Strange cases)

.text
la t0 number
89 AB CD EF
lw t1 3(t0)
lhu t1 5(t0)
lh t1 5(t0)
lbu t1 7(t0)
01 23 45 67
lb t1 7(t0)
0xFFFFFF89
RISC-V Instructions
I-type — Conclusion
RISC-V Instructions
S-type

• sb, sh, sw — Write to main memory

RISC-V Instructions
S-type

sb rs2 imm(rs1)
sh rs2 imm(rs1)
sw rs2 imm(rs1)
RISC-V Instructions
S-type

store byte rs2 imm(rs1)

store halfword rs2 imm(rs1)
store word rs2 imm(rs1)
RISC-V Instructions
S-type

89 AB CD EF

01 23 45 67
RISC-V Instructions
S-type

.text
la t0 number 89 AB CD EF
li t1 0x91
sw t1 0(t0)
sw t1 3(t0) 00 00 00 91
sb t1 2(t0)
sh t1 6(t0)
RISC-V Instructions
S-type

.text
la t0 number 89 00 00 00
li t1 0x91
sw t1 0(t0)
sw t1 3(t0) 91 00 00 91
sb t1 2(t0)
sh t1 6(t0)
RISC-V Instructions
S-type

.text
la t0 number 89 00 00 00
li t1 0x91
sw t1 0(t0)
sw t1 3(t0) 91 91 00 91
sb t1 2(t0)
sh t1 6(t0)
RISC-V Instructions
S-type

.text
la t0 number 00 91 00 00
li t1 0x91
sw t1 0(t0)
sw t1 3(t0) 91 91 00 91
sb t1 2(t0)
sh t1 6(t0)
RISC-V Instructions
S-type
RISC-V Instructions
U-type

• lui — Load Upper Immediate

• auipc — Add Upper Immediate to PC

RISC-V Instructions
U-type

auipc t0 0x3
lui t0 0x3ab85

rd = PC + imm << 12

t0 = 0x3ab85000
t0 = PC + 0x3 << 12
RISC-V Instructions
U-type
RISC-V Instructions
B-type

• beq, bne, blt, bge, bltu, bgeu

• How label becomes immediates?

RISC-V Instructions
B-type — beq, bne, blt, bge, bltu, bgeu

beq rs1 rs2 imm if (rs1 beq rs2) goto label;

bne rs1 rs2 imm if (rs1 bne rs2) goto label;
blt rs1 rs2 imm if (rs1 blt rs2) goto label;
bge rs1 rs2 imm if (rs1 bge rs2) goto label;
bltu rs1 rs2 imm if (rs1 bltu rs2) goto label;
bgeu rs1 rs2 imm if (rs1 bgeu rs2) goto label;
RISC-V Instructions
B-type
How labels become immediates?
RISC-V Instructions
How labels become immediates?

• Calculate the o set

0 nop 0x0 addi x0 x0 0
1 blt x0 x0 label_1 0x4 blt x0 x0 8
2 nop 0x8 addi x0 x0 0
label_1: label_1:
3 nop 0xC addi x0 x0 0
ff
RISC-V Instructions
How labels become immediates?

0x0 addi x0 x0 0
0x4 blt x0 x0 8 0x0 0x00000013
0x8 addi x0 x0 0 0x4 0x00004463
label_1: 0x8 0x00000013
0xC addi x0 x0 0 0xC 0x00000013
RISC-V Instructions
How labels become immediates?

• Wait … What is the imm eld?

0x0 addi x0 x0 0
0x4 blt x0 x0 8 0x0 0x00000013
0x8 addi x0 x0 0 0x4 0x00004463
label_1: 0x8 0x00000013
0xC addi x0 x0 0 0xC 0x00000013

• Extract immediate eld -> 4

fi
fi
RISC-V Instructions
Jal, Jalr

• Jump And Link

• Jump And Link Register

RISC-V Instructions
Jump And Link

0 nop 0x0 addi x0 x0 0

1 jal ra label_1 0x4 jal x1 12
2 nop 0x8 addi x0 x0 0
3 nop 0xC addi x0 x0 0
label_1: label_1:
4 nop 0x10 addi x0 x0 0
RISC-V Instructions
Jump And Link

• The same thing about imm eld happened again

0x0 addi x0 x0 0
0x0 0x00000013
0x4 jal x1 12
0x4 0x00C000EF
0x8 addi x0 x0 0
0x8 0x00000013
0xC addi x0 x0 0
0xC 0x00000013
label_1:
0x10 0x00000013
0x10 addi x0 x0 0

• Extract immediate eld -> 6

fi
fi
RISC-V Instructions
Jump And Link Register

0 la t0 label_2
1 jalr ra t0 4 # load address
2 nop 0x8 jalr x1 x5 4
3 nop 0xC addi x0 x0 0
label_2: 0x10 addi x0 x0 0
4 nop label_2:
5 nop 0x14 addi x0 x0 0
RISC-V Instructions
Jump And Link Register

• This time we have the corresponding o set

# load address
0x8 jalr x1 x5 4 0x8 0x004280E7
0xC addi x0 x0 0 0xC 0x00000013
0x10 addi x0 x0 0 0x10 0x00000013
label_2: 0x14 0x00000013
0x14 addi x0 x0 0

• Extract immediate eld -> 4

fi
ff
Project 1.1
Get started early!
Recommended Readings

• Why JALR encodes the LSB?

• https://github.com/jameslzhu/riscv-card
CALL review
What are those?

• C: Compiler
• A: Assembler
• L: Linker
• L: Loader

• These parts have a demo, so come to the discussion if you need that.
Compiler — Before compiling
The C PreProcessor (cpp)

• Deal with directives — Starting with “#” in C

• “Pull” the declarations from #include
• “Expand/Replace” the macros #define

~ cpp main.c main.i

Compiler
GNU C compiler (gcc)

• Compile the source code to assembly

~ gcc -S main.i
Assembler

• Converts assembly level language code into machine language code.

~ as main.s -o main.o
~ hexdump -C main.o
~ readelf -a main.o
~ objdump -r main.o
Linker, Loader

• Combines the object les, generated by the assembler to generate an

executable.

• Load executable to main memory.

fi
Relocation table

• Information about addresses referenced in this object le that the

linker must adjust once it knows the nal memory allocation.

fi
fi
Symbol table

• Name and current location of variables or functions that can

potentially be referenced in other object les.

fi
What problem should linkers solve?

• Assembler doesn't know the addresses of external objects.

• Puts zeroes in the object le for each unknown address
• Assembler doesn't know where the things it's assembling will go in
memory

• Assume that things start at address zero, leave for linker re-arrange.

Cite: https://web.stanford.edu/~ouster/cgi-bin/cs140-winter12/lecture.php?topic=linkers
fi
Question
When does the instruction is nally determined?

1. add x6, x7, x8 A. After compile

2. jal x1, fprintf B. After assemble

C. After link

D. After load
fi