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5-Level Paging and 5-Level EPT
White Paper

Revision 1.0
December 2016

Document Number: 335252-001

Notice: This document contains information on products in the design phase of development. The information here is subject to
change without notice. Do not finalize a design with this information.
Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software, or service
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*Other names and brands may be claimed as the property of others.
Copyright © 2016, Intel Corporation. All Rights Reserved.

2 Document Number: 335252-001, Revision: 1.0

Contents

1 Introduction .............................................................................................................. 3
1.1 Existing Paging in IA-32e Mode ............................................................................. 3
1.2 Linear-Address Width and VMX Transitions ............................................................. 5
1.3 Existing Extended Page Tables (EPT)...................................................................... 6
2 Expanding Linear Addresses: 5-Level Paging ............................................................. 7
2.1 5-Level Paging: Introduction ................................................................................. 7
2.2 Enumeration and Enabling .................................................................................... 7
2.2.1 Enumeration by CPUID.............................................................................. 7
2.2.2 Enabling by Software ................................................................................ 8
2.3 Linear-Address Generation and Canonicality............................................................ 8
2.4 5-Level Paging: Linear-Address Translation............................................................. 9
2.5 Linear-Address Registers and Canonicality ............................................................ 10
2.5.1 Canonicality Checking on RIP Loads .......................................................... 11
2.5.2 Canonicality Checking on Other Loads ....................................................... 12
2.6 Interactions with TLB-Invalidation Instructions ...................................................... 13
2.7 Interactions with Intel® MPX .............................................................................. 14
2.8 Interactions with Intel® SGX .............................................................................. 15
3 Linear-Address Expansion and VMX Transitions....................................................... 17
3.1 Linear-Address Expansion and VM Entries ............................................................. 17
3.2 Linear-Address Expansion and VM Exits................................................................ 17
4 5-Level EPT ............................................................................................................. 19
4.1 4-Level EPT: Guest-Physical-Address Limit............................................................ 19
4.2 5-Level EPT: Enumeration and Enabling ............................................................... 19
4.2.1 Enumeration.......................................................................................... 19
4.2.2 Enabling by Software .............................................................................. 20
4.3 5-Level EPT: Guest-Physical-Address Translation ................................................... 20
4.4 5-Level EPT and EPTP Switching .......................................................................... 21
5 Intel® Virtualization Technology for Directed I/O ................................................... 23

Figures
1-1 Linear-Address Translation Using IA-32e Paging ...................................................... 4
2-1 Linear-Address Translation Using 5-Level Paging ................................................... 11

Tables
2-1 Format of a PML5 Entry (PML5E) that References a PML4 Table ................................. 9
4-1 Format of an EPT PML5 Entry (EPT PML5E) ........................................................... 20

Document Number: 335252-001, Revision: 1.0 3

Revision History

Document Revision
Description Date
Number Number

335252-001 1.0 • Initial Release December 2016

4 Document Number: 335252-001, Revision: 1.0

1 Introduction

This document describes planned extensions to the Intel 64 architecture to expand the
size of addresses that can be translated through a processor’s memory-translation
hardware.

Modern operating systems use address-translation support called paging. Paging

translates linear addresses (also known as virtual addresses), which are used by
software, to physical addresses, which are used to access memory (or memory-
mapped I/O). Section 1.1 describes the 64-bit paging hardware on Intel 64 processors.
Existing processors limit linear addresses to 48 bits. Chapter 2 describes paging
extensions that would relax that limit to 57 linear-address bits.

Virtual-machine monitors (VMMs) use the virtual-machine extensions (VMX) to

support guest software operating in a virtual machine. VMX transitions are control-
flow transfers between the VMM and guest software. VMX transitions involve the
loading and storing of various processor registers. Some of these registers are defined
to contain linear addresses. Because of this, the operation of VMX transitions depends
in part on the linear-address width supported by the processor. Section 1.2 describes
the existing treatment of linear-address registers by VMX transitions, while Chapter 3
describes the changes required to support larger linear addresses.

VMMs may also use additional address-translation support called extended page
tables (EPT). When EPT is used, paging produces guest-physical addresses, which
EPT translates to physical addresses. Section 1.3 describes the EPT hardware on
existing Intel 64 processors, which limit guest-physical addresses to 48 bits. Chapter 4
describes EPT extensions to support 57 guest-physical-address bits.

1.1 Existing Paging in IA-32e Mode

On processors supporting Intel 64 architecture, software typically references memory
using linear addresses. Most modern operating systems configure processors to use
paging, which translates linear addresses to physical addresses. The processor uses
the resulting physical addresses to access memory.

IA-32e mode is a mode of processor execution that extends the older 32-bit
operation, known as legacy mode. Software can enter IA-32e mode with the following
algorithm.
1. Use the MOV CR instruction to set CR4.PAE[bit 5]. (Physical-address extension
must be enabled to enter IA-32e mode.)
2. Use the WRMSR instruction to set bit 8 (LME) of the IA32_EFER MSR (index
C0000080H).
3. Use the MOV CR instruction to load CR3 with the address of a PML4 table (see
below).
4. Use the MOV CR instruction to set CR0.PG[bit 31].

A logical processor is in IA-32e mode whenever CR0.PG = 1 and IA32_EFER.LME = 1.

This fact is reported in IA32_EFER.LMA[bit 10]. Software cannot set this bit directly; it
is always the logical-AND of CR0.PG and IA32_EFER.LME.

Document Number: 335252-001, Revision: 1.0 3

 In IA-32e mode, linear addresses are 64 bits in size.1 However, the corresponding
paging mode (currently called IA-32e paging) does not use all 64 linear-address bits.

IA-32e paging does not use all 64 linear-address bits because processors limit the size
of linear addresses. This limit is enumerated by the CPUID instruction. Specifically,
CPUID.80000008H:EAX[bits 15:8] enumerates the number of linear-address bits (the
maximum linear-address width) supported by the processor. Existing processors
enumerate this value as 48.

Note: Processors also limit the size of physical addresses and enumerate the limit using
CPUID. CPUID.80000008H:EAX[bits 7:0] enumerates the number of physical-address
bits supported by the processor, the maximum physical-address width. Existing
processors have enumerated values up to 46. Software can use more than 32 physical-
address bits only if physical-address extension has been enabled by setting
CR4.PAE, bit 5 of control register CR4.

The enumerated limitation on the linear-address width implies that paging translates
only the low 48 bits of each 64-bit linear address. After a linear address is generated
but before it is translated, the processor confirms that the address uses only the 48 bits
that the processor supports.

The limitation to 48 linear-address bits results from the nature of IA-32e paging, which
is illustrated in Figure 1-1.

Linear Address
47 39 38 30 29 21 20 12 11 0
PML4 Directory Ptr Directory Table Offset

9 9
9 12 4-KByte Page
Physical Addr

PTE
Page-Directory- PDE
40
Pointer Table 40 Page Table
Page-Directory
PDPTE 40

40
PML4E

40
CR3

Figure 1-1. Linear-Address Translation Using IA-32e Paging

1. IA-32e mode comprises two sub-modes: compatibility mode and 64-bit mode. In compatibility
mode, software uses 32-bit addresses, which the processor zero-extends to 64-bit linear
addresses. In 64-bit mode, software uses 64-bit addresses directly.

4 Document Number: 335252-001, Revision: 1.0

 The processor performs IA-32e paging by traversing a 4-level hierarchy of paging
structures whose root structure resides at the physical address in control register
CR3. Each paging structure is 4-KBytes in size and comprises 512 8-byte entries. The
processor uses the upper 36 bits of a linear address (bits 47:12), 9 bits at a time, to
select paging-structure entries from the hierarchy.

Note: Figure 1-1 illustrates the translation of a linear address to a 4-KByte page. The paging
process can be configured so that the translation of some linear addresses stops one or
two levels earlier, translating instead to 2-MByte pages or 1-GByte pages.

In general, bits 51:12 of each paging-structure entry contain a 4-KByte aligned

physical address. For each entry except the last, this address is that of the next paging
structure; in the last entry, it is the physical address of a 4-KByte page frame. The
final physical address is obtained by combining this page-frame address with the page
offset, bits 11:0 of the original linear address.

Because only bits 47:0 of a linear address are used in address-translation, the
processor reserves bits 63:48 for future expansion using a concept known as
canonicality. A linear address is canonical if bits 63:47 of the address are identical.
(Put differently, a linear address is canonical only if bits 63:48 are a sign-extension of
bit 47, which is the uppermost bit used in linear-address translation.)

When a 64-bit linear address is generated to access memory, the processor first
confirms that the address is canonical. If the address is not canonical, the memory
access causes a fault, and the processor makes no attempt to translate the address.1

Intel 64 architecture includes numerous registers that are defined to hold linear
addresses. These registers may be loaded using a variety of instructions. In most
cases, these instructions cause a general-protection exception (#GP) if an attempt is
made to load one of these registers with a value that is not canonical.

Physical-address bits in a paging-structure entry beyond the enumerated physical-

address width are reserved. A page-fault exception (#PF) results if an attempt is made
to access a linear address whose translation encounters a paging-structure entry that
sets any of those bits.

1.2 Linear-Address Width and VMX Transitions

VM entries and VM exits manipulate numerous processor registers that contain linear
addresses. The transitions respect the processor’s linear-address width in a manner
based on canonicality.

Certain fields in the VMCS correspond to registers that contain linear addresses.
VM entries confirm that most of those fields contain values that are canonical. Some
registers, such as RIP and the LDTR base address, receive special treatment.

VM exits save into the VMCS the state of certain registers, some of which contain linear
addresses. Because the processor generally ensures that the values in these registers
are canonical (see Section 1.1), the values that VM exits save for these registers will
generally be canonical.

1. In general, an attempt to access memory using a linear address that is not canonical causes a
general-protection exception (#GP). A stack-fault exception — #SS — occurs instead if the
memory access was made using the SS segment.

Document Number: 335252-001, Revision: 1.0 5

 VM exits also load from the VMCS certain registers, some of which contain linear
addresses. Each VM exit ensures that the value of each of these registers is canonical.
Specifically, bits 47:0 of the register are loaded from the field in the host-state area;
the value of bit 47 is then sign-extended into bits 63:48 of the register.

1.3 Existing Extended Page Tables (EPT)

Most Intel 64 processors supporting VMX also support an additional layer of address
translation called extended page tables (EPT).

VM entry can be configured to activate EPT for guest software. When EPT is active, the
addresses used and produced by paging (Section 1.1) are not used as physical
addresses to reference in memory. Instead, the processor interprets them as guest-
physical addresses, and translates them to physical addresses in a manner
determined by the VMM. (This translation from guest-physical to physical applies not
only to the output of paging but also to the addresses that the processor uses to
reference the guest paging structures.)

If the EPT translation process cannot translate a guest-physical address, it causes an

EPT violation. (EPT violations may also occur when an access to a guest-physical
address violates the permissions established by EPT for that guest-physical address.)
An EPT violation is a VMX-specific exception, usually causing a VM exit.

As noted in Section 1.1, existing processors limit physical addresses to 46 bits. That
limit applies also to guest-physical addresses. As a result, guest-physical addresses
that set bits beyond this limit are not translated by EPT. (For example, a page fault
results if linear-address translation encounters a paging-structure entry with such an
address.) Because of this, existing EPT has been limited to translating only 48 guest-
physical-address bits.

The existing EPT translation process is analogous to the paging process that was
illustrated earlier in Figure 1-1. Like 4-level paging, the processor implements EPT by
traversing a 4-level hierarchy of 4-KByte EPT paging structures. The last EPT paging-
structure entry contains the upper bits of the final physical address, while the lowest
bits come from the original guest-physical address.

6 Document Number: 335252-001, Revision: 1.0

2 Expanding Linear Addresses:
5-Level Paging

2.1 5-Level Paging: Introduction

5-level paging is a new paging mode that will be available in IA-32e mode. As its
name suggests, it will translate linear addresses by traversing a 5-level hierarchy of
paging structures. Because the process is otherwise unmodified, 5-level paging extends
the processor’s linear-address width to 57 bits. (The additional 9 bits are used to select
an entry from the fifth level of the hierarchy.) For clarity, the paging mode formerly
called IA-32e paging will now be called 4-level paging.

The remainder of this chapter specifies the architectural changes that define and are
entailed by 5-level paging. Section 2.2 specifies how the CPU enumerates the new
feature and how it is enabled by software. Section 2.3 describes changes to the process
of linear-address generation, as well as a revision to the concept of canonicality.
Section 2.4 details how 5-level paging translates linear addresses. Section 2.5 clarifies
how the processor treats loads of registers containing linear addresses, while Section
2.6 to Section 2.8 consider interactions with various other features. (Interactions with
the virtual-machine extensions are specified in Chapter 3.)

2.2 Enumeration and Enabling

This section describes how processors enumerate to software support for 5-level paging
and related features and also how software enables the processor to use that support.

2.2.1 Enumeration by CPUID

Processors supporting the Intel 64 architecture typically use the CPUID instruction to
enumerate to software specific processor functionality. Those processors that support
5-level paging enumerate that fact through a new feature flag as well as through
changes in how related features are reported:
• CPUID.(EAX=07H, ECX=0):ECX[bit 16] is a new feature flag that will enumerate
basic support for 5-level paging. All older processors clear this bit. A processor will
set this bit if and only if it supports 5-level paging.
• As noted in Section 1.1, CPUID.80000008H:EAX[bits 15:8] enumerates the
maximum linear-address width supported by the processor. All older processors
that support Intel 64 architecture enumerated this value as 48. Processors that
support 5-level paging will instead enumerate this value as 57.
• As noted in Section 1.1, CPUID.80000008H:EAX[bits 7:0] enumerates the
maximum physical-address width supported by the processor. Processors that
support Intel 64 architecture have enumerated at most 46 for this value.
Processors that support 5-level paging are expected to enumerate higher values,
up to 52.
• CPUID.(EAX=07H,ECX=0H):ECX.MAWAU[bits 21:17] is an existing field that
enumerates the user MPX address-width adjust (MAWAU). This value specifies the
number of linear-address bits above 48 on which the BNDLDX and BNDSTX
instructions operate in 64-bit mode when CPL = 3.

Document Number: 335252-001, Revision: 1.0 7

 Older processors that support Intel® MPX enumerated 0 for this value. Processors
that support 5-level paging may enumerate either 0 or 9, depending on
configuration by system software. See Section 2.7 for more details on how BNDLDX
and BNDSTX use MAWAU and how system software determines its value.
• CPUID.(EAX=12H,ECX=0H):EDX[bits 15:8] is an existing field that enumerates
information that specifies the maximum supported size of a 64-bit enclave. If the
value enumerated is n, the maximum size is 2n. Older processors that support
Intel® SGX enumerated at most 47 for this value. Processors that support 5-level
paging are expected to enumerate this value as 56.

2.2.2 Enabling by Software

Section 1.1 identified an algorithm by which software can enter IA-32e mode. On
processors that do not support 5-level paging, this algorithm enables 4-level paging.
On processors that support 5-level paging, it can be adapted to enable 5-level paging
instead.

Processors that support 5-level paging allow software to set a new enabling bit,
CR4.LA57[bit 12].1 A logical processor in IA-32e mode (IA32_EFER.LMA = 1) uses 5-
level paging if CR4.LA57 = 1. Outside of IA-32e mode (IA32_EFER.LMA = 0), the value
of CR4.LA57 does not affect paging operation.

The following items detail how a logical processor determines the current paging mode.
• If CR0.PG = 0, paging is disabled.
• If IA32_EFER.LMA = 0, one of the legacy 32-bit paging modes is used (depending
on the value of legacy paging-mode bits in CR4).2
• If IA32_EFER.LMA = 1 and CR4.LA57 = 0, 4-level paging is used.
• If IA32_EFER.LMA = 1 and CR4.LA57 = 1, 5-level paging is used.

Software can thus use the following algorithm to enter IA-32e mode with 5-level
paging.
1. Use the MOV CR instruction to set CR4.PAE and CR4.LA57.
2. Use the WRMSR instruction to set IA32_EFER.LME.
3. Use the MOV CR instruction to load CR3 with the address of a PML5 table (see
Section 2.4).
4. Use the MOV CR instruction to set CR0.PG.

The processor allows software to modify CR4.LA57 only outside of IA-32e mode. In
IA-32e mode, an attempt to modify CR4.LA57 using the MOV CR instruction causes a
general-protection exception (#GP).

2.3 Linear-Address Generation and Canonicality

As noted in Section 1.1, processors with a linear-address width of 48 bits reserve
linear-address bits 63:48 for future expansion. Linear addresses that use only bits 47:0
(because bits 63:48 are a sign-extension of bit 47) are called canonical.

1. Software can set CR4.LA57 only if CPUID.(EAX=07H, ECX=0):ECX[bit 16] is enumerated as 1.

2. Recall that IA32_EFER.LMA is the logical-AND of CR0.PG and IA32_EFER.LME.

8 Document Number: 335252-001, Revision: 1.0

 When a 64-bit linear address is generated to access memory, the processor first
confirms that the address is canonical. If the address is not canonical, the memory
access causes a fault, and the address is not translated.

Processors that support 5-level paging can translate 57-bit linear addresses when 5-
level paging is enabled. But if software has enabled only 4-level paging, such a
processor can translate only 48-bit linear addresses. This fact motivates the definition
of two levels of canonicality.

A linear address is 48-bit canonical if bits 63:47 of the address are identical.
Similarly, an address is 57-bit canonical if bits 63:56 of the address are identical. Any
linear address is that 48-bit canonical is also 57-bit canonical.

When a 64-bit linear address is generated to access memory, a processor that supports
5-level paging checks for canonicality based on the current paging mode: if 4-level
paging is enabled, the address must be 48-bit canonical; if 5-level paging is enabled,
the address need only be 57-bit canonical. If the appropriate canonicality is not
observed, the memory access causes a fault.

2.4 5-Level Paging: Linear-Address Translation

As noted in Section 2.2.2, a logical processor uses 5-level paging if IA32_EFER.LMA = 1
and CR4.LA57 = 1.

Like 4-level paging, 5-level paging translates linear addresses using a hierarchy of in-
memory paging structures. Because 5-level paging increases the linear-address width
to 57 bits (from the 48 bits supported by 4-level paging), 5-level paging allows up to
128 PBytes of linear-address space to be accessed at any given time.

Also like 4-level paging, 5-level paging uses CR3 to locate the first paging-structure in
the hierarchy. (CR3 has the same mode-specific format with 5-level paging as it does
with 4-level paging.) The following items describe in more detail the changes that 5-
level paging makes to the translation process.
• Translation begins by identifying a 4-KByte naturally aligned PML5 table. It is
located at the physical address specified in bits 51:12 of CR3. A PML5 table
comprises 512 64-bit entries (PML5Es). A PML5E is selected using the physical
address defined as follows.
— Bits 51:12 are from CR3.
— Bits 11:3 are bits 56:48 of the linear address.
— Bits 2:0 are all 0.
Because a PML5E is identified using bits 56:48 of the linear address, it controls
access to a 256-TByte region of the linear-address space. The format of a PML5E is
given in Table 2-1.

Table 2-1. Format of a PML5 Entry (PML5E) that References a PML4 Table
Bit Position(s) Contents

0 (P) Present; must be 1 to reference a PML4 table.

1 (R/W) Read/write; if 0, writes may not be allowed to the 256-TByte region controlled by this entry.

2 (U/S) User/supervisor; if 0, user-mode accesses are not allowed to the 256-TByte region
controlled by this entry.

3 (PWT) Page-level write-through; indirectly determines the memory type used to access the PML4
table referenced by this entry.

Document Number: 335252-001, Revision: 1.0 9

Table 2-1. Format of a PML5 Entry (PML5E) that References a PML4 Table (Continued)
Bit Position(s) Contents

4 (PCD) Page-level cache disable; indirectly determines the memory type used to access the PML4
table referenced by this entry.

5 (A) Accessed; indicates whether this entry has been used for linear-address translation.

6 Ignored.

7 (PS) Reserved (must be 0).

11:8 Ignored.

M–1:12 Physical address of 4-KByte aligned PML4 table referenced by this entry.

51:M Reserved (must be 0).

62:52 Ignored.

63 If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the
256-TByte region controlled by this entry); otherwise, reserved (must be 0).

• The next step of the translation process identifies a 4-KByte naturally aligned PML4
table. It is located at the physical address specified in bits 51:12 of the PML5E (see
Table 2-1). A PML4 table comprises 512 64-bit entries (PML4Es). A PML4E is
selected using the physical address defined as follows.
— Bits 51:12 are from the PML5E.
— Bits 11:3 are bits 47:39 of the linear address.
— Bits 2:0 are all 0.
As is normally the case when accessing a paging-structure entry, the memory type
used to access the PML4E is based in part on the PCD and PWT bits in the PML5E.
Because a PML4E is identified using bits 56:39 of the linear address, it controls
access to a 512-GByte region of the linear-address space.

Once the PML4E is identified, bits 38:0 of the linear address determine the remainder
of the translation process exactly as is done for 4-level paging. As suggested in
Table 2-1, the values of bit 1, bit 2, and bit 63 of the PML5E are used normally (in
combination with the corresponding bits in other paging-structure entries) to determine
access rights. The accessed flag (bit 5) in the PML5E is updated as is done for other
paging-structure entries.

The operation of 5-level paging is illustrated in Figure 2-1.

2.5 Linear-Address Registers and Canonicality

Intel 64 architecture includes numerous registers that are defined to hold linear
addresses. These registers may be loaded using a variety of instructions. As noted in
Section 1.1, each of these instructions typically causes a general-protection exception
(#GP) if an attempt is made to load a linear-address register with a value that is not
canonical.

As noted in Section 2.3, processors that support 5-level paging use two definitions of
canonicality: 48-bit canonicality and 57-bit canonicality. This section describes how
such a processor checks the canonicality of the values being loaded into the linear-
address registers. One approach is used for operations that load RIP (the instruction
pointer; see Section 2.5.1) and another is used for those that load other registers (see
Section 2.5.2).

10 Document Number: 335252-001, Revision: 1.0

 Linear Address
56 47 39 38 30 29 21 20 12 11 0
PML5 PML4 Directory Ptr Directory Table Offset

9 9
9 9
12 4-KByte Page
Physical Addr

PDE
PDPTE 40
40 Page Directory
Page-Directory 40

PML4E 40 Pointer Table

9
PTE
40
Page Table
PML5E

40
CR3

Figure 2-1. Linear-Address Translation Using 5-Level Paging

2.5.1 Canonicality Checking on RIP Loads

The RIP register contains the offset of the current instruction pointer within the CS
segment. Because the processor treats the CS base address as zero in 64-bit mode, the
value of the RIP register in that mode is the linear address of the instruction pointer.

Operations that load RIP (including both instructions such as JMP as well as control
transfers through the IDT) check first whether the value to be loaded is canonical
relative to the current paging mode. If the processor determines that the address is not
canonical, the RIP load is not performed and a general-protection exception (#GP)
occurs.

Note: An instruction that would load RIP with a non-canonical address faults, meaning that
the return instruction pointer of the fault handler is the address of the faulting
instruction and not the non-canonical address whose load was attempted.

The canonicality checking performed by these operations uses 48-bit canonicality when
4-level paging is active. When 5-level paging is active, the checking is relaxed to
require only 57-bit canonicality.

The SYSCALL and SYSENTER instructions load RIP from the IA32_LSTAR and
IA32_SYSENTER_EIP MSRs, respectively. On processors that support only 4-level
paging, these instructions do not check that the values being loaded are canonical
because the WRMSR instruction ensures that each of these MSRs contains a value that
is 48-bit canonical. On processors that support 5-level paging, the checking by WRMSR
is relaxed to 57-bit canonicality (see Section 2.5.2). On such processors, an execution

Document Number: 335252-001, Revision: 1.0 11

 of SYSCALL or SYSENTER with 4-level paging checks that the value being loaded into
RIP is 48-bit canonical.1

The normal advancing of the instruction pointer to the next instruction boundary may
result in the RIP register holding a non-canonical address. The fetch of the next
instruction from that non-canonical address will result in a general-protection exception
as indicated in Section 2.3. In this case, the return instruction pointer of the fault
handler will be that non-canonical address.

2.5.2 Canonicality Checking on Other Loads

In addition to RIP, the CPU maintains numerous other registers that hold linear
addresses:
• GDTR and IDTR (in their base-address portions).
• LDTR, TR, FS, and GS (in the base-address portions of their hidden descriptor
caches).
• The debug-address registers (DR0 through DR3), which hold the linear addresses
of breakpoints.
• The following MSRs: IA32_BNDCFGS, IA32_DS_AREA, IA32_KERNEL_GS_BASE,
IA32_LSTAR, IA32_RTIT_ADDR0_A, IA32_RTIT_ADDR0_B, IA32_RTIT_ADDR1_A,
IA32_RTIT_ADDR1_B, IA32_RTIT_ADDR2_A, IA32_RTIT_ADDR2_B,
IA32_RTIT_ADDR3_A, IA32_RTIT_ADDR3_B, IA32_SYSENTER_EIP, and
IA32_SYSENTER_ESP.
• The x87 FPU instruction pointer (FIP).
• The user-mode configuration register BNDCFGU, used by Intel® MPX.

With a few exceptions, the processor ensures that the addresses in these registers are
always canonical in the following ways.
• Some instructions fault on attempts to load a linear-address register with a non-
canonical address:
— An execution of the LGDT or LIDT instruction causes a general-protection
exception (#GP) if the base address specified in the instruction’s memory
operand is not canonical.
— An execution of the LLDT or LTR instruction causes a #GP if the base address to
be loaded from the GDT is not canonical.
— An execution of WRMSR, WRFSBASE, or WRGSBASE causes a #GP if it would
load the base address of either FS or GS with a non-canonical address.
— An execution of WRMSR causes a #GP if it would load any of the following MSRs
with a non-canonical address: IA32_BNDCFGS, IA32_DS_AREA,
IA32_FS_BASE, IA32_GS_BASE, IA32_KERNEL_GS_BASE, IA32_LSTAR,
IA32_RTIT_ADDR0_A, IA32_RTIT_ADDR0_B, IA32_RTIT_ADDR1_A,
IA32_RTIT_ADDR1_B, IA32_RTIT_ADDR2_A, IA32_RTIT_ADDR2_B,
IA32_RTIT_ADDR3_A, IA32_RTIT_ADDR3_B, IA32_SYSENTER_EIP, or
IA32_SYSENTER_ESP.2

1. The SYSRET and SYSEXIT instructions, which complement SYSCALL and SYSENTER, load RIP
from RCX and RDX, respectively. Even before 5-level paging, these instructions checked the
canonicality of the value to be loaded into RIP. As with other instructions that load RIP, this
checking will be based on the current paging mode.
2. Such canonicality checking may apply also when the WRMSR instruction is used to load some
non-architectural MSRs (not listed here) that hold a linear address.

12 Document Number: 335252-001, Revision: 1.0

 — An execution of XRSTORS causes a #GP if it would load any of the following
MSRs with a non-canonical address: IA32_RTIT_ADDR0_A,
IA32_RTIT_ADDR0_B, IA32_RTIT_ADDR1_A, IA32_RTIT_ADDR1_B,
IA32_RTIT_ADDR2_A, IA32_RTIT_ADDR2_B, IA32_RTIT_ADDR3_A, and
IA32_RTIT_ADDR3_B.
This enforcement always uses the enumerated maximum linear-address width and
is independent of the current paging mode. Thus, a processor that supports 5-level
paging will allow the instructions mentioned above to load these registers with
addresses that are 57-bit canonical but not 48-bit canonical — even if 4-level
paging is active. (As a result, instructions that store these values — SGDT, SIDT,
SLDT, STR, RDFSBASE, RDGSBASE, RDMSR, XSAVE, XSAVEC, XSAVEOPT, and
XSAVES — may save addresses that are 57-bit canonical but not 48-bit canonical,
even if 4-level paging is active.)
• The FXRSTOR, XRSTOR, and XRSTORS instructions ignore attempts to load some of
these registers with non-canonical addresses:
— Loads of FIP ignore any bits in the memory image beyond the enumerated
maximum linear-address width. The processor sign-extends to most significant
bit (e.g., bit 56 on processors that support 5-level paging) to ensure that FIP is
always canonical.
— Loads of BNDCFGU (by XRSTOR or XRSTORS) ignore any bits in the memory
image beyond the enumerated maximum linear-address width. The processor
sign-extends to most significant bit (e.g., bit 56 on processors that support 5-
level paging) to ensure that BNDCFGU is always canonical.
• Every non-control x87 instruction loads FIP. The value loaded is always canonical
relative to the current paging mode: 48-bit canonical if 4-level paging is active, and
57-bit canonical if 5-level paging is active.

DR0 through DR3 can be loaded with the MOV to DR instruction. The instruction allows
those registers to be loaded with non-canonical addresses. The MOV from DR
instruction will return the value last loaded with the MOV to DR instruction, even if the
address is not canonical. Breakpoint address matching is supported only for canonical
linear addresses.

2.6 Interactions with TLB-Invalidation Instructions

Intel 64 architecture includes three instructions that may invalidate TLB entries for the
linear address of an instruction operand: INVLPG, INVPCID, and INVVPID. The following
items describe how they are affected by linear-address width.
• The INVLPG instruction takes a memory operand. It invalidates any TLB entries
that the logical processor is caching for the linear address of that operand for the
current linear address space. The instruction does not fault if that address is not
canonical relative to the current paging mode (e.g., is not 48-bit canonical when 4-
level paging is active). However, no invalidation is performed because the processor
does not cache TLB entries for addresses that are not canonical relative to the
current paging mode.
• The INVPCID instruction takes a register operand (INVPCID type) and a memory
operand (INVPCID descriptor). If the INVPCID type is 0, the instruction invalidates
any TLB entries that the logical processor is caching for the linear address and PCID
specified in the INVPCID descriptor. If the linear address is not canonical relative
the linear-address width supported by the processor, the instruction causes a
general-protection exception (#GP). If the processor supports 5-level paging, the
instruction will not cause such a #GP for an address that is 57-bit canonical,
regardless of paging mode, even if 4-level paging is active and the address is not
48-bit canonical.

Document Number: 335252-001, Revision: 1.0 13

 • The INVVPID instruction takes a register operand (INVVPID type) and a memory
operand (INVVPID descriptor). If the INVPCID type is 0, the instruction invalidates
any TLB entries that the logical processor is caching for the linear address and VPID
specified in the INVVPID descriptor. If the linear address is not canonical relative
the linear-address width supported by the processor, the instruction fails.1 If the
processor supports 5-level paging, the instruction will not fail for an address that is
57-bit canonical, regardless of paging mode, even if 4-level paging is active and the
address is not 48-bit canonical.

2.7 Interactions with Intel® MPX

The Intel® Memory Protection Extensions (Intel® MPX) define a set of 4 bound
registers, each of which software can associate with a specific pointer in memory.
Intel MPX includes two instructions — BNDLDX and BNDSTX — that allow software to
load from or store into memory the bounds associated with a particular pointer in
memory.

The BNDLDX and BNDSTX instructions each take a bound register and a memory
operand (the associated pointer). Each of these parses the linear address of the
memory operand to traverse a hierarchical data structure in memory. In 64-bit mode,
these instructions do not necessarily use all the bits in the supplied 64-bit addresses.
The number of bits used is 48 plus a value called the MPX address-width adjust
(MAWA).

The value of MAWA depends on CPL; the current paging mode (4-level paging or 5-level
paging); and, if 5-level paging is active, the value of a new MSR. Processors that
support both Intel MPX and 5-level paging support the IA32_MPX_LAX MSR (MSR index
1000H). Only bit 0 of the MSR is defined.

If CPL < 3, the supervisor MAWA (MAWAS) is used. The value of MAWAS is determined
by the setting of CR4.LA57. If CR4.LA57 = 0 (4-level paging is active; recall that MAWA
is relevant only in 64-bit mode), the value of MAWAS is 0. If CR4.LA57 = 1 (5-level
paging is active), the value of MAWAS is 9. The value of MAWAS is not enumerated by
the CPUID instruction.

If CPL = 3, the user MAWA (MAWAU) is used. The value of MAWAU is determined as
follows. If CR4.LA57 = 0 or IA32_MPX_LAX[bit 0] = 0, the value of MAWAU is 0. If
CR4.LA57 = 1 and IA32_MPX_LAX[bit 0] = 1, the value of MAWAU is 9. The current
value of MAWAU is enumerated in
CPUID.(EAX=07H,ECX=0H):ECX.MAWAU[bits 21:17].

The following items specify how an execution of the BNDLDX and BNDSTX instructions
in 64-bit mode parses a linear address to traverse a hierarchical data structure.
• A bound directory is located at the 4-KByte aligned linear address specified in
bits 63:12 of BNDCFGx.2 A BDE is selected using the LAp (linear address of pointer
to a buffer) to construct a 64-bit offset as follows:
— bits 63:31+MAWA are 0;
— bits 30+MAWA:3 are LAp[bits 47+MAWA:20]; and
— bits 2:0 are 0.

1. INVVPID is a VMX instruction. In response to certain conditions, execution of a VMX may fail,
meaning that it does not complete its normal operation. When a VMX instruction fails, control
passes to the next instruction (rather than to a fault handler) and a flag is set to report the
failure.
2. If CPL < 3, BNDCFGS is used; if CPL = 3, BNDCFGU is used.

14 Document Number: 335252-001, Revision: 1.0

 The address of the BDE is the sum of the bound-directory base address (from
BNDCFGx) plus this 64-bit offset.
If either BNDLDX or BNDSTX is executed inside an enclave, the instruction operates
as if MAWAU = 0 (regardless of the values of CR4.LA57 and IA32_MPX_LAX[bit 0]).
• The processor uses bits 63:3 of the BDE as the 8-byte aligned address of a bound
table (BT). A BTE is selected using the LAp (linear address of pointer to a buffer) to
construct a 64-bit offset as follows:
— bits 63:22 are 0;
— bits 21:5 are LAp[bits 19:3]; and
— bits 4:0 are 0.
The address of the BTE is the sum of the bound-table base address (from the BDE)
plus this 64-bit offset.

A bound directory comprises 228+MAWA 64-bit entries (BDEs);1 thus, the size of a
bound directory in 64-bit mode is 21+MAWA GBytes. A bound table comprises 217 32-
byte entries (BTEs); thus, the size of a bound table in 64-bit mode is 4 MBytes
(independent of MAWA).

2.8 Interactions with Intel® SGX

Intel® Software Guard Extensions (Intel® SGX) define new processor functionality that
is implemented as SGX leaf functions within the ENCLS (supervisor) and ENCLU (user)
instructions.

The SGX leaf functions include memory accesses using linear addresses normally.
When executed in 64-bit mode, the linear address are 64 bits in width and are subject
to the normal treatment of accesses to memory with 64-bit linear addresses (see
Section 2.3). In addition, some of the leaf functions apply specific architectural checks
related to linear-address width. The following items detail these checks and how they
are defined for processors that support 5-level paging.
• The ECREATE leaf function of ENCLS creates a new enclave by creating a new SGX
enclave control structure (SECS). For a 64-bit enclave, the processor checks
whether the enclave base linear address (specified in the SECS) is canonical,
generating a general-protection exception (#GP) if it is not. On processors that
support 5-level paging, this check is for 57-bit canonicality, regardless of the
current paging mode.
In addition to checking the canonicality of the enclave base linear address,
ECREATE confirms that the enclave size (specified in the SECS) is not greater than
the maximum size supported by the processor (if the enclave size is too large,
ECREATE generates a #GP). As noted in Section 2.2.1, older processors supported
64-bit enclaves with sizes up to 247 bytes; processors that support 5-level paging
are expected to support enclaves with sizes up to 256 bytes.
If bits 4:3 of the enclave’s XSAVE feature request mask (XFRM) are set (indicating
that Intel MPX will be enabled during execution of the enclave), ECREATE generates
a #GP if the enclave’s size is greater than 248 bytes, even if the processor
enumerates support for larger enclaves.
• The EENTER and ERESUME leaf functions of ENCLU transfer control flow to an entry
point within a specified enclave. For entry to a 64-bit enclave, the processor checks

1. A bound directory used in a 64-bit enclave always comprises 228 64-bit BDEs and thus has a size
of 2 GBytes.

Document Number: 335252-001, Revision: 1.0 15

 whether certain linear addresses are canonical, generating a general-protection
exception (#GP) if any one is not. The following items detail these checks.
— The linear address of the specified entry point must be canonical. If 4-level
paging is active, it must be 48-bit canonical; if 5-level paging is active, it must
be 57-bit canonical.
— The linear address of the asynchronous exit point (AEP — the address to which
the processor transfers control on an asynchronous enclave exit) must be
canonical. If 4-level paging is active, it must be 48-bit canonical; if 5-level
paging is active, it must be 57-bit canonical.
— The enclave values for the base addresses of the FS and GS segments must be
canonical. On processors that supports 5-level paging, these checks are for 57-
bit canonicality, regardless of the current paging mode.
• The EEXIT leaf function exits the currently executing enclave and branches to a
specified address. For an exit from a 64-bit enclave, the processor checks whether
that target linear address is canonical, generating a general-protection exception
(#GP) if it is not. If 4-level paging is active, it must be 48-bit canonical; if 5-level
paging is active, it need only be 57-bit canonical.

As noted in Section 2.7, executions of BNDLDX and BNDSTX in a 64-bit enclave always
operate as if MAWAU = 0.

16 Document Number: 335252-001, Revision: 1.0

3 Linear-Address Expansion and
VMX Transitions

As noted in Section 1.2, VM entries and VM exits manipulate numerous processor

registers that contain linear addresses. The transitions respect the processor’s linear-
address width in a manner based on canonicality.

As discussed in Chapter 2, processors that support 5-level paging expand the linear-
address width from 48 bits to 57 bits. That expansion changes the operation of VMX
transitions. Changes to VM entries are detailed in Section 3.1, while changes to
VM exits are given in Section 3.2.

3.1 Linear-Address Expansion and VM Entries

Certain fields in the VMCS correspond to registers that contain linear addresses.
VM entries confirm those fields contain values that are canonical. This checking is
based on the linear-address width supported by the processor (e.g., is based on 57-bit
canonicality if the processor supports 5-level paging). The following are the fields to
which this applies.
• In the host-state area:
— The fields for the IA32_SYSENTER_EIP and IA32_SYSENTER_ESP MSRs.
— The base-address fields for FS, GS, TR, GDTR, and IDTR.
• In the guest-state area:
— The fields for the IA32_SYSENTER_EIP and IA32_SYSENTER_ESP MSRs.
— The base-address fields for FS, GS, TR, GDTR, and IDTR.
— The base-address field for LDTR (if LDTR will be usable).
— The field for the IA32_BNDCFGS MSR (if VM entry is loading that MSR).

A VM entry to 64-bit mode also performs a check on the RIP field in the guest-state
area of the current VMCS. If the VM entry would result in 4-level paging, it checks that
bits 63:48 of the guest RIP field are identical; if it would result in 5-level paging, that
check is on bits 63:57.1

3.2 Linear-Address Expansion and VM Exits

VM exits save the state of certain registers into the guest-state area of the VMCS.
Some of these registers contain linear addresses. As discussed in Section 1.1, the CPU
generally ensures that the values in these registers respect the CPU’s linear-address
width. As a result, the values the VM exits save for these registers will do the same.

1. Note that these checks do not confirm that the guest RIP field is canonical relative to the paging
mode being entered. For example, bits 63:47 are identical in a 48-bit canonical address. However,
VM entry to 4-level paging may load RIP with a value in which bit 47 differs from that of
bits 63:48.

Document Number: 335252-001, Revision: 1.0 17

 There is a special case for LDTR base address. If LDTR was not usable at the time of a
VM exit, the value saved for the base address is undefined. However, this undefined
value is always 48-bit canonical on processors that do not support 5-level paging and is
always 57-bit canonical on processors that do support 5-level paging.

VM exits load the state of certain registers from the host-state area of the VMCS. Some
of these registers contain linear addresses. Each VM exit ensures that the value of each
of the following registers is canonical: the IA32_SYSENTER_EIP and
IA32_SYSENTER_ESP MSRs; and the base addresses for FS, GS, TR, GDTR, and IDTR.
How this is done depends on whether the processor supports 5-level paging.
• If the processor does not support 5-level paging, bits 47:0 of the register are
loaded from the field in the host-state area; the value of bit 47 is then sign-
extended into bits 63:48 of the register.
• If the processor does support 5-level paging, bits 56:0 of the register are loaded
from the field in the host-state area; the value of bit 56 is then sign-extended into
bits 63:57 of the register.

Again, there is a special case for LDTR. LDTR is always unusable after a VM exit. Its
base address may be loaded with an undefined value. This undefined value is always
48-bit canonical on processors that do not support 5-level paging and is always 57-bit
canonical on processors that do support 5-level paging.

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4 5-Level EPT

5-level EPT is a new mode for EPT. As its name suggests, it will translate guest-
physical addresses by traversing a 5-level hierarchy of EPT paging structures. Because
the process is otherwise unmodified, 5-level paging extends the processor’s guest-
physical-address width to 57 bits. (The additional 9 bits are used to select an entry
from the fifth level of the hierarchy.) For clarity, the original EPT mode will now be
called 4-level EPT.

The remainder of this chapter specifies architectural changes to 4-level EPT as well as
those that define and are entailed by 5-level EPT. Section 4.1 describes how the
expansion of the guest-physical-address width affects 4-level EPT. Section 4.2 specifies
how the CPU enumerates 5-level EPT and how the feature is enabled by software.
Section 4.3 details how 5-level EPT translates guest-physical addresses.

4.1 4-Level EPT: Guest-Physical-Address Limit

As explained in Section 1.3, 4-level EPT is limited to translating 48-bit guest-physical
addresses.

This is not a problem on existing processors, because they limit the physical-address
width to 46 bits (see Section 1.1). A processor’s physical-address width also limits
guest-physical addresses. That means that, on existing processors, any attempt to use
a guest-physical address that sets a bit above the low 48 bits will cause a page-fault
exception (#PF).

Processors that support 5-level paging are expected to support 52 physical-address

bits. Such processors allow use of a guest-physical address that sets bits in the range
51:48; no #PF is generated.

A guest-physical address that sets bits in the range 51:48 cannot be translated by 4-
level EPT. An attempt to access such an address when 4-level EPT is active causes an
EPT violation (see Section 1.3).

EPT violations generate information about the exception in a value called the exit
qualification. In general, EPT violations caused by attempts to access a guest-physical
address that is too wide establish the exit qualification as is currently done for other
EPT violations. Exceptions are made for bits 6:3 of the exit qualification, which report
the access rights for the guest-physical address. The new EPT violations always clear
these bits.

4.2 5-Level EPT: Enumeration and Enabling

This section describes how processors enumerate to software support for 5-level EPT
and how software enables the processor to use that support.

4.2.1 Enumeration
Processors supporting EPT enumerate details related to EPT in the
IA32_VMX_EPT_VPID_CAP MSR (index 48CH). Currently,
IA32_VMX_EPT_VPID_CAP[bit 6] enumerates support for 4-level EPT. Processors that
also support 5-level EPT will enumerate that fact by also setting
IA32_VMX_EPT_VPID_CAP[bit 7].

Document Number: 335252-001, Revision: 1.0 19

 The guest-physical-address width supported by a processor is not enumerated using
the IA32_VMX_EPT_VPID_CAP MSR. This is because that width is always the same as
the processor’s maximum physical-address width as enumerated by
CPUID.80000008H:EAX[bits 7:0].

4.2.2 Enabling by Software

A VMM enables EPT by setting the “enable EPT” VM-execution control in the current
VMCS before using the VMCS for VM entry.

Specific details of EPT operation are determined by the extended-page-table pointer

field (EPTP) in the VMCS. In particular, EPTP[bits 5:3] contain a value that is 1 less than
the number of levels used by the EPT. On existing processors, this value must be 3,
indicating 4-level EPT. (VM entry fails if a different value is used.) Processors that also
support 5-level EPT will also allow the value 4 (indicating 5-level EPT).

In summary, VM entry on a processor that supports 5-level check EPTP[bits 5:3]. If the
value is 3, the VM entry activates 4-level EPT. If the value is 4, the VM entry activates
5-level EPT. With any other value, VM entry fails.

4.3 5-Level EPT: Guest-Physical-Address Translation

Like 4-level EPT, 5-level EPT translates guest-physical addresses using a hierarchy of
in-memory paging structures. Because 5-level EPT increases the guest-physical-
address width to 57 bits (from the 48 bits supported by 4-level EPT), 5-level EPT allows
up to 128 PBytes of guest-physical-address space to be accessed at any given time.

The following items describe in more detail the changes that 5-level EPT makes to the
translation process.
• Translation begins by identifying a 4-KByte naturally aligned EPT PML5 table. It is
located at the physical address specified in bits 51:12 of EPTP. An EPT PML5 table
comprises 512 64-bit entries (EPT PML5Es). An EPT PML5E is selected using the
physical address defined as follows.
— Bits 63:52 are all 0.
— Bits 51:12 are from EPTP.
— Bits 11:3 are bits 56:48 of the guest-physical address.
— Bits 2:0 are all 0.

Because an EPT PML5E is identified using bits 56:48 of the guest-physical address, it
controls access to a 256-TByte region of the linear-address space. The format of an EPT
PML5E is given in Table 4-1.

Table 4-1. Format of an EPT PML5 Entry (EPT PML5E)

Bit Position(s) Contents

0 Read access; indicates whether reads are allowed from the 256-TByte region controlled by
this entry.

1 Write access; indicates whether writes are allowed from the 256-TByte region controlled by
this entry.

2 If the “mode-based execute control for EPT” VM-execution control is 0, execute access;
indicates whether instruction fetches are allowed from the 256-TByte region controlled by
this entry.
If that control is 1, execute access for supervisor-mode linear addresses; indicates whether
instruction fetches are allowed from supervisor-mode linear addresses in the 256-TByte
region controlled by this entry.

20 Document Number: 335252-001, Revision: 1.0

Table 4-1. Format of an EPT PML5 Entry (EPT PML5E) (Continued)
Bit Position(s) Contents

7:3 Reserved (must be 0).

8 If bit 6 of EPTP is 1, accessed flag for EPT; indicates whether software has accessed the
256-TByte region controlled by this entry. Ignored if bit 6 of EPTP is 0.

9 Ignored.

10 Execute access for user-mode linear addresses. If the “mode-based execute control for
EPT” VM-execution control is 1, indicates whether instruction fetches are allowed from user-
mode linear addresses in the 256-TByte region controlled by this entry. If that control is 0,
this bit is ignored.

11 Ignored.

M–1:12 Physical address of 4-KByte aligned EPT PML4 table referenced by this entry.

51:M Reserved (must be 0).

63:52 Ignored.

• The next step of the translation process identifies a 4-KByte naturally aligned EPT
PML4 table. It is located at the physical address specified in bits 51:12 of the EPT
PML5E (see Table 4-1). An EPT PML4 table comprises 512 64-bit entries (EPT
PML4Es). An EPT PML4E is selected using the physical address defined as follows.
— Bits 51:12 are from the EPT PML5E.
— Bits 11:3 are bits 47:39 of the guest-physical address.
— Bits 2:0 are all 0.
Because an EPT PML4E is identified using bits 56:39 of the guest-physical address,
it controls access to a 512-GByte region of the guest-physical-address space.

Once the EPT PML4E is identified, bits 38:0 of the guest-physical address determine the
remainder of the translation process exactly as is done for 4-level EPT. As suggested in
Table 4-1, the values of bits 2:0 and bit 10 of the EPT PML5E are used normally (in
combination with the corresponding bits in other EPT paging-structure entries) to
determine whether EPT violations occur. The accessed flag (bit 8) in the EPT PML5E is
updated as is done for other EPT paging-structure entries.

4.4 5-Level EPT and EPTP Switching

The value of EPTP may be modified in VMX non-root operation by invoking
VM function 0 (EPTP switching). This is done by executing the VMFUNC instruction with
value 0 in the EAX register. Invocation of VM function 0 loads EPTP with a value
selected from a data structure in memory.

Before loading EPTP in this way, the processor first confirms that the value to be loaded
is valid. The definition of a valid EPTP value depends on whether the processor supports
5-level EPT.
• If the processor does not support 5-level EPT, an EPTP value in memory is
considered valid if it would not cause VM entry to fail (e.g., it does not set any
reserved bits).
• If the processor does support 5-level EPT, an EPTP value in memory is considered
valid only if it would not cause VM entry to fail (as above) and if its value in
bits 5:3 (which controls the number of EPT levels) is the same as that of the
current value of EPTP.

The implication is that an invocation of VM function 0 cannot change the EPT mode
between 4-level EPT and 5-level EPT.

Document Number: 335252-001, Revision: 1.0 21

22 Document Number: 335252-001, Revision: 1.0
5 Intel® Virtualization
Technology for Directed I/O

Intel® Virtualization Technology for Directed I/O includes a feature called DMA
remapping.

DMA remapping provides hardware support for isolation of device accesses to memory.
When a device attempts to access system memory, DMA-remapping hardware
intercepts the access and utilizes paging structures to determine whether the access
can be permitted; it also determines the actual location to access.

The DMA-remapping hardware may support two levels of address translation. One level
may translate a linear address to a guest-physical address, while a second level may
remap the guest-physical address to physical address.

The first-level translation uses paging structures with the same format as those used
for ordinary paging. The second-level translation uses paging structures with the same
format as those used for EPT.

It is expected that, on platforms that support wider linear and guest-physical addresses
(using 5-level paging and 5-level EPT, respectively), the DMA-remapping hardware will
be similarly enhanced to support those wider addresses with 5-level translation
processes.

This enhanced support for DMA remapping will be detailed in a future revision of the
Intel® Virtualization Technology for Directed I/O Architecture Specification.

Document Number: 335252-001, Revision: 1.0 23

24 Document Number: 335252-001, Revision: 1.0
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Resident-General, was in a position of power. To act truthfully and
sincerely in his relations with this powerful friend, and to co-operate
with his endeavors at the improvement of the national condition,
would, then, be his own best way to secure for his people
“instruction in right ways,” “the opening of their minds to
enlightenment and modern ideas,” and an effective “contribution to
their progress.”
Moreover, it must be remembered that there had been for
centuries, and there were still, two parties in Japan, with reference
to the proper treatment of Korea. One was the party which favored
friendship between the two countries and a peaceful development of
the interests so important to them both; the other was the party of
the strong hand, which was always urging the immediate application
of the most drastic measures. If it seemed desirable at any time for
Japan to do so, the latter party was ready for subjugation of the
country by the military and for putting it under military control.
Marquis Ito had always been one of the foremost leaders of the
party of peace; he had indeed risked not only his reputation as a far-
seeing statesman, but even his personal safety and his life, in behalf
of the peaceful policy. Let His Majesty carefully reflect upon what it
would mean for him and for his country for the present peaceful
plans of the Japanese Government, under the present Resident-
General, to prove unavailing for their difficult task.
But if His Majesty continued to fail of an appreciation of the real
situation, if he persisted in trusting those who were deceiving him
with vain hopes and robbing him and the nation of its resources and
its opportunity, I had the gravest fears that ruin would follow for him
and for his house; and then great increase of trouble for the people
of the land. All this I wished to say to him, not at all as a politician or
as a diplomat, but as a teacher of morals and an observer of human
affairs. Nor did I speak on account of my friendship for Marquis Ito
simply; and not at all by His Excellency’s instigation or request. I was
moved by a sincere desire to see Korea really prosperous and, if it
might be so, to contribute in some small way to the instruction,
enlightenment, and progress of its people.
 This message was in due time faithfully transmitted to the
Emperor of Korea, and was listened to with attention and apparently
with the same friendly spirit with which it was sent. Its reception
was followed by the “sincere (?) promise to heed its injunctions and
with a protestation of respect and affection for Marquis Ito.” This is
His Majesty’s habit when he is not excited for the moment by the
passions of anger or fear. “In at one ear and out at the other”—such
is the description which those who have had most experience with
this monarch testify as to the real effect upon him of all such advice.
If any honest intention is ever really formed to keep the promises, to
be true to the protestations and pledges made on such occasions, it
is habitually scattered to the winds by the next impure breath which
blows upon him. A master of intrigue himself (an intrigue of the
Korean type which combines as, perhaps, nowhere else in the world
the unmixed elements of a tenuous subtlety and a fatuous silliness),
the Emperor of Korea is also the victim and willing subject of
intriguing eunuchs, concubines, sorceresses, Yang-bans, and
unscrupulous and unsavory foreign adventurers. From his point of
view, his missionary physician is his spy; and, from the same point
of view, the guest of Marquis Ito was, as a matter of course,
suspected of being a spy—in the one case in behalf of, in the other
case against, his cherished interests. And these interests are not the
welfare of his country, or even those more important and lasting
interests that concern his own crown and the perpetuation of the
royal house. They are sensuous and personal. Yet this complex
character is truthfully described as amiable, kindly by preference,
and ready to smile upon and give gifts to all. But this, too, is a
problem which requires further consideration, as one of interest from
the psychologist’s point of view not only, but also and chiefly, from
the point of view which regards the social and political relations of
Japan and Korea. At the time my message was delivered, and even
before it was sent, the fatal mistake of sending a Commission to The
Hague had been made. In the case of monarchs and of nations, as
in the case of common folk—individuals and communities—there are
promises sincerely made, but made too late, and penitence which
follows but does not anticipate and prevent the last fatal
consequences of years of folly and of crime.
To these results of my observations in Korea the following
particulars should be added in this place. As has just been indicated,
one of the strongest and most fixed impressions made was that of
the well-nigh hopeless corruption of the Korean Court. Of intrigue
and corruption there is doubtless enough in all courts, especially in
those of Oriental countries. Nor are these evils by any means absent
from the political centres of Republican Governments, whether of the
national or local character. But the intrigue and corruption of the
Korean Court are of a peculiarly despicable and, indeed, intolerable
character. The premises in which it is housed at present are entirely
lacking in any appearance of dignity; are, indeed, almost squalid. In
a commonplace brick building were lodged the Emperor, the Crown
Prince, Lady Om, the little Prince her son, and an innumerable
number of court officials, court ladies, and eunuchs. The Cabinet
Ministers in attendance during the night await the Imperial pleasure
in a Korean house near the courtyard, in rooms hardly larger than
horse-stalls. At times the contents of the cesspools, in close
proximity to the main palace gates, offend both eyes and nose. So
often as the rigorous inspection of the foreign lady in control of such
affairs is relaxed, the filth in the apartments themselves begins to
accumulate. Gifts to His Majesty, in value all the way from expensive
screens to baskets of fruit, are appropriated by the court rabble to
their own uses. Dishes, and even chairs, are often stolen by the
lackeys and coolies at the Imperial garden-parties. Yet there is a
marvellous display of gorgeous uniforms worn by the court
functionaries; and these functionaries are numerous enough to cover
all the usual bureaus, ceremonies, decorations, and offices really
existing or imaginary, with the customary crowd of masters of
ceremony and chamberlains thought needful for the courts of the
largest and wealthiest nations. At the time of the disbandment of the
army, thirty generals and only ten colonels constituted the corps of
officers in command.
 All these appointments have hitherto been dependent on the
“gracious favor” of His Majesty and have been dispensed without
regard to moral character or any form of fitness, or to the real
interests of the nation. Indeed, it is no exaggeration to say that they
have often been sold to those who offered the highest percentage of
squeezes for the outstretched royal hand. To secure them, access to
the ear of the Emperor is indispensable in most cases. Not a few of
the most low-lived and unscrupulous of his subjects and of
foreigners have been recipients of royal favors in this way. To quote
the words of one who knows: “Now it was the interpreter of a
foreign legation, now a common police spy, now a minister or ex-
minister of State, and now some comparatively humble member of
the Imperial entourage. The soothsayers, geomancers, and others of
that ilk, were always present, and frequently influential in devising
grotesque schemes which spelled profit to themselves and to other
hangers-on of the court. But the most constant influence at court of
late years was that exercised by some of the eunuchs. Among these,
the chief eunuch Kang, was probably the most powerful. He grew
rich upon the perquisites of office, and would undoubtedly be
flourishing still, had it not been for the famous house-cleaning which
the-court underwent some time ago. He then fled, and report has it
(seemingly with good reason) that he was harbored nearly two
weeks for a substantial consideration, in the house of a foreigner
connected in a subordinate capacity with an American business
concern. When in his heyday he exercised great personal influence
with the Emperor, and there are well authenticated instances of
cabinet ministers having bribed him in order to secure access to the
Imperial presence.”
It should also be remembered that this state of things in the Court
of Korea was not at all in spite of the Emperor, but was rather of his
own choosing. Indeed, his character and habit of conducting his
Imperial office was the principal effective reason for the
perpetuation of such corruption. The signs of this stream of evil
influence are by no means all concealed. Every day of my stay in
Seoul I was witness to the line of jinrikishas, and the procession of
pedestrians—many of a by no means prepossessing appearance—
along the lane on which stands the gate through which those
seeking audience were passing in to the palace enclosure. As to
foreigners who, in person, are introduced to the Emperor, the
Japanese Government had then a practically efficient control. But for
Korean subjects, and for foreigners using Koreans to further their
schemes, there was at that time still abundant access. And the
number of those who visited this “prisoner in his palace” was
frequently advertised in the daily news as counted by scores and by
hundreds. To leave his “prison” and go out upon the streets of Seoul
otherwise than on those rare ceremonial occasions when everything
is prepared beforehand, would have been for His Majesty to break
with the etiquette of centuries. Now, however, that the Japanese are
in much more complete control, the freedom of the Emperor’s
movements is greatly enlarged.
I shall not easily forget how the contrast between the new forces
of spiritual uplift and the old forces of intellectual and moral
degradation came over me, as I was present one Sunday at the
morning service of the Methodist church, which stands just across
the way from the palace enclosure. The combined congregations
gathered here numbered an audience of more than one thousand,
nearly one half of which were children. Bishop Ross preached a short
and simple sermon, Dr. Jones interpreting. Several of the American
delegates to the great missionary Conference in China, on their way
homeward, were present, surprised and rejoicing in the size and
enthusiasm of the Korean multitude of hearers. The girls from one of
the schools patronized by Lady Om (whose true history is told in Mr.
Angus Hamilton’s book, and who is now euphemously styled the
“Emperor’s consort”), which had recently been complained of by the
English edition of the Korean Daily News for “being used to foster
allegiance to Japan,” were singing “I surrender all to Jesus.” But
what was then being done a few yards distant, just over the palace
wall, where were living a collection of as vulgar, ignorant, corrupt,
and murderous men and women as were to be found anywhere in
so-called “heathendom”?
 How the intrigue and deceitfulness, combined with weakness, of
the Korean Emperor and his Korean and foreign friends, terminated
with the commission to The Hague Peace Conference is now a
matter of history. As such, it demands a further study in its historical
origins and historical setting.
The impression which I received as to the capacity and character
of the Korean official and Yang-ban (or “gentry”) class was, on the
whole, not reassuring in regard to their real willingness or ability to
inaugurate and support governmental and industrial reforms in
Korea. It is indeed difficult for one born and fostered under an
Occidental—and, perhaps, especially an American—system of
civilization justly to appreciate the institutions and the personal
characteristics of the men of the Orient. Of this difficulty I had had
an initial experience on my first visit to Japan fifteen years ago.
Repeated visits to Japan, and intimate intercourse with Japanese of
various classes, together with painstaking observation of the people,
had enabled me to overcome this difficulty to a considerable extent,
so far as the Land of the Rising Sun is concerned. But, as has
already been indicated, Old Japan was really more like Mediæval
Europe in many of its most essential psychological and social
characteristics, than like either modern India, or China, or Korea. A
winter spent in travel and lecturing rather widely over India was of
more important service in coming to an understanding of the upper
classes in Korea. This, too, is insufficient for a standard of
comparison. With the high-caste Hindu a Westerner of reflective
mind will, of course, have many intellectual interests in common.
With the Korean Yang-ban, except in the very rarest cases, there can
be no common interests of this kind. The problems of life and
destiny, the Being of God, the constitution of the universe, the
fundamental principles of ethics, politics, and law are of little
concern to him. It is doubtful, indeed, whether it has ever dawned
upon his mind that there are such questions worthy of patient
consideration by the reflective powers. A few, but a few only—such,
at any rate, was the impression made upon me—have a genuine,
unselfish, and fairly intelligent sentiment of patriotism as
distinguished from a desire to use office and influence for the
promotion of their own self-interested ends. And these few—even
that still smaller number who to the sentiment of patriotism add
manly courage, strength of purpose, and readiness to suffer—are
incapable of combining their forces so as to carry through in their
own land any policy to secure the most imperatively needed reforms.
After discussing this matter repeatedly with one of Korea’s most
appreciative and respected foreign friends, I forced him to this
admission: namely, there were not, then, so far as he knew, two
leaders of men in all Korea who could come together, trust each
other, agree together, and stand together, to fight and work for the
good of their country to the bitter end. Moreover, had it been
possible to find two, or even twenty, such strong and trusted political
leaders, under his late Majesty and the unpurged court of his rule,
the reformers could not have escaped exile or assassination, so far
as Majesty and Court were permitted to have their own way. Indeed,
it was during all that spring only the determined purpose of the
Japanese Government, as administered by Marquis Ito, that made
possible the inauguration and progress of any measure of reform. It
was the same wise policy that stood between the Emperor and a
fate similar to that endured by his royal consort at dawn of October
8, 1895. And only after his friend, the Resident-General, hoping for a
long time against the repeated violation of the grounds of hope, had
reached the sad conclusion that the Emperor’s “disease was
incurable,” and that the vital interests of Korea as well as of Japan
demanded the termination of his unfortunate and disgraceful career,
did the event take place. Even then, however, it was forced by his
own cabinet ministers.
As to the general character of the administration of the
magistrates throughout the country of Korea, in the winter and
spring of 1906 and 1907, there can be no difference of intelligent
opinion. It was essentially the same which it had been for hundreds
of years. With rare exceptions, which were liable to make the
magistrate suspected and traduced to the Emperor and his court,
the local jurisdiction in Korea was a system of squeezes and acts of
oppression, capable of classification only under two important
specific differences. These differences were, first, the marks of
strength and corruption combined with cruelty, and, second, of
weakness and corruption without obvious cruelty. The following
extracts from the Korean Daily News—the paper which (with its
native edition) Mr. Hulbert and Mr. Bethell, its editor, were employing
to excite foreign and native opposition to the Japanese—are only a
small number of the items of news on which this impression was
based:

As a high official was passing through the streets heavily

guarded, a number of men belonging to the chain-gang were
passed. One of them was heard to remark that if the official
were not a criminal himself he would not need the heavy
guard, and he added that after his term of penal labor was
over the first thing he would do would be to kill that official
and a few more like him. These words were heard by all and
they continued until the minister was out of sight.
A man of Ma-chun (near Chemulpo) was recently arrested
by order of the local magistrate and tortured without cause.
After confinement and torture for a period of eight days the
man expired and his relatives are now asking the Supreme
Court to look into the matter and punish the magistrate.
A report from South Chul-la Province states that the people
in a certain section there do not look with favor on the new
tax-collectors; on the contrary, they say that they will tie up
the collectors with ropes and make life hard for them.
A Japanese report from the far Northeast says that a band
of 500 Koreans attacked the Japanese at Whang-hai-po and
some people were wounded by the Koreans; they were
repulsed by Japanese gendarmes from Kyung-heung.
On Tuesday evening over 250 rioters marched down on
Neung-chon district, broke down the telegraph poles, and
attacked the people. The matter was reported to the police
 and many were despatched to the scene of the outbreak. The
rioters, however, had dispersed before they could be arrested.
We hope it is not true, as the Koreans report, that the
Governor of Chung-ju has eaten the money which the
Emperor gave for the relief of the sufferers from the flood
there last autumn. He is said to have gone even further than
this and compelled these destitute people to give their time
for nothing to public works. This is worth looking into.
An armed band of robbers made a raid on the road-
repairing bureau at Chin-nampo the other day and carried
away considerable property. In the struggle the Japanese
engineer and two Korean officers were severely wounded.
It is time that serious steps were taken to put down the
brigandage that prevails in the country. No one’s property
appears to be safe, for we now learn that the Dongak Sa
monastery in Kong Chu district has been rushed by robbers
and pillaged of everything that was at all valuable.

It must not be supposed that these instances of disturbance in the

provinces are rare and selected from a long period of time. Indeed,
fully one-half as many instances, illustrative of the condition of
things prevalent in the country districts of Korea as have been given
above, might have been taken from single issues of this morning
paper. So true is this that its daily column headed “Local News and
Comment,” called out an ironical article from the Japanese semi-
official paper, the Seoul Press, entitled “Speak Well of Your Friends.”
In this article was the assertion: “A digest of its issues (i. e., of the
Korean Daily News) for one month, as far as they relate to the
Koreans, would indicate that outside Seoul every third Korean was a
bandit, while in Seoul every other man was either a traitor or
corrupt. This hardly appears to be the way to establish a good
reputation for the Koreans.” One needs, however, to know only a
little as to the proper reading between the lines, in order to discover
that the real reason why there was a dearth of good news, of
importance enough to print, in this anti-Japanese paper was this:
almost all such items would have accrued to the credit of the
Japanese Administration. Such items would, therefore, bring into too
strong contrast, to suit these foreign friends of Korea, the traditional
ways and results of the Korean Government and the already
manifest effects of the reforms that were being carried through by
the Resident-General and his Japanese and Korean helpers.
The news from the country, as given by the pro-Japanese press
did not differ from that given by this anti-Japanese paper from which
extracts have already been made. The former, however, dwelt much
more upon the changes for the better which were being
accomplished, chiefly at Seoul, but also in other cities and even in
the country districts. The following extracts, selected from a number
of similar items, will show this statement to be true. Says the Seoul
Press:

A report received in the Police Adviser’s Office here on

Monday night states that a body of rioters assaulted and set
on fire seven buildings of the District officials of Ko-syöng,
South Kyöng-sang-do. The officials have all taken refuge in
Chin-nampo, and two leaders of the rioters were arrested.
The rioters, however, show no signs of dispersing. All
foreigners and the police are said to be safe, but there were
some casualties on the side of the rioters. According to a later
report received here from Vice-Resident Wada at Masan, the
rioters assembled numbered some 1,500. Grievances in
connection with taxation were the immediate cause of the
trouble. On the night of the 6th instant the mob stormed the
office of the District Magistrate and destroyed the jail,
liberating all prisoners within. In addition, they burned down
seven buildings of the district officials, and some people were
seriously injured. Police Inspector Nakagawa’s men, in
conjunction with the twenty troops told off from Chin-nampo,
succeeded in arresting three rebel leaders. The District
 Magistrate escaped, and all the Japanese are safe. The
disturbance has not yet been suppressed.

Still another item from the Seoul Press narrates a similar

experience:

Disquietude of a somewhat serious nature is reported from

Kim-hai, under the Fusan Residency. About six o’clock in the
morning of the 14th inst., the Residency of Fusan received a
message from Kim-hai to the effect that a number of Koreans
were threatening to storm the District Office on account of
some grievance connected with taxation. Several policemen
were at once despatched to the scene of trouble, where they
found a crowd of natives actively rioting. The latter broke
open the prison, set all its inmates free and, far from yielding
to the advice of the policemen to disperse, offered obstinate
resistance. The policemen found the odds hopelessly great,
and decided to ask for re-enforcements. About this time there
arrived a force of our gendarmes who hastened to the
disturbed scene on receipt of the news that Mr. Lyang Hong-
muk, the Magistrate of Kim-hai District, had been taken
prisoner by the rioters, and that our police force from Kui-po,
having attempted to recover the Magistrate, were suffering
from the violence of the furious mob. The mob, however,
successfully checked the advance of the gendarmes for some
time by the free use of cudgels and other weapons. In the
meantime, Mr. Lyang was carried away by the mob and his
whereabouts is still unknown. Police re-enforcements
subsequently arrived, and ordered the rioters to go home, but
in vain. It is stated that the situation is assuming a more
serious aspect. A joint force of our gendarmes and policemen
was despatched from Fusan early on the morning of the 15th
inst. Reports conflict about the number of rioters, but it is
believed that they are some 400.
 All this, and similar experiences, as well as the history of the
Korean people for two thousand years, raises the serious question of
the possibility of a truly national redemption. Both before and during
my visit to Seoul I was given to understand by foreign residents,
Japanese and European, that the case of the nation is hopeless;
their whole social and political system is decadent; they are an
effete race, destined to give way before the invasion of members
from any more vigorous race. But Marquis Ito evidently entertained
no such view. It was the Korean nation which he desired to rescue
and to lift up—whether with, or without, the consent and assistance
of their Emperor and his court. Of the same opinion with the Marquis
were the missionaries. Many of these were extravagant in their
praises of the native characteristics of their converts, and not only
sincerely attached to them, but also confident of their capacity for
educational advancement and moral and social reform. To be sure,
when asked more particularly as to what were the precise traits of
character which encouraged these hopes and elicited this affection,
and when reminded how almost universal had been the confessions,
recent and still going on among the native Christians, of long-
continued indulgence in the vices of lying, dishonesty, and impurity,
there was no altogether satisfactory answer to be given. The
grounds for praise were usually exhausted when the amiable and
affectionate nature of the Korean had been duly emphasized. To
increase my distrust of the view held by the missionaries, were the
facts gained in conversation with others who had been witnesses to
the actions of the excited Korean populace; who had seen Korean
officials that had offended this populace, or had been the object of
some trumped-up charge circulated by their political rivals and
enemies, beaten, jumped upon, smashed, torn limb from limb by
their “gentle” and “amiable” fellow-countrymen. Nor were these
things done in remote country-places, but in Seoul itself, near the
Great Bell in the neighborhood of Song-do. I had also heard from
the lips of Mr. Morris, manager of the Seoul Electric Railway, the
story of how, at three o’clock in the morning of the night of May 27,
1900, he had been called out of bed and, accompanied by an escort
of Japanese soldiers, taken to the prison near the Little West Gate to
view the bodies of An Kyun Soo and Kwan Yung Chin. These were
reformers who had been cajoled through promises of fair treatment
by the smiling Emperor and his officials to return from exile in
Japan; whereupon they had been foully murdered. Was one to share
the “shivery feeling” with which Mr. Morris passed between the rows
of instruments of torture to view the red marks of the cord with
which these patriots had been strangled; or was one to trust the
estimate of their Christian teachers regarding the mild and lovable
disposition of the native Koreans? There was also the glimpse into
the smouldering fires of hatred and cruelty, mingled with cowardice
and hypocrisy, which I had myself had during the visit to Pyeng-
yang. And there were the unceasing daily items of both the pro- and
the anti-Japanese papers, to which reference has already been
made. Finally, there was the fact that these characteristics of the
Korean populace were historical, and were chiefly in evidence among
themselves, in their relations toward their own countrymen rather
than directed toward foreigners, even including the Japanese. Out of
this confusion of witnesses there slowly emerged the conclusion that
the mixture of good and bad needed itself to be historically
explained; therefore, neither the denunciations of the one party nor
the praises of the other could afford to the observer the sufficient
reasons for a just judgment of the native character. It is, indeed, on
the whole, just now rather more despicable than that of any other
people whom I have come to know. But it is not necessarily beyond
redemption. At any rate, here is another question which needs
illumining in the whiter and broader light of history.
The impressions gained as to the Koreans—Emperor, Court, Yang-
bans, and populace—were, of course, intimately associated with the
impressions formed as to the nature and efficiency of the forces
chiefly at work for the reform and uplift of the nation. Such
reforming and uplifting forces are undoubtedly these two: the
personality of the Resident-General, assisted in his work by the
official corps under him, and supported by the Government of His
Imperial Majesty of Japan; and the Christian missionaries. What
impressions, then, seemed warranted by my observations as to the
soundness and efficacy of these two forces?
As to the sincerity of Marquis Ito in his self-sacrificing and arduous
task of effecting a reformed condition, industrially and politically, of
the Korean nation, no shadow of doubt ever arose in my own mind.
But this is a relatively small and unimportant thing to say. It is more
instructive as to the truth to notice that his sincerity was, so far as I
am aware, never questioned by any one, not even by those most
hostile to his policy, except in an obviously ignorant and hypocritical
way. The extreme military party of Japan, the advocates of the
strong hand and of immediate forcible annexation, as well as anti-
Japanese missionaries and other foreigners, and even that Korean
officialdom which always has so much difficulty in believing that any
one in office can be sincere—all these, as soon as ignorant prejudice
became but partially enlightened, ceased to bring the charge of self-
seeking and deceit against the Resident-General. For he had
unmistakably affirmed, both privately and publicly, to his own
countrymen, to the Koreans, and to the world, that it was his
intention to do all that in his power lay for the betterment of the
condition of the Korean people themselves. When His Korean
Majesty, who had not only repeatedly violated his most solemn
treaty obligations, but had also, with frequent prevarications,
falsehoods, and treachery, broken his equally solemn promises to
the man who was far more unselfishly interested in the welfare of
Korea than was its ruler, involved himself in sore trouble, he, too,
turned to the Marquis Ito for advice and help. That even the
insincere Korean Emperor and his corrupt Court believed in the
sincerity of the Resident-General I have abundant reason to know.
It was not the sincerity of Marquis Ito, however, which made most
impression upon the leading people of Seoul; it was rather the
qualities of patience, pity, and gentleness. Such are, indeed, not
usually the mental attitudes of the diplomat or politician toward
those who are intriguing, or otherwise actively endeavoring to defeat
his cherished plans. It should not be forgotten that less than a year
before, during the absence of the Resident-General, a plot had been
formed which involved his assassination; and that this plot had been
traced to those who had the entrée of the Palace, in despite of their
well-known bad character, and some of whom were the recognized
Korean associates of the men whose “services” to the Korean
Emperor terminated in the commission to the Peace Conference at
The Hague. Of those Korean officials who were most opposed to the
Japanese Protectorate, the Marquis was ready to say that he
sympathized with them in their desire for the perfect independence
of their country; nor did he blame them for their struggles to bring
about this result so long as their way was free from lying, robbery,
and murder. But the witness of history he regarded as
unimpeachable proof of the incapacity of the Korean ruling classes to
lift up, or to rule well their own country; unaided, they could never
effect the reformation of existing industrial and social evils. Japan,
the Far East, and the interests of the civilized world forbade their
being longer permitted to disturb the peaceful relations of foreign
nations. In this connection the Marquis once spoke of the difficulty
which he experienced in preventing his own countrymen from
themselves degenerating in character under the morally depressing
influences of Korea. These influences had, in his judgment, been
more or less effective in the case of most foreigners—diplomats and
missionaries included—who had lived for a long time in Seoul. “I tell
them,” said he, “you must not become Koreans; you are here to
raise the Koreans up, and you cannot do this if you sink down to
their level.” At a small dinner party, at the house of one of the
foreign consuls, the Resident-General spoke more freely than is his
custom about his own early life, his observations during his several
trips abroad in America, Europe, and Russia, and the ideals which
had guided his official career. In this connection, with reference to
his present work in Korea, he referred to the expressions of surprise
from some of his foreign colleagues, that he could endure so calmly
the ways of the Koreans toward him and toward his administrative
efforts; but “in truth,” he added, “I have no feelings of anger toward
these people; they are so ignorant, they have been so long deprived
of all honest and enlightened government, they are so poor and
miserable, I am not angry with them. I pity them.”
 It will doubtless seem a strange reversal of what many in the
United States and elsewhere have been led to believe was true—and
certainly it is a strange reversal of what ought to have been true—
when I say that the patience and sympathy of Marquis Ito in his
relations with the foreign Christian workers in Korea was a surprise
to me. The behavior of some of the missionaries and men prominent
in the circle of the Young Men’s Christian Association, which was in
receipt of a subsidy from the Japanese Government, had been trying
indeed. That their professed Korean converts and adherents had
used the name of Christian and the Christian organizations for selfish
political purposes could not have been wholly avoided. Even the
threats of legal proceedings had been unable to prevent this. But
that injudicious reports of wrongs, either exaggerated or wholly
false, should be sent by private and public letters to the “home
country,” while the requests of the Resident-General to learn of these
wrongs and to have the opportunity to correct them remained wholly
unheeded, constituted a trial to patience which, I am of the opinion,
few men in his position would have borne so well. Emphasis was
given to this by the fact that some of the most violent and false
accusations against the Japanese Government in Seoul were made
in papers and books published by authors who were known to be on
terms of friendship with foreign religious agencies. Even certain paid
attorneys of the Imperial intrigues against the Resident-General
were of this connection. To all this it should be added that His
Excellency was being severely (although by no means fairly)
criticized in his own country for his “excessive” patience toward
these teachers of a foreign religion. Excited by the reports which
were coming from the United States (see p. 62), one of the
respectable Japanese papers of Tokyo (the Yomiuri, in its issue of
May 6th) had found it “necessary to examine the past conduct of the
American missionaries in Korea.” It expressed profound admiration
“for the personality of the Founder of Christianity and high respect
for the enthusiasm and devotion of his followers.” But as for those
who, “wearing the mask of missionaries ... pander to the native
prejudices ... and endeavor to thwart our policy by disseminating
baseless rumors and mischievous insinuations, there ought to be no
hesitation to deport them out of the country.” “Marquis Ito, as a
friend of peace and liberty, has already shown more than sufficient
conciliation and patience.”
The story of the better way which Marquis Ito steadily followed,
with its unwavering policy of conciliation and patience, and of its
success so far as the majority of the more representative and
influential of the missionary body is concerned, has already been
told in part. For the small number who still refuse to respond to this
policy, it is, of course, not deportation by the Japanese Government,
but counsel and rebuke from their employers at home, which is the
proper remedy. But the impressions of the visitor, who had full
measure of the confidence of the leader of one of these two parties
who are working for the redemption of Korea, and some good
measure of the confidence of certain leaders of the other party, can
be given in no other way so well as by quoting the following words
from one of their number:
“From the Peninsula,” said Dr. George Heber Jones, in an address
to the First General Conference of the Methodist Church in Japan,
“we watch with intense interest the development in Japan; for
Providence has bound up together the destinies of the two nations.
Nationally, a new life opens up before Korea. Japan has sent her
veteran statesman to advise and guide Korea, the man to whom in
the largest sense Japan owes so much—the most conspicuous
statesman in Asia to-day, Marquis Ito. Plans for the reform of the
Government, codification of the laws, development of the industry
and business of the people, and extension of education, have been
formulated, and in a comparatively short time most promising results
achieved. In spite of difficulties which necessarily for the present
encumber the situation, the outlook is most hopeful. As a church in
Korea we deliberately stand aloof from all politics, but find our work,
as it relates to the production of strong character, of honest, upright,
true men, most intimately related to the regeneration of the nation.
The coming ten years promise to be the most eventful in the history
of Korea.”
 At a tea-party, given in the gardens of Dr. and Mrs. Scranton, at
Seoul, where Bishop Cranston, Bishop Harris, Dr. Leonard and Dr.
Goucher, were among the non-resident guests, Marquis Ito was
present; having arrived somewhat earlier than the appointed hour.
After greeting the ladies and gentlemen present, the Marquis spoke
as follows:

I wish to take this opportunity of saying a few words to

you. I beg you, however, not to expect that I shall say
anything new or striking. I only mean to repeat to you what I
have been saying to the Japanese and the Koreans. If my
words are not new or striking, I may at least assure you that
what I am going to say comes from my heart, and represents
just what I feel and think. As the official representative of
Japan in this country, my principal duty consists in guiding
and assisting Korea in her efforts at improvement and
progress. I entertain deep sympathy with the people of this
country; and it is my earnest ambition to help in saving them
from the unfortunate state in which they now find
themselves. You, ladies and gentlemen, are also here for
serving and saving the Koreans. The only difference is that,
while I seek to serve them through political and
administrative channels, you work for the same end by means
of religious influences. We thus stand on common ground, we
are working for a common object. You will therefore believe
me when I assure you that I always take the most
sympathetic interest in your noble work, and that I am ever
ready to co-operate with you, in so far as my duties permit, in
your efforts to further the moral and intellectual elevation of
this people. On the other hand, I feel confident that I may
rely upon a similar attitude on your part toward my endeavors
for the benefit of the Koreans. As to the political relations
between Japan and Korea, it would be too long and tedious
to refer to the past; it is a long history. It is sufficient for my
present purpose to say that the two countries are so situated
 toward each other that their destinies are bound together in
the closest manner. To maintain undisturbed the close mutual
relations which fate has ordained for the two countries, is the
object for which Japan is in this country; beyond that she has
no other object. As you know very well, Korea can hardly be
called an organized state in the modern sense. I am trying to
make it such. Whether, or how far, I may be able to realize
my object in this work of political regeneration, as also in the
task of improving the general lot of the people, God alone
knows. All that I can say to you is that I shall do my best for
the successful realization of my mission. I may be permitted
to refer to a matter in which you can do much good for
Koreans. I dare say that among the many thousands of
Japanese in this country, there are some who disgrace their
nation by misconduct toward Koreans; but you may rest
assured that these wrong-doers find in me the most
uncompromising enemy. I may also say that wrong-doing is
not confined to the Japanese; there are similar offenders
among the Koreans too. While I am taking unsparing pains to
repress wrong-doing among the Japanese, I rely upon you for
your hearty co-operation to the same end among the
Koreans, in so far as it lies in your power as their religious
teachers and leaders.

But the wisdom and firmness of the Resident-General were no less

impressive than were the qualities of patience and gentleness. To
the student of Korean affairs, of the more recently past and the
present relations of the Japanese to the Koreans, it soon becomes
patent what is chiefly needed in order to mend the former and to
improve the latter. It is first of all the impartial administration of
justice, in the way of righting wrongs, so far as this is possible, and
of securing the rights of life, liberty, and property; then comes the
fostering of education in the industries and arts, and the progressive
elevation of the moral and religious condition of the people. At the
time of my visit there were numberless claims pending of fraud and
violence—not so much of recent occurrence as acts of some months
or years old—on the part of Koreans against Koreans, and of
Japanese and Koreans against each other. Land had been seized and
stolen outright, or fraudulently obtained by forged deeds or under
false titles. Foreign promoters were clamoring over privileges and
concessions, which were either purchased with some show of
fairness or obtained from His Majesty, or from some subject, by
partnership with the crowd of Korean official “squeezers.” The
weaker race—it was claimed—was oppressed, insulted, beaten, or
rudely pushed around—not now by their own officials or by Chinese
or Russians, but by a people whose superiority of any sort it
humiliated their traditional pride even grudgingly to admit. The
ability of the most honest and capable local magistrate, whether
Japanese or Korean, to discover the truth and to do any measure of
justice was greatly hampered and, indeed, made almost practically
unavailing by the differences in the two languages and by the fact
that the interpreters themselves could, for the most part, in no
respect be thoroughly trusted. It was, indeed, a favorite trick with
the average Korean interpreter to hire out to one of his own
countrymen who had a case against some Japanese, and then to
betray his client for a bribe from the other side, by misstating or
falsifying his client’s cause. And, under such circumstances, what
could any magistrate do who understood only one of the two
languages? Moreover, according to the testimony of Mr. D. W.
Stevens, who had made careful examination into scores of such
complaints, it was an extremely rare thing for a Korean, even when
he had a perfectly good case, to refrain from mixing a large measure
of exaggeration and falsehood with his truth-telling; nor was it easy
to find any considerable crime of fraud committed against a Korean
by a Japanese without uncovering a Korean partner to the base
transaction. So crafty are the Koreans that, in most cases of such
partnership, it is not the foreign member of the firm who gets the
larger share of the dividends resulting.
All these impressions as to what was most imperatively needed for
the emergencies that were daily arising I was encouraged to
mention to the Resident-General at any of our several interviews. It
was, of course, desirable first of all to prevent the continuance of the
evils which had been, both in Korea and abroad, charged against his
own nationals in their treatment of the Koreans. Inquiry and
observation combined to confirm the opinion that this was already
being accomplished. At that time, however, most of the riots in the
country districts did not appear to indicate feelings of hatred on the
part of the natives toward “foreign oppressors”; they were only the
customary expression of lawless resistance to a condition of
wretchedness and misrule that was of native origin and indefinitely
long-standing. No important acts of violence on the part of Japanese
toward Koreans came under my observation, and none of recent
occurrence were credibly reported. Even of those petty deeds of
rudeness and incivility, which exasperate hostile feeling far beyond
their real significance, I saw comparatively few. There was some
rather contemptuous treatment of the Korean crowd at the gates of
the railway stations and on the platforms of the trains; but the
Koreans are themselves exceedingly stupid and ready to crowd
others; and the handling given them by the Japanese officials was in
no case so rough as that which the proudest American citizen is
liable to receive at the Brooklyn Bridge or on the Fourth Avenue
street-cars. Once, indeed, my jinrikisha-man, after he had several
times warned, by his outcry, a Korean gentleman who was occupying
the middle of the street with that dignified and slow-moving pace so
characteristic of the idle Yang-ban, in order to avoid knocking the
pedestrian down with his vehicle, gave him a somewhat ungentle
push to one side. The Korean fell forward, after the manner of a
boy’s tin soldier before a marble. His crinoline hat rolled off his head,
but alighted a short distance away. At first I was alarmed lest he
might be injured, and was about to order the offending kurumaya to
stop his running that I might offer my assistance. But when it
appeared that neither the victim of this scarcely avoidable rudeness,
nor his hat, was injured, and that no one, including the man himself,
seemed to consider the incident worth noticing, I decided not to
emphasize it further. Undoubtedly, this would not have happened
with a Japanese child or woman in the adult Korean’s place; it might
easily have happened, however, in the streets of Tokyo or Kyoto if
the pedestrian had been a man of obviously inferior rank.
In brief, it was the uniform testimony of those who had been in
Korea during the troublous times which followed the war with Russia
that, under Marquis Ito’s administration, Japanese wrong-doers were
being sought out and restrained or punished, and that deeds of
violence and even of rudeness were becoming rarer with every
month of his stay.
Other measures which seemed to me desirable to have put in
operation were such as the following: a civil-service examination
which should provide that every official, Korean or Japanese, whose
duties brought him into intimate daily relations with both peoples,
should have a working knowledge of both languages; the organizing
of a body of authorized interpreters, whose honesty and ability to
discharge this very delicate and important function of oral or written
interpretation, in all legal causes and matters of Government
business, should be guaranteed, the speedy and even spectacular
demonstration of the Government’s intention to give to the Korean
common people strict justice in all their valid complaints against the
Japanese; the improvement of the character of the Japanese civil
service and of the Japanese police and petty officers of every kind;
and some kind of arrangement between the missionary schools and
the schools under the control of both the Korean and the Japanese
authorities, by which uniformity might be attained in the primary
education, and, in the higher stages, the mistakes made by the
British Government in India might be avoided. These mistakes have
resulted in educating a crowd of native “babus,” who are both
unwilling and unfit for most kinds of serviceable employment in the
real interests of their own nation’s development. As to this last
matter, the statement may be repeated that not a small proportion
of the Koreans educated abroad or in the missionary schools, with
an almost purely literary education, have turned out either useless,
or positively mischievous, when the practical reform and redemption
of their own country is to be undertaken and enforced. For if there is
any one thing which the average educated Korean Yang-ban will not
do, that thing is hard and steady useful work.
None of these measures—it was soon made obvious—were to be
overlooked or neglected in the large and generous plans of the
Resident-General for the reform and uplift of Korea. Time, however,
was needed for them all; they all required a supply of helpers, to
train which time was required. And who that knows the lives of the
great benefactors of mankind, or is versed in the most significant
facts and obvious truths of history, does not recognize the evil
clamor of the press, of the politicians, and of the crowd, to have that
done all at once which cannot possibly be done without the help of
time. The whole explanation of the delay is best summed-up in the
pregnant sentence already quoted from one of Marquis Ito’s public
addresses, which was evidently designed as a declaration of settled
policy on his part. “As you know very well,” said he, “Korea can
hardly be called an organized state in the modern sense; I am trying
to make it such,” But as he explained to me more in detail: “I have
been at work on these difficult problems only one short year,
interrupted by visits to Japan, because my own Emperor required my
presence; and the first half of this year was almost entirely occupied
with such physical improvements as various engineering schemes,
provision for hospitals, roads, and similar matters. There has never
been any such thing as Korean law, under which justice can be
administered impartially. But, according to the constitution of Japan,
no Japanese subject of His Imperial Majesty, as well as no other
foreigners resident in Korea, can be deprived of property, or of
liberty, otherwise than by due process of law. Nor is my relation to
the administration of justice in Korea like that of the British
magistrate in British India. With Korean affairs, purely internal, when
the attempt is made to settle them in Korean fashion, I have no
right, under the treaty, to interfere. And the Koreans, when they
could resort to legal measures for settling their disputes, ordinarily
will not do so; they prefer to resort to the ancient illegal practice of
running to some Korean Court official and bribing him to use
influence on their side. As for Korean judges who can be trusted to
do justice, there is scarcely any raw material even for such judges to
be found. A carefully selected number of jurists, with a large force of
clerks, has, however, been brought from Japan; and they are
diligently at work trying to devise a written code under which the
ancient customs and common laws of Korea, as representing its best
efforts to enact and establish justice, shall be made available for
future use.”
Meantime, as we have already seen, the Resident-General was
being opposed and, as far as possible, thwarted, in every effort to
improve the civil service and judicial administration of Korea, by the
corrupt Korean Court, with its mob of eunuchs, palace women,
sorceresses, etc., and by nearly all the native officials and Yang-bans
in places of influence and power. And the chief seat of corruption
and of opposition to genuine, effective reform was the smiling and
amiable Korean Emperor himself. How effectively, because wisely
and firmly, Marquis Ito initiated and advanced these reform
measures will receive its proof, so far as proof is at present possible,
by examination of results recorded in official and other trustworthy
reports. To the facts already narrated, on which my personal
impression of these qualities was based, many others of even a
more convincing character might easily be added.
Of the feelings of admiration and friendship which grew during
these weeks of somewhat confidential relations, on the part of the
guest toward his host, it would not be fitting to speak with any
detail. But in closing the more exclusively personal part of my
narrative I might quote the words of one of the Consuls-General
residing in Seoul. This diplomat expressed his feeling toward the
Marquis Ito as one of veneration, beyond that which he had ever felt
for any but a very few of the men whom he had met in his official
career.
After all, however, personal impressions, no matter how favorable
to truth the conditions under which they are derived, are not of
themselves satisfactory in answer to questions so grave and so
complicated as those which encompass the existing relations
between Japan and Korea. Such impressions must be subjected to
the severer tests, the more comprehensive considerations, the
profounder sanctions, of history and of statistics. For this reason I
now pass on to the much more difficult task of reviewing in the light
of these tests, considerations, and sanctions, the impressions of my
visit to Korea in 1907, as the guest of Marquis Ito.
 PART II
A CRITICAL AND HISTORICAL INQUIRY
 CHAPTER IX
THE PROBLEM: HISTORICAL

An authentic and trustworthy history of Korea has never been

written; and enormous difficulties await the investigator who, in the
future, attempts this task. The native records, almost down to the
present time, consist of the same uncritical mixture of legend, fable,
oral tradition, and unverified written narrative which characterizes
the earliest so-called histories of all civilized peoples. But the Korean
civilization has not as yet produced any writer both ambitious and
able to treat this material in a way corresponding to the opportunity
it affords. All the narratives of events, except those of the most
recent date, which have been written by foreigners, have, of
necessity, been lacking in that intimate acquaintance with the Korean
language, institutions, customs, and the temperament and spirit of
the people, which is the indispensable equipment of the historian.
The antiquities and other physical records of an historical character
have, moreover, never to any considerable extent been explored. A
striking example of this general truth was afforded only a short time
ago when Dr. George Heber Jones discovered the fact that a wrong
date (by a whole century) had been given for the casting of the
Great Bell at Chong-no—one of the most conspicuous public objects
of interest in Seoul; yet the correct date was inscribed on the bell
itself! The reason for this petty falsifying of historical fact was
characteristically Korean; it was in order that the honor of casting
the bell might be ascribed to the Founder of the present Dynasty.
In spite of these facts, however, the main outlines of the
development of Korea are unmistakable. Its history has been, for the
ruling classes, one long, monotonous, almost unbroken record of
misrule and misfortune; and for the people an experience of poverty,
oppression, and the shedding of blood. That they have endured at
all as the semblance of a nation, although not “as an organized state
in the modern sense,” has been due chiefly to these two causes:
first, to a certain native quality of passive resistance, varied by
periods of frenzied uprising against both native and foreign
oppressors; and, second, to the fact that the difficulties encountered
in getting over mountains and sea, in order to maintain a foreign
rule long enough to accomplish these ends, have prevented their
stronger neighbors on all sides from thoroughly subjugating and
absorbing them. This latter reason may be stated in another way: it
has hitherto never been worth the cost to terminate the independent
existence of the Korean nation.
Nor is it difficult to learn from authentic sources the two most
potent reasons for the unfortunate and evil state throughout their
history of the Korean people. These reasons are, on the one hand,
the physical results of repeated invasions from the outside; and, on
the other hand, the adoption and perpetuation, in a yet more
mischievous and degraded fashion, of the civil and official
corruptions received from Korea’s ancient suzerain, China. It is
customary to attach great importance, both as respects the damage
done to the material interests of the country, and also as accounting
for the Korean hatred of the Japanese, to the invasion of Hideyoshi.
But the undoubted facts do not bear out this contention. The lasting
effects of this incoming of foreign armed forces from the south, and
of their short-lived and partial occupation of Korean territory, were
relatively unimportant. None of the institutions of Korea were
changed; none of her physical resources were largely depleted. It
was just those places in which the Japanese remained in the most
intimate relations with the Koreans, where there was least
permanent development of race hatred. But the results of the
successive invasions from the north and northwest, by the wild
tribes, by the Mongols, and by the Chinese and Manchu dynasties,
were much more injurious in every way to the physical well-being of
the peninsula.
It is one of the most remarkable contrasts between Japan and
Korea that, whereas the more distinctly moral elements of
Confucianism moulded a noble and knightly type of character in the
former country, in its neighbor the doctrines of the great Oriental
teacher chiefly resulted in forming the average official into a more
self-conceited but really corrupt and mischievous personality.
Indeed, the baleful influence of China, especially since the
establishment of the Manchu dynasty, has been the principal
hindrance to the industrial and civic development of Korea. The
contribution made to its civilization by Chinese letters, inventions,
and arts, has been no adequate compensation for the depressing
and debasing character of the imported political and social system.
The official institutions and practices of the suzerain have for
centuries been bad enough at home; but here they have been even
worse, whether admiringly copied or enforced by the influence of its
Court and the power of its army. And, whereas the great multitude
of the Chinese people have displayed for a long time the inherent
power of industrial self-development and of successful business
intercourse with foreigners, the Koreans have thus far been relatively
lacking in the qualities essential for every kind of material and
governmental success. Thus all the civilization of Korea has been so
characterized by weakness and corruption as to excite contempt as
well as disapprobation from the moralist’s and the economist’s points
of view. It is China and not Japan which through some 2,000 years
of past history has been the expensive and bloody enemy, and the
political seducer and corrupter of Korea.
The division of the history of Korea, made by Mr. Homer B.
Hulbert, into ancient and modern—the latter period beginning in
1392, with the founding of the present dynasty—is entirely without
warrant. “Modern history” can scarcely be said to have begun in the
so-called “Hermit Kingdom” previous to the time when a treaty was
concluded between Japan and Korea by General Kuroda, acting as
Plenipotentiary, on February 26, 1876. Even then, the first Korean
Embassy under the new régime, having arrived at Yokohama by a
Japanese steamer on the following May 29th, when it started back
to Korea a month later, refused all overtures of Western foreigners to
communicate with their country. From the time when the present
kingdom arose by the union of the three previously existing
kingdoms, the doings of the Korean Court and of the Korean people
have been substantially the same. When threatened by foreign
invaders or by popular uprisings and official rebellion at home, the
Court—a motley crowd or mob, of King, palace officials, eunuchs,
concubines, blind men, sorceresses, and other similar retainers of
the palace—has, as a rule, precipitately fled to some place of refuge,
deserted by efficient military escort and in most miserable plight.
Only when behind walls and compelled to fight, or when aroused to
a blind fury in the form of a mob, does the average Korean show the
courage necessary to defend or to avenge his monarch. The saying
of the Japanese that “the Koreans are kittens in the field and tigers
in the fortress” characterized their behavior during the Hideyoshi
invasion; it is characteristic of them to-day. Three centuries ago,
when the king was in flight from Seoul to Pyeng-yang his own
attendants stole his food and left him hungry; and the Korean
populace, left behind in Seoul rose at once and burned and looted
what the Court had not carried away. “Before many days had
elapsed the people found out that the coming of the Japanese did
not mean universal slaughter, as they had supposed, and gradually
they returned to their lands in the city. They reopened their shops,
and as long as they attended to their own affairs they were
unmolested by the Japanese. Indeed, they adapted themselves
readily to the new order of things, and drove a lucrative trade with
the invaders”![5] In these respects, too, the voice of Korean history
is a witness with a monotone; as it was in 1592 and earlier, so it has
been down to the present time.
In one other most important respect there has been little variation
in the records of Korean history. Brave, loyal, and good men, when
they have arisen to serve their monarch and their country, have
never been permitted to flourish on Korean soil. The braver, more
loyal and unselfish they have been, the more difficult has the path to
the success of their endeavors been made by a corrupt Court and an
ignorant and ungrateful populace. Almost without exception such
men—rare enough at the best in Korean history—have been
traduced by their enemies and deserted and degraded by their king.
Curing the Hideyoshi invasion the most worthy leader of the Korean
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