UNIT-3

8086 INTERFACING
Concept-I: Semiconductor memories interfacing (RAM,ROM)
Concept-II: Intel 8255 programmable peripheral interface
Concept-III: Interfacing switches and LEDS
Concept-IV: Interfacing seven segment displays
Concept-V: Software and hardware interrupt applications
Concept-VI: Intel 8251 USART architecture and interfacing
Concept-VII: Intel8237a DMA controller
Concept-VIII: Stepper motor
Concept-IX: A/D and D/A converters
Concept-X: Need for 8259 programmable interrupt controller

Unit Outcomes:
At the end of this unit you will learn:
1. Identify the different ways of interfacing memory and I/O with microprocessors.
2. Apply and analyze the interfacing concept of different programmable interfacing
modules with microprocessors for real time applications.

Peripheral Interfacing Introduction:

Any application of a microprocessor based system requires the transfer of data between
external circuitry to the microprocessor and microprocessor to the external circuitry.
User can give information to the microprocessor based system using keyboard and user can
see the result or output information from the microprocessor based system with the help of display
device.
The transfer of data between keyboard and microprocessor, and microprocessor and display
device is called input/output data transfer or I/O data transfer. This data transfer is done with the help
of I/O ports.

What is an Interfacing?
Interface is the path for communication between two components. Interfacing is of two types,
memory interfacing and I/O interfacing.

What is a memory interfacing?

When we are executing any instruction, we need the microprocessor to access the memory for
reading instruction codes and the data stored in the memory. For this, both the memory and the
microprocessor requires some signals to read from and write to registers.
The interfacing process includes some key factors to match with the memory requirements
and microprocessor signals. The interfacing circuit therefore should be designed in such a way that it
matches the memory signal requirements with the signals of the microprocessor.

What is an IO interfacing?
There are various communication devices like the keyboard, mouse, printer, etc. So, we need to interface the
keyboard and other devices with the microprocessor by using latches and buffers. This type of interfacing is
known as I/O interfacing.
Block Diagram of Memory and I/O Interfacing

 Concept-1
SEMICONDUCTOR MEMORIES INTERFACING (RAM,ROM)
Semiconductor memories are of two types, viz. RAM (Random Access Memory) and ROM
(Read Only Memory).
The semiconductor RAMs are of broadly two types-static RAM and dynamic RAM. The
semiconductor memories are organized as two dimensional arrays of memory locations.
For example, 4Kx8 or 4K byte memory contains 4096 locations, where each location contains
8-bit data and only one of the 4096 locations can be selected at a time.
The general procedure of static memory interfacing with 8086 is briefly described as follows:
1. Arrange the available memory chips so as to obtain 16-bit data bus width. The upper 8-bit bank is
called "odd address memory bank" and the lower 8-bit bank is called "even address memory bank".
2. Connect available memory address lines of memory chips with those of the microprocessor and
also connect the memory RD‘ and WR‘ inputs to the corresponding processor control signals. Connect
16-bit data bus of the memory bank with that of the microprocessor 8086.
3. The remaining address lines of the microprocessor, BHE‘ and A0 are used for decoding the required
chip select signals for the odd and even memory banks. The CS‘ of memory is derived from the O/P
of the decoding circuit.
Relation between number of address pins and memory capacity

Problem1: Interfacing of two 4KX4 PROM and two 8KX4 RAM with 8086 CPU, Draw the
memory map and interfacing diagram for it, the RAM address follows the ROM address.
Solution:
Given Data:
Number of PROM chips =02, each one size 4KX4.
(4KX4)*2=8KX4
Number of RAM Chips =02, each one size 8KX4
(8KX4)*2 = 16KX4
PROM Odd Bank Size 4KX4, Even Bank Size 4KX4
RAM Odd Bank Size 8KX4, Even Bank Size 8KX4
After RESET, the IP and CS are initialized to form address FFFF0h. Hence, this address must
lie in the EPROM. The address of RAM may be selected any where in the 1MB address space of 8086,
but we will select the RAM address such that the address map of the system is continuous.
Address Decoding Table
Address A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00

FFFFFH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
EPROM 8K X 8

FE000H 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

FDFFF 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
H
RAM 8K X 8

FC000H 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Let us assume that the latched address, BHE‘ and de-multiplexed data lines are readily available for
interfacing.

1. Total 8K bytes of EPROM need 13 address lines A0-A12 (since 213 = 8K).
2. Address lines A13 - A19 are used for decoding to generate the chip select.
3. The BHE‘ signal goes low when a transfer is at odd address or higher byte of data is to be
accessed.
4. If A0 is 0, i.e., the address is even and is in RAM, then the lower RAM chip is selected
indicating 8-bit transfer at an even address.
 5. If A0 is i.e., the address is odd and is in RAM, the BHE‘ goes low, the upper RAM chip is
selected, further indicating that the 8-bit transfer is at an odd address.
6. If the selected addresses are in ROM, the respective ROM chips are selected.
7. If at a time A0 and BHE‘ both are 0, both the RAM or ROM chips are selected, i.e., the data
transfer is of 16 bits.

Memory Chip Selection Table:

Decoder I/P --> A2 A A0 Selection/
Address/𝐵𝐻𝐸 --> A1 1 𝐵𝐻𝐸 Comment
3 A
0
Word transfer on D0 - D15 0 0 0 Even and odd address in RAM
Byte transfer on D7 - D0 0 0 1 Only even address in RAM
Byte transfer on D8 - D15 0 1 0 Only odd address in RAM
Word transfer on D0 - D15 1 0 0 Even and odd address in RAM
Byte transfer on D7 - D0 1 0 1 Only even address in RAM
Byte transfer on D8 - D15 1 1 0 Only odd address in ROM

Problem2: Design an interface between 8086 CPU and two chips of 16K×8 EPROM and two
chips of 32K×8 RAM. Select the starting address of EPROM suitably. The RAM address must
start at 00000 H.
Solution: The last address in the map of 8086 is FFFFF H. after resetting, the processor starts from
FFFF0 H. hence this address must lie in the address range of EPROM.
It is better not to use a decoder to implement the above map because it is not continuous, i.e. there is
some unused address space between the last RAM address (0FFFF H) and the first EPROM address
(F8000 H). Hence the logic is implemented using logic gates.

Problem3: It is required to interface two chips of 32K×8 ROM and four chips of 32K×8 RAM
with 8086, according to following map. ROM 1 and ROM 2 F0000H - FFFFFH, RAM 1 and
RAM 2 D0000H - DFFFFH, RAM 3 and RAM 4 E0000H - EFFFFH. Show the implementation
of this memory system.
Solution:
INTERFACING I/O PORTS
 I/O ports or Input/output ports are the devices through which the microprocessor
communicates with other devices or external data source/destinations.
 Input activity, as one may expect, is the activity that enables the microprocessor to read data
from external devices, and for example keyboards. These devices are known as input devices
as they feed data into microprocessor system.
 Output activity transfers data from the microprocessor to the external devices, for example
CRT display. These devices which accept the data from a microprocessor system are called
output devices.
 Thus for a microprocessor the input activity is similar to read operation, while the output
activity is similar to write operation.
Steps in Interfacing an I/O Device
 Connect the data bus of the microprocessor system with the data bus of the I/O port.
 Derive a device address pulse by decoding the required address of the device and use it as the
chip select of the device.
 Use a suitable control signal i.e. IOWR‘ and IORD‘ to carry out device operations.
Memory Mapping IO
mapping
1. 20-bit addresses are provided for IO devices. 1. 8-bit or 16-bit address are provided for IO devices
2. The IO ports or peripherals can be treated like
memory locations and so all instructions related 2. Only IN and OUT instructions can be used for data
to memory can be used for data transfer between IO device and the processor.
transfer.
3. In memory mapped ports, the data can be 3. In IO mapped ports, the data transfer can take
moved from any register to port and vice versa only between the accumulator and the ports
4. When memory mapping is used for IO devices, 4. When IO mapping is used for IO devices, then the
the full memory address space cannot be usedfor full address space can be used for addressing
addressing memory. memory.
Problem: Interface an input port 74LS245 to read the status of switches SW1 to SW8. The
switches, when shorted, input a 1 else input a 0 to the microprocessor system. Store the status in
register BL. The address of the port is 0740H.
Solution:

MOV BL, 00 ; Clear BL for status

MOV DX, 0740H ; 16-bit port address in DX
IN AL, DX ; Read port 0740H for switch positions
MOV BL, AL ; Store status of switches from AL into BL
HLT ; Stop

Important questions from concept-1.

1. Define semiconductor memory.

2. Differentiate between static memory and dynamic memory.
3. Interfacing of two 4KX4 PROM and two 8KX4 RAM with 8086 CPU, Draw the memory map
and interfacing diagram for it, the RAM address follows the ROM address.

 Concept-2
INTEL 8255 PROGRAMMABLE PERIPHERAL INTERFACE
The 8255 is a general purpose programmable IO device. It is designed to interface the CPU
with some external devices like ADC, DAC, keyboard etc. We can program the device according to
the given condition. There are three 8-bit bi-directional IO ports, Port-A, Port-B and Port-C. These
ports are assigned as input or output port.
Ports of 8255A
8255A has three ports, i.e., PORT A, PORT B, and PORT C.
 Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
 Port B is similar to PORT A.
 Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7-
PC4) by the control word.
These three ports are further divided into two groups, i.e. Group A includes PORT A and upper PORT
C. Group B includes PORT B and lower PORT C. These two groups can be programmed in three
different modes, i.e. the first mode is named as mode 0, the second mode is named as Mode 1 and the
third mode is named as Mode 2.
Operating Modes
8255A has three different operating modes –
There are two different modes of 8255. These modes are:
 Bit Set Reset (BSR) Mode
 Input/ Output Mode
Bit Set Reset (BSR) Mode
This mode is used to set or reset the bits of the Port-C only. For BSR mode always D7 will be 0. The
control register is looking like this:

Input/ Output Mode

This mode is selected when the D7 bit of the control register is 1.
This mode has also three different modes. These modes are Mode 0 and Mode 1 and Mode 3.

 Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit ports.
Each port can be programmed in either input mode or output mode where outputs are latched
 and inputs are not latched. Ports do not have interrupt capability.
 Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can be configured as
either input or output ports. Each port uses three lines from port C as handshake signals. Inputs
and outputs are latched.
 Mode 2 − In this mode, Port A can be configured as the bidirectional port and Port B either in
Mode 0 or Mode 1. Port A uses five signals from Port C as handshake signals for data transfer.
The remaining three signals from Port C can be used either as simple I/O or as handshake for
port B.

Features of 8255A
The prominent features of 8255A are as follows −
 It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
 Address/data bus must be externally demux'd.
 It is TTL compatible.
 It has improved DC driving capability.
8255 Pin diagram

The signal description of 8255 are briefly presented as follows:

 PA7-PA0: These are eight port A lines that acts as either latched output or buffered input
lines depending upon the control word loaded into the control word register.
 PC7-PC4: Upper nibble of port C lines. They may act as either output latches or input buffers
lines. This port also can be used for generation of handshake lines in mode 1 or mode 2.
 PC3-PC0: These are the lower port C lines, other details are the same as PC7-PC4 lines.
 PB0-PB7: These are the eight port B lines which are used as latched output lines or buffered
input lines in the same way as port A.
 RD: This is the input line driven by the microprocessor and should be low to indicate read
operation to 8255.
 WR: This is an input line driven by the microprocessor. A low on this line indicates write
operation.
 CS: This is a chip select line. If this line goes low, it enables the 8255 to respond to RD and
WR signals, otherwise RD and WR signal are neglected.
 A1-A0: These are the address input lines and are driven by the microprocessor. These lines
A1-A0 with RD, WR and CS from the following operations for 8255. These address lines are
used for addressing any one of the four registers, i.e. three ports and a control word register as
given in table below. In case of 8086 systems, if the 8255 is to be interfaced with lower order
data bus, the A0 and A1 pins of 8255 are connected with A1 and A2 respectively.
 D0-D7: These are the data bus lines those carry data or control word to/from the
microprocessor.
 RESET: A logic high on this line clears the control word register of 8255. All ports are set as
input ports by default after reset.
8255 Architecture
The following figure shows the architecture of 8255A −

It consists of 40 pins and operates in +5V regulated power supply. Port C is further divided
into two 4-bit ports i.e. port C lower and port C upper and port C can work in either BSR (bit set rest)
mode or in mode 0 of input-output mode of 8255. Port B can work in either mode or in mode 1 of
input-output mode. Port A can work either in mode 0, mode 1 or mode 2 of input-output mode.
It has two control groups, control group A and control group B. Control group A consist of
port A and port C upper. Control group B consists of port C lower and port B.
Depending upon the value if CSbar, A1 and A0 we can select different ports in different modes
as input-output function or BSR. This is done by writing a suitable word in control register (control
word D0-D7).

Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data bus. Data
is transmitted or received by the buffer as per the instructions by the CPU. Control words and status
information is also transferred using this bus.
Read/Write Control Logic
This block is responsible for controlling the internal/external transfer of data/control/status word. It
accepts the input from the CPU address and control buses, and in turn issues command to both the
control groups.
CS
It stands for Chip Select. A LOW on this input selects the chip and enables the communication between
the 8255A and the CPU. It is connected to the decoded address, and A0 & A1 are connected to the
microprocessor address lines.
Their result depends on the following conditions −
CS A1 A0 Result

0 0 0 PORT A

0 0 1 PORT B

0 1 0 PORT C

0 1 1 Control
Register

1 X X No Selection

WR
It stands for write. This control signal enables the write operation. When this signal goes low, the
microprocessor writes into a selected I/O port or control register.
RESET
This is an active high signal. It clears the control register and sets all ports in the input mode.
RD
It stands for Read. This control signal enables the Read operation. When the signal is low, the
microprocessor reads the data from the selected I/O port of the 8255.
A0 and A1
These input signals work with RD, WR, and one of the control signal. Following is the table showing
their various signals with their result.
A1 A0 RD WR CS Result

Input Operation
0 0 0 1 0
PORT A → Data Bus

0 1 0 1 0 PORT B → Data Bus

1 0 0 1 0 PORT C → Data Bus

Output Operation
0 0 1 0 0
Data Bus → PORT A
 0 1 1 0 0 Data Bus → PORT A

1 0 1 0 0 Data Bus → PORT B

1 1 1 0 0 Data Bus → PORT D

Important questions from concept-5.

1. Give the control word structure of 8255 PPI
2. Explain the BSR mode of operation of 8255 programmable peripheral interface.
3. What are the main features of 8255? Draw and explain the control word register formats of
8255.
4. Describe the operational modes of 8255 programmable peripheral interface.

 Concept-3
Interfacing switches and LEDS
LED’s interfaced with 8086
Interface an 8255 chip with 8086 to work as an I/O port. Initialize port A as output port, Port
B as I/P port and Port C as O/P port. Port A address should be 0740H. Write an ALP to sense switch
positions SW0–SW7 connected at port B. The sensed pattern is to be displayed on port A, to which 8
LED's are connected, while port C lower displays number of on switches out of the total eight switches
?
 The 8255 is to be interfaced with lower order data bus; i.e. D0-D7. The A0 and A1 pins of
8255 are connected to A1 and A2 pins of the microprocessor respectively. We will use absolute
decoding scheme that uses all the 16 address lines. For deriving the device address pulse. Out of A0
– A15 lines, two address lines A2 and A1 are directly required by 8255 for three port and CWR address
decoding. Hence only A3 to A15 are used for decoding addresses. Circuit diagram, the 8086 is
assumed to be in the maximum mode so that IORD and I OWR are readily available.
Program

MOV DX, 0746H ; Initialize CWR with

MOV AL, 82H ; control word 82H
OUT DX, AL ;
SUB DX, 04 ; Get address of port B in DX
IN AL, DX ; Read port B for switch
SUB DX, 02 ; positions in to AL and get port A address in DX
OUT DX, AL ; Display switch positions on port A
MOV BL, 00H ; Initialize BL for switch count
MOV CH, 08H
YY: ROL AL ; Rotate AL through carry to check,
JNC XX ; whether the switches are on or
INC BL ; off, i.e. either 1 or 0
XX: DEC CH ; Check for next switch. If all
JNZ YY ; switch are checked, the
MOV AL, BL ; number of on switches are
ADD DX, 04 ; in BL. Display it on port C
OUT DX, AL ; lower
HLT
 Concept-4
Interfacing to Seven Segment Displays

 7 segment displays are generally used as numerical indicators and consists of a number of LEDs
arranged in seven segments.
 Any number between 0-9 can be indicated by lighting the appropriate segments.
 The seven segments are labeled as a-g and dot is labeled as h.
 By forward biasing different LED segments, we can display the digits 0 through 9.

Problem: Interface an 8255 with 8086 at 80H as an I/O address of port A. interface five 7 segment displays
with 8255. Write a sequence of instructions to display 1, 2, 3, 4 and 5 over five displays continuously as
per their positions starting with 1 at the least significant position.
Solution: In this scheme. I/O port A is multiplexed to carry data to all the 7-segment displays. The port B
selects one of the displays at a time. The displays used are common anode type.

All these codes, decided above, are stored in a look up table starting at 2000:0000

Interfacing to Seven
Segment Displays
 7 segment displays are generally used as numerical indicators and consists of a number of LEDs
arranged in seven segments.
 Any number between 0-9 can be indicated by lighting the appropriate segments.
 The seven segments are labeled as a-g and dot is labeled as h.
 By forward biasing different LED segments, we can display the digits 0 through 9.

Problem: Interface an 8255 with 8086 at 80H as an I/O address of port A. interface five 7 segment displays
with 8255. Write a sequence of instructions to display 1, 2, 3, 4 and 5 over five displays continuously as per
their positions starting with 1 at the least significant position.
Solution: In this scheme. I/O port A is multiplexed to carry data to all the 7-segment displays. The port B
selects one of the displays at a time. The displays used are common anode type.
All these codes, decided above, are stored in a look up table starting at 2000:0000
Program:
ASSUME CS: CODE
CODE SEGMENT

AGAIN: MOV CL, 05H ; Count for displays

; Initialize data segment
MOV BX, 2000H

MOV DS, BX ; for look up table

MOV CH, 01H ; 1st number to be displayed
MOV AL, 80H ; Load control word in the
OUT 86H, AL ; CWR
MOV DL, 01H ; Enable code for least significant 7-seg display
NXTDGT: MOV BX, 0000H ; Set pointer to look up table
MOV AL, CH ; First no to display Store number to be displayed in AL
XLAT ; Find code from look up table
OUT 80H, AL ; Display the code
MOV AL, DL ; Enable the display
OUT 82H, AL;
ROL DL ; Go for selecting next display
INC CH ; Next number to display
DEC CL
JNZ NXTDGT ; Go for next digit display
JMP AGAIN
CODE ENDS
 MOV DS, BX ; for look up table
MOV CH, 01H ; 1st number to be displayedMOV AL, 80H ; Load control word in
the
OUT 86H, AL ; CWR
MOV DL, 01H ; Enable code for least significant 7-seg display
NXTDGT: MOV BX, 0000H ; Set pointer to look up table
MOV AL, CH ; First no to display Store number to be displayed in ALXLAT ; Find
code from look up table
OUT 80H, AL ; Display the code
MOV AL, DL ; Enable the displayOUT 82H, AL;
ROL DL ; Go for selecting next display
INC CH ; Next number to displayDEC CL
JNZ NXTDGT ; Go for next digit displayJMP AGAIN
CODE ENDS

Important questions from concept-4.

1. Interface an 8255 with 8086 to work as a peripheral interface. Initialize its port A as output
port, port B as input port and port C as output port. Port A address should be 0740H.Writ
a program to sense switch positions SW0 –SW7 connected at port B. The sensed pattern is
to be displayed in port A, to which 8 LEDs are connected, which the port C lower displays
number of ‗ON‘ switches out of the total eight switches.

 Concept-5
Software and hardware interrupt applications
Hardware Interrupt Applications
 Simple Interrupt data input.
 Counting Applications.
 Timing Applications.
Software Interrupt Applications
 To test various ISPs.
 To insert break points in program for debugging.
 To call BIOS procedures in an IBM PC type compute

Important questions from concept-5.

1. Explain the important features of 8259 interrupts controller.

 Concept-6
INTEL 8251 USART ARCHITECTURE AND INTERFACING
USART stands for Universal Synchronous and Asynchronous Receiver Transmitter and
functions as an intermediary that allows serial and parallel communication between the
microprocessor and the peripheral devices.
The microprocessors allow parallel communication. And in parallel communication, the
number of cables required for data transmission is equal to the number of bits to be transmitted
per cycle.
Thus the approach of transmitting data parallelly to long distance is cost-ineffective.
So, to reduce the overall cost of the system despite parallel data communication between the
processor and peripheral devices, the serial transfer of data is permitted.
Hence for this purpose, USART acts as a mediator between the processor and peripheral
devices so, that the parallel data from the processor can be converted into serial data and
efficiently transferred to the peripheral devices.
In a similar way, the serial data from the peripheral devices is converted by the USART into
the parallel form so that it can be accepted by the processor.
Also, it allows both synchronous and asynchronous transmission and reception thus is called
so.

21 Unit-3
ARCHITECTURE

1. Data Bus Buffer: It basically interfaces the 8251 with the internal system buses of the
processor.

The data bus buffer has 8-bit bidirectional data bus that allows the transfer of data bytes, status
or command word between the processor and external devices.

2. Read/Write Control Logic: This functional unit generates a control signal for the operation
of 8251 according to the signal present in the control bus of the processor. Basically, it
performs decoding operation of the control signal produced by the processor, so that
respective operation can be performed by the USART.

The control formats for system operation is stored in control and command word registers
present in the read/write logic unit. The signals handled by the read/write control logic unit
are discussed below:
 CS: It is chip select. A low signal at this pin shows that processor has selected 8251 in
order to communicate with the peripheral devices.

22 Unit-3
  C/D: As the system has control, status and data register. So, when a high signal is
present at this pin then control or status register is addressed. While in case of low
signal data register is addressed.
 RD and WR: Both read and write are active low signal pins. A low signal at RD shows
that the processor is reading the control, status or data bytes from the 8251. While at
WR indicates the write operation over the data bus of 8251.
 CLK and RESET: CLK stands for clock and it produces the internal timing for the
device. While an active high signal at the RESET pin puts the 8251 in the idle mode.
3. Transmit Buffer: This unit is used to change the parallel data received from the CPU into
serial data by inserting the necessary framing information. Once the data is transformed into
serial form, then in order to transmit it to the external devices, it is provided to the TxD pin of
the 8251.

This unit consists of 2 registers. These are as follows:

Buffer register: Basically the data provided by the processor is stored in the buffer register. As
we know that initially, the CPU provides parallel data to 8251. So, the processor loads the
parallel data to the buffer register. Further, this data is fed to the output register.
Output register: The parallel data from the buffer register is fed to the empty output register.
This register changes the 8-bit parallel data into a stream of serial bits. Then further the serial
data is provided at the TxD pin so as to have its transfer to the peripheral device.
As we have already discussed that it performs both synchronous and asynchronous transmission
and reception. Thus in case of asynchronous transmission, start and stop bit is added by the
transmitter in order to notify the external devices about the data transmission.

But in case of synchronous transmission, the clock signal is used thus there exists no need of
adding additional bits expect the parity bit (if required).
4. Transmit Control: As the name of the unit is itself indicating that it is controlling the
transmission action. And it does so by accepting and sending signals both externally and
internally.

The various control signal generated by this unit are as given below:

 TxRDY: It implies transmit ready. This signal is used to notify the processor that the
buffer register of the 8251 is empty and ready to accept the data.
 The status read operation is utilized by the processor in order to check the presence of
the signal.
 TxE: This stands for transmitter empty. It is an active high signal that indicates that the
output buffer is empty and thus data received from the processor can be loaded to it for
conversion.

23 Unit-3
  TxC: It stands for transmitter clock and is an active low pin. It controls the rate of
character transmission by the USART.
 However, 8251 offers programmable clock rate. As by writing appropriate mode word
in the mode set register the clock division can be programmed.
5. Receive Buffer: This unit takes the serial data from the external devices, changes the serial
data into the parallel form so that it can be accepted by the processor. It consists of 2 registers:
receiver input register and buffer register.

When the external device is ready to send the data to the 8251 then it sends a low signal to the
RxD line of the 8251. In asynchronous mode, once 8251 receives a low signal it considers that
signal as start bit of the data.

So, once the start bit is successfully accepted by 8251, then it also receives the whole data bits
in serial form along with parity and stop bits.

Once the data is received by the receiver input register then it converts the data bits in parallel
form and sends it to the receiver buffer register.
In case of the synchronous mode of operation, according to the clock input, the external device
loads the serial data bits in the receiver input register. And on converting the serial data to
parallel format the receiver input register sends the data to the buffer register.

6. Receiver Control

This unit controls the operation of the receiver buffer. It manages the data reception, along with
that it also detects the presence of false start bit, error in parity bit, framing errors etc.

 RxRDY: It stands for receiver ready. When this signal goes high then it indicates that
the receiver buffer register is holding the data and is ready to transfer it to the processor.
Once the CPU reads the data sent by the 8251 then this pin is reset.
 RxC: It stands for receiver clock. This clock signalling controls the rate at which the
8251 receives the data in the synchronous mode of operation. It is provided by the
modem and is equal to the baud rate.
 While asynchronous mode offers the clock rate as 1, 16 or 64 times of the baud rate as
it is programmable.
7. Modem Control: This unit of 8251 holds input and output control signals that simplify the
operation of the whole system. The control circuitry for handing various signals is provided by
the modem control unit. It includes DTS, RTS, DTR and CTS.

These are all active low signals.

24 Unit-3
  DSR: Stands for data set ready and the signal is used to check whether the data set is
ready or not when the processor is in the urge of communication.
 DTR: Implies data terminal ready. An active-low signal at this pin shows that the 8251
is now ready to accept the data from the processor.
 RTS: It stands for the request to send. A low signal shows an assertion for data
transmission.
 CTS: Clear to send. When 8251 receives a low signal at this pin then it clears all the
data present in the modem in order to allow further communication.
This is all about the architectural working of 8251 USART.

Important questions from concept-6.

1. Explain the 8251 USART with neat block diagram and its mode word, command word and
status word.
Draw the internal block diagram of 8251 USART and explain 1 about each block in detail.
Discuss about the pin diagram of 8251 USART (Universal 2 Synchronous Asynchronous Receiver
Transmitter)
Draw and explain the synchronous mode transmitter and 3 receiver data formats of 8251.
Draw and discuss the asynchronous mode transmitter and receiver data formats of 8251.
Discuss in detail about Asynchronous and synchronous serial 3 communication with neat diagrams.

25 Unit-3
  Concept-7
INTEL8237A DMA CONTROLLER
DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest
rate. It allows the device to transfer the data directly to/from memory without any interference of
the CPU.
Using a DMA controller, the device requests the CPU to hold its data, address and control
bus, so the device is free to transfer data directly to/from the memory. The DMA data transfer is
initiated only after receiving HLDA signal from the CPU.
 Initially, when any device has to send data between the device and the memory, the device
has to send DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert
the HLDA.
 Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU
leaves the control over bus and acknowledges the HOLD request through HLDA signal.
 Now the CPU is in HOLD state and the DMA controller has to manage the operations over
buses between the CPU, memory, and I/O devices.
Programmable DMA Controller 8237a

 The 8237 works in two modes i.e., master and slave modes.
 In slave mode, the 8237 functions as an input/output device. In this mode the system buses
arc controlled by microprocessor and hence the microprocessor is connected to the system
bus.
 In master mode 8237 becomes the bus master and hence the microprocessor is isolated
from the system bus. This isolation is done by AEN signal.
 In minimum configuration, 8237 DMA controller is used to transfer the data. The
peripheral chips are interface as normal 10 ports. Figure shows the interfacing of DMA
controller with 8086.
 In minimum mode the HOLD and HLDA signals are used to bus arbitration and in
maximum mode configuration RQ_0/GT_0; and RQ_1/GT_1.
 The 8237 outputs only 16-bit memory address but not the complete 20-bit address of 8086.
To store the remaining four address hits A_16—A_19 a separate page latch is required.
 The 8237 is not compatible with 8086 in its maximum mode configuration. This is because
RQ/GT is not compatible with HRQ and HLDA of 8237.
 So if 8086 is to be interfaced with DMA controller, then 8089 10 processor is required.

26 Unit-3
  The 8089 interfaces to the 8086's local multiplexed buses. It shares the bus buffers and
system controller of the host system. It is compatible with the RQ/GT signals of 8086 and
outputs the complete 20-bit address.

Different data transfer modes of 8237 DMA controller:

The 8237 is in the idle cycle if there is no pending request or the 8237 is waiting for a request from one of
the DMA channels. Once a channel requests a DMA service, the 8237 sends the HOLD request to the CPU
using its HRQ pin. If the CPU acknowledges the hold request on HLDA, the 8237 enters an active cycle.
In the active cycle, the actual data transfer takes place in one of the following transfer modes as is
programmed.

1. Single Transfer Mode: In this mode, the device transfers only one byte per request. The word
count is decremented and the address is decremented or incremented (depending on programming)
after each such transfer. The Terminal Count (TC) state is reached when the count becomes zero.
For each transfer the DREQ must be active until the DACK is activated, in order to get recognized.
After TC the bus will be relinquished for the CPU. For a new DREQ to 8237 it will again activate
the HRQ signal to the CPU and the HLDA signal from the CPU will push the 8237 again into the
single transfer mode. This mode is also called as 'cycle stealing'.

27 Unit-3
2. Block Transfer Mode: In this mode, the 8237 is activated by DREQ to continue the transfer until
a TC is reached, i.e. a block of data is transferred. The transfer cycle may be terminated due to EOP
(either internal or external) which forces Terminal Count (TC). The DREO needs to be activated
only till the DACK signal is activated by the DMA controller. Auto-initialization may be
programmed in this mode.
3. Demand Transfer Mode: In this mode, the device continues transfers until a TC is reached or an
external EOP is detected or the DREQ signal goes inactive. Thus a transfer may exhaust the
capacity of data transfer of an I/O device. After the I/O device is able to catch up the service may
be re-established activating the DREQ signal again. Only the EOP generated by TC or external
EOP can cause the auto-initialization, and only if it is programmed for.
4. Cascade Mode: In this mode, more than one 8237 can be connected together to provide more than
four DMA channels. The HRQ and HLDA signals from additional 8237s are connected with DREQ
and DACK pins of a channel of the host 8237 respectively. The priorities of the DMA requests may
be preserved at each level. The first device is only used for prioritizing the additional devices (slave
8237s), and it does not generate any address or control signal of its own. The host 8237 responds
to DREQ generated by slaves and generates the DACK and the HRQ signals to coordinate all the
slaves. All other outputs of the host 8237 are disabled.
5. Memory to memory Transfer: To perform the transfer of a block of data from one set of memory
address to another one, this transfer mode is used. Programming the corresponding mode bit in the
command word, sets the channel 0 and I to operate as source and destination channels, respectively.
The transfer is initialized by setting the DREQ0 using software commands. The 8237 sends HRQ
(Hold Request) signal to the CPU as usual and when the HLDA signal is activated by the CPU. the
device starts operating in block transfer mode to read the data from memory. The channel 0 current
address register acts as a source pointer. The byte read from the memory is stored in an internal
temporary register of 8237. The channel 1 current address register acts as a destination pointer to
write the data from the temporary register to the destination memory location. The pointers are
automatically incremented or decremented, depending upon the programming. The channel 1 word
count register is used as a counter and is decremented after each transfer. When it reaches zero, a
TC is generated, causing EOP to terminate the service. The 8237 also responds to external EOP
signals to terminate the service. This feature may be used to scan a block of data for a byte. When
a match is found the process may be terminated using the external EOP. Under all these transfer
modes, the 8237 carries out three basic transfers namely, write transfer, read transfer and verify
transfer. In write transfer, the 8237 reads from an I/O device and writes to memory under the control
of IOR and MEMW signals. In read transfer, the 82

28 Unit-3
 6. 37 reads from memory and writes to an I/O device by activating the MEMR and IOW signals. In
verify transfers, the 8237 works in the same way as the read or write transfer but does not generate
any control signal.

Important questions from concept-4.

1. What is DMA? What are its advantages?
2. Explain in detail about the DMA controller with a neat diagram.

 Concept-8
STEPPER MOTOR
A stepper motor is a digital motor. It can be driven by digital signal.

Fig: Stepper Motor Interface

29 Unit-3
Construction & Working:
 Motor shown in the circuit has two phases, with center-tap winding.
 The center taps of these windings are connected to the 12V supply.
 Due to this, motor can be excited by grounding four terminals of the two windings.
 Motor can be rotated in steps by giving proper excitation sequence to these windings.
 The lower nibble of port A of the 8255 is used to generate excitation signals in the proper
sequence.

Fig: Full step excitation sequence

 The given excitation sequence rotates the motor in clockwise direction.
 To rotate motor in anticlockwise direction we have to excite motor in a reverse sequence.
 The excitation sequence for Stepper Motor Interface many change due to change in
winding connections.
 However, it is not desirable to excite both the ends of the same winding simultaneously.
 This cancels the flux and motor winding may damage. To avoid this, digital locking system
must be designed.

Fig: Simple digital Locking system

 In a simple digital locking system, only one output is activated (made low) when properly
excited; otherwise output is disabled (made high).
 In full step sequence excitation ends of the phase are changed in one step. The excitation
sequence given in half step sequence takes two steps to change the excitation ends of the
phase, in each step the motor is rotated by 0.9°.

30 Unit-3
  We know that Stepper Motor Interface is stepped from one position to the next by changing
the currents through the fields in the motor.
 The winding inductance opposes the change in current and this puts limit on the stepping
rate. For higher stepping rates and more torque, it is necessary to use a higher voltage
source and current limiting resistors.
 By adding series resistance, we decrease L/R time constant, which allows the current to
change more rapidly in the windings. There is a power loss across series resistor, but
designer has to compromise between power and speed.
ALP PROGRAM
MODEL SMALL
.STACK 100
.DATA
PORTA EQU FFC0H ; PORTA ADDRESS
PORTB EQU FFC2H ; PORTB ADDRESS
PORTC EQU FFC4H ; PORTC ADDRESS
CWR EQU FFC6H ; CONTROL PORT ADDRESS
PHASEC EQU 03H
PHASEB EQU 06H ; SEQUENCE IN SERIES TO ROTATE MOTOR
PHASED EQU 0CH ; IN CLOCKWISE DIRECTION
PHASEA EQU 09H
.CODE
START:
MOV AL,@DATA
MOV DX,CTL
OUT DX,AL
AGAIN:
MOV AL,PHASEC
MOV DX,PORTC

31 Unit-3
 OUT DX,AL
MOV CX,0FFFFH
UP:
LOOP UP
MOV AL,PHASEB
MOV DX,PORTC
OUT DX,AL
MOV CX,0FFFFH
UP1:
LOOP UP1
MOV AL,PHASED
MOV DX,PORTC
OUT DX,AL
MOV CX,0FFFFH
UP2:
LOOP UP2
MOV AL,PHASEA
MOV DX,PORTC
OUT DX,AL
MOV CX,0FFFFH
UP3:
LOOP UP3
JMP AGAIN ; REPEATE OUTPUT SEQUENCE
INT 03H
END START
Assembly Language Program to rotate Stepper Motor in Anticlockwise direction
MODEL SMALL
.STACK 100
.DATA
PORTA EQU FFC0H ; PORTA ADDRESS
PORTB EQU FFC2H ; PORTB ADDRESS
PORTC EQU FFC4H ; PORTC ADDRESS
CWR EQU FFC6H ; CONTROL PORT ADDRESS
PHASEC EQU 03H
PHASEA EQU 09H ; SEQUENCE IN SERIES TO ROTATE MOTOR
PHASED EQU 0CH ; IN ANTICLOCKWISE DIRECTION
PHASEB EQU 06H
.CODE
START:
MOV AL,@DATA

32 Unit-3
 MOV DX,CTL
OUT DX,AL
AGAIN:
MOV AL,PHASEC
MOV DX,PORTC
OUT DX,AL
MOV CX,0FFFFH
UP:
LOOP UP
MOV AL,PHASEA
MOV DX,PORTC
OUT DX,AL
MOV CX,0FFFFH
UP1:
LOOP UP1
MOV AL,PHASED
MOV DX,PORTC
OUT DX,AL
MOV CX,0FFFFH
UP2:
LOOP UP2
MOV AL,PHASEB
MOV DX,PORTC
OUT DX,AL
MOV CX,0FFFFH
UP3:
LOOP UP3
JMP AGAIN ; REPEATE OUTPUT SEQUENCE
INT 03H
END START

Important questions from concept-8.

1. Draw the schematic diagram of stepper motor interfacing to 8086. Write an assembly
language program to rotate shaft of a 4-phase, 200 teeth stepper motor i) 10 rotations in
clockwise ii)5 rotations in anticlockwise iii) Exactly by an angle of 27o in clockwise.
April/May‘19.
2. Draw a typical stepper motor interface with 8255 and explain its functioning.

33 Unit-3
  Concept-9
A/D & D/A Converters
Why Analog to Digital?
Signals in the real world are analog: light, sound, temperature, pressure, acceleration or other
phenomenon. So, real-world signals must be converted into digital, using a circuit called ADC
(Analog-to-Digital Converter), before they can be manipulated by digital equipment.
 When you scan a picture with a scanner what the scanner is doing is an analog-to-digital
conversion: it is taking the analog information provided by the picture (light) and
converting into digital.
 When you record your voice on your computer, you are using an analog-to-digital
converter to convert your voice, which is analog, into digital information.
 When an audio CD is recorded at a studio, once again analog-to-digital is taking place,
converting sounds into digital numbers that will be stored on the disc.
 Whenever we need the analog signal back, the opposite conversion – digital-to-analog,
which is done by a circuit called DAC, Digital-to-Analog Converter – is needed.
 When you play an audio CD, what the CD player is doing is reading digital information
stored on the disc and converting it back to analog so you can hear the audio.

 ADC 0808 is an 8 channel, 8 bit ADC. It can convert an analog voltage input into an 8 bit
digital data output.
 To select an input out of 8 options, there are three select lines (C, B and A). We put a
channel number on these lines (0…7) and latch it using ALE. SOC signal is given to
indicate start of conversion.
 The channel voltage is internally sampled and held into a capacitor. Conversion takes place
internally using ―Successive Approximations Algorithm‖.
 Reference voltage for conversion is provided using +Vref and –Vref. The clock supply
needed for conversion is given through CLK (typically ~ 1MHz).
 The end of conversion is indicated by the ADC using EOC signal. Now we give the OE
signal enabling 8-bit data output from the ADC to 8255.

34 Unit-3
 This data from 8255 is now transferred to the microprocessor. The process is repeated for
subsequent channels, by changing the channel number. ADCs have a vast use in the modern
electronic world for Data Acquisition Systems. They can be used for temperature sensing,
voice recording, speed sensing etc.

35 Unit-3
Features
- Easy interface to all microprocessors
- Operates ratio metrically or with 5 VDC or analog span adjusted voltage reference
- No zero or full-scale adjust required
- 8-channel multiplexer with address logic
- 0V to 5V input range with single 5V power supply
- Outputs meet TTL voltage level specifications
- ADC0808 equivalent to MM74C949
- ADC0809 equivalent to MM74C949-1

36 Unit-3
DAC
A Digital to Analog Converter (DAC) converts a digital input signal into an analog output
signal. The digital signal is represented with a binary code, which is a combination of bits 0 and
1.

Pin Name Description

1 NC No connection
2 GND Ground
3 VEE Negative power supply
4 IO Output signal pin
5 A1 Digital input bit 1 (Most Significant Bit)
6 A2 Digital input bit 2
7 A3 Digital input bit 3
8 A4 Digital input bit 4
9 A5 Digital input bit 5
10 A6 Digital input bit 6
11 A7 Digital input bit 7
12 A8 Digital input bit 8 (Least Significant Bit)
13 VCC Positive power supply
14 VREF+ Positive reference voltage
15 VREF- Negative reference voltage
16 COMPENSATION Compensation capacitor pin

37 Unit-3
  DAC 0808 is an 8 bit Digital to Analog Converter. It can convert an 8 bit digital data input
into an analog voltage output.
 Reference voltage for conversion is provided using +Vref and –Vref. The output can be
amplified (optional) using an op-amp.
 DACs are used in various applications such as Waveform generation, PWM, Motor control
Applications, DSP etc. Here we connect the output to a display device like a CRO.
 By simple programming we can generate several types of wave forms like Ramp, Saw-
tooth, Triangular waveform etc.

Features:

 8 bit parallel digital data input

 Fast settling time (typical value): 150 ns
 Relative accuracy at ±0.19% maximum error
 Full scale current match: ±1 LSB

38 Unit-3
  Non-inverting digital inputs are TTL and CMOS compatible
 High speed multiplying input slew rate: 8 mA/μs
 Power supply voltage range: ±4.5V to ±18V
 Low power consumption: 33 mW@ ±5V
 Maximum Power dissipation: 1000 mW
 Operating temperature range: 0ºC to +75ºC

Applications

 Analog and digital circuits

 Electrical measurements
 Audio conversion
 Hobbyist applications

Assembly language program in 8086 to generate a symmetrical square wave with 1KHz
frequency? Give the necessary circuit set up with a DAC.
Assume selected counter is Counter-1, Mode for Square wave is Mode-3, Address for Counter 1
is 82H
Calculation of CWR:

Interface ADC 0808 with 8086 using 8255 ports. Use port A of 8255 for transferring digital data
output of ADC to the CPU and port C for control signals. Assume that an analog input is present
at I/P2 of the ADC and a clock input of suitable frequency in available for ADC. Draw the
schematic and write required ALP.

39 Unit-3
Important questions from concept-9.
1. Interface ADC 0808 with 8086 using 8255 ports. Use port A of 8255 for transferring digital
data output of ADC to the CPU and port C for control signals. Assume that an analog input
is present at I/P2 of the ADC and a clock input of suitable frequency in available for ADC.
Draw the schematic and write required ALP.
2. Discuss the applications of A-to-D and D-to-A converters.
3. Write an assembly language program in 8086 to generate a symmetrical square wave with
1KHz frequency? Give the necessary circuit set up with a DAC.

40 Unit-3
  Concept-10
INTEL 8259 PROGRAMMABLE INTERRUPT CONTROLLER
The 8259 is known as the Programmable Interrupt Controller (PIC) microprocessor. In
8086 there are two hardware interrupts respectively. But adding 8259, we can increase the interrupt
handling capability. This chip combines the multi-interrupt input source to single interrupt output.
This provides 8-interrupts from IR0 to IR7.

Features
 This chip is designed for 8085 and 8086.
 It can be programmed either in edge triggered, or in level triggered mode
 We can mask individual bits of Interrupt Request Register.
 By cascading 8259 chips, we can increase interrupts up to 64 interrupt lines
 Clock cycle is not needed.
The pin level diagram and functional pin diagram is like below -

41 Unit-3
dlock diagram -

Working

42 Unit-3
 Block Description

This block is used to communicate between 8259 and

8085/8086 by acting as buffer. It takes the control word from
8085/8086 and send it to the 8259. It transfers the opcode of the
Data Bus Buffer
selected interrupts and address of ISR to the other connected
microprocessor. It can send maximum 8-bit at a time.

This block works when the value of pin CS is 0. This block is

R/W Control Logic used to flow the data depending upon the inputs of RD and WR.
These are active low pins for read and write.
It controls the functionality of each block. It has pin called
INTR. This is connected to other microprocessors for taking the
interrupt request. The INT pin is used to give the output. If 8259
Control Logic is enabled, and also the interrupt flags of other microprocessors
are high then this causes the value of the output INT pin high,
and in this way this chip can responds requests made by other
microprocessors.

Interrupt Request It stores all interrupt level that are requesting for interrupt
Register service.

Interrupt Service It stores interrupt level that are currently being execute.
Register

Interrupt Mask It stores interrupt level that will be masked, by storing the
Register masking bits of interrupt level.

It checks all three registers, and set the priority of the interrupts.
Interrupt with the highest priority is set in the ISR register. It
Priority Resolver
also reset the interrupt level which is already been serviced in
the IRR.
To increase number of interrupt pin, we can cascade more
number of pins, by using cascade buffer. When we are going to
Cascade Buffer
increase the interrupt capability, CSA lines are used to control
multiple interrupts.

Interrupt Sequence in an 8086 System

The interrupt sequence in an 8086-8259A system is described as follows:
1. One or more of the interrupt request lines (IR0-IR7) are raised high, setting the corresponding
IRR bits.

43 Unit-3
2. The priority resolver checks three registers: the IRR for interrupt requests, the IMR for masking
bits and the ISR for the interrupt request being served. It resolves priority and sets the INT high
when appropriate.
3. The CPU acknowledges the INT and responds with INTA pulse.
4. Upon receiving an INTA from the CPU, the highest priority ISR bit is set and the corresponding
IRR bit is reset. The 8259A does not drive data bus during this cycle.
5. A selection of priority modes is available to the programmer so that the manner in which requests
are processed by the 8259A can be configured to match his system requirements. The priority
modes can be changed dynamically at any time during the main program.
6. The 8086 will initiate a second INTA pulse. During this pulse 8259A releases interrupt type
onto the DATA bus where it is read by CPU.
7. This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the end of the second
INTA pulse. Otherwise the ISR bit remains set until an appropriate EOI command is issued at
the end of interrupt subroutine.
Programming the 8259A:
The 8259A requires two types of command words.
1. Initialization Command Words (ICWs)
2. Operational Command Words (OCWs)
The 8259A can be initialized with four ICWs; the first two are compulsory and the other
two are optional based on the modes being used.
After initialization, the 8259A can be set up to operate in various modes by using three
different OCWs .
Flow Chart:

44 Unit-3
Initialization Command Word 1 (ICW1):

A write command issued to 8259A with A0=0 and D4=1 is interpreted as ICW1, which starts the
initialization sequence.
It specifies
1. Single or multiple 8259As in the system.
2. 4 or 8 bit interval between the interrupt vector locations.
3. The address bit A7-A5 to CALL instruction.
4. Edge triggered or level triggered interrupts.
5. ICW4 is needed or not.

Initialization Command Word 2 (ICW2):

A write command following ICW1, with A0=1 is interpreted as ICW2. This is used to load high
order byte of the interrupt vector address of all interrupts.
Initialization Command Word 3 (ICW3):
 ICW3 is required only if there is more than one 8259A in the system and if they are
cascaded. An ICW3 operation loads a slave register in the 8259.
 For master each bit in ICW3 is used whether it has a slave 8259 attached to it on its
corresponding IR input.
 For slave, bits D0-D2 of ICW3 are used to assign a slave identification code to the 8259A

45 Unit-3
Initialization Command Word 4 (ICW4):
It is loaded only if the D0 bit of ICW1 is set.

It specifies
1. Whether to use special fully nested mode or non special fully nested mode.
2. Whether to use buffered mode or non buffered mode.
3. Whether to use automatic EOI or normal EOI.
4. CPU used 8086/8088
 After initialization the 8259A is ready to process the interrupt request. However during
operation it might be necessary to change the mode of processing the interrupts.
 Operation Command Words (OCWs) are used for this purpose.
Operation Command Word 1 (OCW1):
 A write command to the 8259 with A0=1 (after ICW2) is interpreted as OCW1. OCW1 is
used for enabling or disabling the recognition of specific interrupt requests by
programming the IMR.

46 Unit-3
Operation Command Word 2 (OCW2):
 A write command to the 8259 with A0=1 and D4D3=00 is interpreted as OCW2.

Operation Command Word 3 (OCW3):

 OCW3 is used to read the status of registers, and to set or reset the Special Mask and
Polled modes.

47 Unit-3