B.V.

M Engineering College
(AN AUTONOMOUS INSTITUTE) ELECTRONICS
ENGINEERING DEPARTMENT

ACADEMIC YEAR: AY 2021-22

SUBJECT: 3EL42: DSD
Institute Vision: “Produce globally employable innovative engineers with core values”

Institute Mission:

1. Re-engineering curricula to meet global employment requirements

2. Promote innovative Practices at all levels

3. Imbibe core values

4. Reform policies, systems and processes at all levels

5. Develop faculty and staff members to meet the challenges

Department: Electronics Engineering

Vision: “Produce globally employable, innovative Electronics engineers with core values”

Mission:

1. Promote Innovative Practices to strengthen teaching and learning process in

electronics engineering
2. Develop faculty and staff to meet challenges in Electronics engineering
3. Adapt Engineering curricula to meet global requirements for Electronics
engineering program me.
4. Reform policies, systems and processes at all levels
5. Imbibe core Values.
Program Educational Objectives (PEOs):

1. Study and analysis of Electronics engineering systems.

2. Adapt state-of-art developments in Electronics engineering and eco friendly
technologies.

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 Report
On

Alarm Clock
Mini Project
(3EL42)
SUBMITTED BY:
Deep Chauahn & Jayraj Patoriya (ID No.21EL040 & 21EL065)
IN FULFILLMENT FOR THE AWARD OF THE DEGREE OF
BECHELOR OF TECHNOLOGY
IN
Electronics Engineering

BIRLA VISHWAKARMA MAHAVIDALAYA

Engineering Collage, Vallabh Vidyanagar, 388120

[An Autonomous Institution] Electronics Department

Lab Teacher Course Coordinator & Guide

Prof. Chintan Patel Prof. Chintan Patel

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 ELECTRONICS ENGG DEPARTMENT

BIRLA VISHWAKARMA MAHAVIDYALAYA ENGG COLLEGE V V NAGAR

CERTIFICATE

This is to certify that MR. Deep Chauhan & Jayraj Patoriya ID No. 21EL040 &
21EL065 of B.Tech (Electronics Engineering) SEM-V has satisfactorily completed the
term work of the subject DSD (3EL42) prescribed by BVM an Autonomous Institution
during the Academic Year 2021-2022.

Lab Teacher Course Coordinator & Guide

Prof. Chintan Patel Prof. Chintan Patel

~3~
 Acknowledgment

Firstly, we offer thanks to our guide and Course coordinator Prof. CHINTAN
PATEL Electronics Department, Birla Vishvakarma Mahavidyalaya, our Lab
teacher: Prof. CHINTAN PATEL Lecturer, Birla Vishvakarma Mahavidyalaya,
Electronics Department, for their invaluable support, guidance and advice
given throughout this semester and for helping to establish our direction.

We are also thankful for all our other faculties for their consistence support
and guidance.

~4~
 Alarm clock
Verilog code for an alarm clock on FPGA is presented in this project. The Verilog code is
fully synthesizable for FPGA implementation.

The simple alarm clock is shown in the following figure. The alarm clock outputs a real-
time clock with a 24-hour format and also provides an alarm feature. Users also can set the
clock time through switches.

Block Diagram

~5~
Verilog code:

module Aclock(
input reset,
input clk,
input [1:0] H_in1,
input [3:0] H_in0,
input [3:0] M_in1,
input [3:0] M_in0,
input LD_time,
input LD_alarm,
input STOP_al,
input AL_ON,
output reg Alarm,
output [1:0] H_out1,
output [3:0] H_out0,
output [3:0] M_out1,
output [3:0] M_out0,
output [3:0] S_out1,
output [3:0] S_out0);

reg clk_1s;
reg [3:0] tmp_1s;
reg [5:0] tmp_hour, tmp_minute, tmp_second;
reg [1:0] c_hour1,a_hour1;
reg [3:0] c_hour0,a_hour0;

~6~
reg [3:0] c_min1,a_min1;
reg [3:0] c_min0,a_min0;
reg [3:0] c_sec1,a_sec1;
reg [3:0] c_sec0,a_sec0;

function [3:0] mod_10;

input [5:0] number;
begin
mod_10 = (number >=50) ? 5 : ((number >= 40)? 4 :((number >= 30)? 3 :((number >= 20)?
2 :((number >= 10)? 1 :0))));
end
endfunction

always @(posedge clk_1s or posedge reset )

begin
if(reset) begin
a_hour1 <= 2'b00;
a_hour0 <= 4'b0000;
a_min1 <= 4'b0000;
a_min0 <= 4'b0000;
a_sec1 <= 4'b0000;
a_sec0 <= 4'b0000;
tmp_hour <= H_in1*10 + H_in0;
tmp_minute <= M_in1*10 + M_in0;
tmp_second <= 0;
end
else begin
if(LD_alarm) begin
a_hour1 <= H_in1;

~7~
a_hour0 <= H_in0;
a_min1 <= M_in1;
a_min0 <= M_in0;
a_sec1 <= 4'b0000;
a_sec0 <= 4'b0000;
end
if(LD_time) begin
tmp_hour <= H_in1*10 + H_in0;
tmp_minute <= M_in1*10 + M_in0;
tmp_second <= 0;
end
else begin
tmp_second <= tmp_second + 1;
if(tmp_second >=59) begin
tmp_minute <= tmp_minute + 1;
tmp_second <= 0;
if(tmp_minute >=59) begin
tmp_minute <= 0;
tmp_hour <= tmp_hour + 1;
if(tmp_hour >= 24) begin
tmp_hour <= 0;
end
end
end

end
end
end

~8~
always @(posedge clk or posedge reset)
begin
if(reset)
begin
tmp_1s <= 0;
clk_1s <= 0;
end
else begin
tmp_1s <= tmp_1s + 1;
if(tmp_1s <= 5)
clk_1s <= 0;
else if (tmp_1s >= 10) begin
clk_1s <= 1;
tmp_1s <= 1;
end
else
clk_1s <= 1;
end
end

always @(*) begin

if(tmp_hour>=20) begin
c_hour1 = 2;
end
else begin
if(tmp_hour >=10)

~9~
c_hour1 = 1;
else
c_hour1 = 0;
end
c_hour0 = tmp_hour - c_hour1*10;
c_min1 = mod_10(tmp_minute);
c_min0 = tmp_minute - c_min1*10;
c_sec1 = mod_10(tmp_second);
c_sec0 = tmp_second - c_sec1*10;
end

always @(posedge clk_1s or posedge reset)

begin
if(reset)
Alarm <=0;
else begin
if({a_hour1,a_hour0,a_min1,a_min0}=={c_hour1,c_hour0,c_min1,c_min0})
begin
if(AL_ON) Alarm <= 1;
end
if(STOP_al) Alarm <=0;

end
end

assign H_out1 = c_hour1;

~ 10 ~
assign H_out0 = c_hour0;
assign M_out1 = c_min1;
assign M_out0 = c_min0;
assign S_out1 = c_sec1;
assign S_out0 = c_sec0;

endmodule

Testbench Code:

module Testbench;

reg reset;
reg clk;
reg [1:0] H_in1;
reg [3:0] H_in0;
reg [3:0] M_in1;
reg [3:0] M_in0;
reg LD_time;
reg LD_alarm;
reg STOP_al;
reg AL_ON;

// Outputs

~ 11 ~
wire Alarm;
wire [1:0] H_out1;
wire [3:0] H_out0;
wire [3:0] M_out1;
wire [3:0] M_out0;
wire [3:0] S_out1;
wire [3:0] S_out0;

Aclock uut (
.reset(reset),
.clk(clk),
.H_in1(H_in1),
.H_in0(H_in0),
.M_in1(M_in1),
.M_in0(M_in0),
.LD_time(LD_time),
.LD_alarm(LD_alarm),
.STOP_al(STOP_al),
.AL_ON(AL_ON),
.Alarm(Alarm),
.H_out1(H_out1),
.H_out0(H_out0),
.M_out1(M_out1),
.M_out0(M_out0),
.S_out1(S_out1),
.S_out0(S_out0)
);

~ 12 ~
initial begin
clk = 0;
forever #50000000 clk = ~clk;
end
initial begin
// Initialize Inputs
reset = 1;
H_in1 = 1;
H_in0 = 0;
M_in1 = 1;
M_in0 = 9;
LD_time = 0;
LD_alarm = 0;
STOP_al = 0;
AL_ON = 0;

#1000000000;
reset = 0;
H_in1 = 1;
H_in0 = 0;
M_in1 = 2;
M_in0 = 0;
LD_time = 0;
LD_alarm = 1;
STOP_al = 0;
AL_ON = 1;

~ 13 ~
#1000000000;
reset = 0;
H_in1 = 1;
H_in0 = 0;
M_in1 = 2;
M_in0 = 0;
LD_time = 0;
LD_alarm = 0;
STOP_al = 0;
AL_ON = 1;

wait(Alarm);
#1000000000;
#1000000000;
#1000000000;
#1000000000;
#1000000000;
#1000000000;
STOP_al = 1;

end
endmodule

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Schematic

Wave form

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Synthesized design

Implementation design

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 POWER REPORT:

CONCLUSION :
In this Project we learned about Verilog and using this we make one
project of Alarm Clock we learned a lot of things and gained
knowledge and try different things. And it was a great hands-on
experience.

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