electronics

Article
A ±0.15 ◦ C (3σ) Inaccuracy CMOS Smart Temperature Sensor
from −40 ◦ C to 125 ◦ C with a 10 ms Conversion Time-Leveraging
an Adaptative Decimation Filter in 65 nm CMOS Technology
Fábio Passos 1,2,3, *, Gabriel Santos 3 and Marcelino Bicho dos Santos 1,2,3

1 INESC-ID, 1000-029 Lisbon, Portugal

2 Instituto Superior Técnico, Universidade de Lisboa, 1000-029 Lisbon, Portugal
3 Silicon Gate, 1000-029 Lisbon, Portugal
* Correspondence: [email protected]

Abstract: This paper presents the design and implementation of a highly accurate smart temperature
sensor designed in 65 nm CMOS technology. The sensor exhibits a ±0.15 ◦ C (3σ) error across a
wide temperature range from −40 ◦ C to 125 ◦ C, catering to diverse application needs. Leveraging
advanced CMOS technology, the sensor employs an adaptive decimation filter that allows us to
control the conversion time, ensuring that the accuracy of the conversion is maintained even in
challenging conditions. The proposed sensor architecture integrates advanced techniques for tem-
perature sensing for improved accuracy and reliability. Through meticulous circuit design and the
usage of dynamic element matching, chopping, and calibration/trimming, the sensor demonstrates
Citation: Passos, F.; Santos, G.; dos
exceptional performance characteristics, making it suitable for various industrial, automotive, and
Santos, M.B. A ±0.15 ◦ C (3σ)
consumer electronics applications demanding high precision temperature monitoring.
Inaccuracy CMOS Smart Temperature
Sensor from −40 ◦ C to 125 ◦ C with a
10 ms Conversion Time-Leveraging an
Keywords: adaptative decimation filter; chopping; dynamic element matching; smart temperature
Adaptative Decimation Filter in 65 nm sensor; sigma–delta modulator
CMOS Technology. Electronics 2024,
13, 2823. https://doi.org/10.3390/
electronics13142823
1. Introduction
Academic Editor: Francesco Driussi
In modern electronics, temperature sensing is a fundamental aspect that underpins
Received: 28 May 2024 the performance, reliability, and safety of numerous devices and systems. From industrial
Revised: 10 July 2024
process control to microprocessors and consumer electronics, the accurate measurement
Accepted: 16 July 2024
of temperature is essential for maintaining optimal operation and preventing catastrophic
Published: 18 July 2024
failures [1].
Correction Statement: This article Smart temperature sensors are essential in the design and operation of Application-
has been republished with a minor Specific Integrated Circuits (ASICs) due to their ability to provide precise information to
change. The change does not affect other acting circuits which can then perform thermal management. These sensors help
the scientific content of the article and maintain optimal operating temperatures, which is crucial for the performance and reliabil-
further details are available within the ity of ASICs. Overheating can lead to thermal throttling, reduced efficiency, and potentially
backmatter of the website version of permanent damage to the circuit. By continuously monitoring the temperature, smart
this article. sensors allow for dynamic adjustments, such as modulating clock speeds or power delivery,
to prevent overheating. This ensures that ASICs operate within their specified temperature
ranges, enhancing their longevity and stability. Thus, smart temperature sensors contribute
significantly to both the quality and reliability of ASICs throughout their lifecycle. As
Copyright: © 2024 by the authors.
technological advancements continue to push the boundaries of miniaturization and inte-
Licensee MDPI, Basel, Switzerland.
This article is an open access article
gration, the demand for highly precise and compact temperature sensors has intensified. In
distributed under the terms and
response to this need, researchers and engineers have endeavored to develop innovative
conditions of the Creative Commons solutions capable of delivering exceptional accuracy, reliability, and efficiency [2–5].
Attribution (CC BY) license (https:// As previously said, there is the need for robust temperature sensing solutions in a
creativecommons.org/licenses/by/ wide range of applications. Accurate temperature monitoring is essential for optimizing the
4.0/). performance and longevity of electronic equipment, ensuring compliance with regulatory

Electronics 2024, 13, 2823. https://doi.org/10.3390/electronics13142823 https://www.mdpi.com/journal/electronics

Electronics 2024, 13, 2823 2 of 16

standards, and enhancing user experience in consumer products. One of the critical
challenges in temperature sensing is achieving high accuracy across a broad range of
operating conditions. Traditional temperature sensors often struggle to maintain precision
in extreme environments or exhibit significant errors due to variations in process, voltage,
and temperature (PVT) [6]. Moreover, the quest for low-area and low-power integrated
circuits (ICs) adds further complexity to sensor design, necessitating novel architectures and
techniques to address these constraints effectively. Two of the most important performances
of a smart temperature sensor are accuracy and conversion speed. In smart temperature
sensors, there is often a trade-off between these two performances. High accuracy means
the sensor can measure temperature very precisely, which is essential for applications
requiring exact temperature control, such as in medical or scientific equipment. However,
achieving this high accuracy typically requires more time for each measurement, as the
sensor may need to average multiple readings or perform complex calibrations to reduce
noise and enhance precision.
On the other hand, fast conversion speed allows the sensor to provide real-time tem-
perature readings, which is crucial for dynamic systems like HVAC controls or automotive
applications. However, increasing the speed of conversion can introduce more noise and
reduce the accuracy of the measurement. Manufacturers of smart temperature sensors often
need to balance these two factors, optimizing the design to meet the specific needs of the
application, whether it prioritizes rapid updates or precise measurements. The objective of
this work is to achieve a very high accuracy but with smaller conversion times than typical
smart sensors with the same accuracy [7,8].
In this context, the present paper introduces an advancement in temperature sensing
technology by proposing a ±0.15 ◦ C (considering 3σ) error CMOS smart temperature sensor
across a broad range of temperatures (−40 ◦ C to 125 ◦ C) and implemented in a 65 nm
CMOS technology. This sensor leverages dynamic element matching (DEM) techniques
and chopping in order to mitigate the effects of noise, nonlinearity, and process variations
inherent in CMOS-based sensors and obtain such a high accuracy. Since all the primary
sources of error are reduced to a 0.01 ◦ C level, in this temperature sensor, the primary
source of error stems from the variability in the characteristics of the bipolar transistors [2].
Hence, calibration at a single temperature proves adequate to identify and rectify this error
through trimming. Given the essentially unidimensional nature of this variability, the
correction remains effective across the entire operational spectrum.
Central to the functionality of the smart temperature sensor is the sigma–delta (Σ∆)
analog-to-digital converter (ADC), which operates differently from traditional converters.
Instead of directly converting the incoming analog signal into a digital sample of n-bit
precision at the Nyquist rate, they employ oversampling. This means the analog signal
is sampled at a much higher rate, denoted as fN, where fN << fS (with oversample rates
like 16, 32, 64, or 128 being common). During oversampling, the ADC captures the analog
signal at a lower precision (coarser quantization), often effectively functioning as a 1-bit
ADC (as in our case). The output of the modulator or 1-bit ADC is a bitstream (bs). The
density of the ones in this stream correlates with the magnitude of the sine-wave input.
The 1-bit ADC stream undergoes digital filtering to derive an n-bit representation of the
analog input. Put simply, the 1-bit ADC stream is summed over N sampling cycles and
then divided by N. This process produces a decimated value, representing the average
value of the bitstream from the modulator [3]. The circuit that performs such decimated
value is called a decimator filter. The output of the decimator can then be converted to
temperature; hence, the Σ∆ ADC (modulator and the decimator) operates as a voltage to
temperature converter.
The Σ∆ modulator needs to feed several bits to the decimator filter in order to achieve
sufficient resolution. This will therefore increase the number of cycles that the Σ∆ needs to
run in order to achieve a good temperature resolution and therefore accuracy. This time
is known as conversion time. In order for obtain fast conversion times, higher sampling
rates can be used, second-order Σ∆s [4], or higher order decimation filters can be used [5].
 and area. Hence, the relationships among complexity, power consumption, and a
difficult to manage, and novel approaches must be followed in order to minimize
vious parameters. However, this is never trivial in circuit design.
Electronics 2024, 13, 2823
Hence, in order to improve the conversion speed while keeping the 3 ofarea,
16 pow
sumption, and design complexity to a minimum, in our work, we have developed
adaptative decimation filter which is able to dynamically adjust the number of cycl
However, each of those solutions has its cost in design complexity, power consumption
for
and the
area.decimation in order to
Hence, the relationships amongkeepcomplexity,
topmost poweraccuracy withoutand
consumption, resorting
area are to extr
power
difficultor
to increasing
manage, and the design
novel complexity
approaches must of be the analog
followed circuits,
in order like using
to minimize alla highe
previous parameters. However, this is never trivial in circuit design.
Σ∆. This adaptive feature distinguishes the proposed sensor from conventional te
Hence, in order to improve the conversion speed while keeping the area, power con-
ture sensors, which often rely on fixed or predetermined filtering strategies that ma
sumption, and design complexity to a minimum, in our work, we have developed a novel
promise
adaptativeaccuracy
decimationor efficiency
filter in dynamic
which is able environments.
to dynamically This adaptative
adjust the number of cycles useddecima
ter willdecimation
for the be explainedin orderintodetail in Section
keep topmost 3. without resorting to extra area, power
accuracy
or increasing the designofcomplexity
The remainder this paper of is
theorganized
analog circuits, like using
as follows: a higher-order
Section Σ∆. the b
2 discusses
This adaptive feature distinguishes the proposed sensor from conventional
smart temperature basics. Section 3 presents the implementation details of the pr temperature
sensors, which often rely on fixed or predetermined filtering strategies that may compro-
smart temperature
mise accuracy sensor,
or efficiency and Section
in dynamic 4 showcases
environments. the performance
This adaptative decimation characterist
filter
capabilities
will be explainedof the smart
in detail in temperature
Section 3. sensor through comprehensive pre- and post
simulations. Finally,
The remainder Section
of this paper is5 organized
draws the as conclusions.
follows: Section 2 discusses the basics of
smart temperature basics. Section 3 presents the implementation details of the proposed
smart temperature sensor, and Section 4 showcases the performance characteristics and
2. Smart Temperature Sensor Basics
capabilities of the smart temperature sensor through comprehensive pre- and post-layout
To obtain
simulations. a digital
Finally, Section 5temperature reading, a comparison measurement
draws the conclusions. must
formed, comparing a temperature-dependent signal with a reference signal. Al
2. Smart Temperature Sensor Basics
most devices exhibit temperature-dependent characteristics and could ideally be u
To obtain a digital temperature reading, a comparison measurement must be per-
such
formed,purpose,
comparing bipolar transistors are especially
a temperature-dependent signal with awell-suited for Although
reference signal. that [6]. most
They can p
both
devicesa voltage proportional to absolute
exhibit temperature-dependent temperature
characteristics (PTAT)
and could ideallyand a temperature-ind
be used for such
ent bandgap
purpose, reference
bipolar transistorsvoltage. In CMOS
are especially technology,
well-suited substrate
for that [6]. They canbipolar
produce transistors
both
a voltage proportional
fil this role effectively. to absolute temperature (PTAT) and a temperature-independent
bandgap reference voltage. In CMOS technology, substrate bipolar transistors can fulfil
Figure 1 depicts the operational concept of a temperature sensor. It employs
this role effectively.
ode-connected substrate
Figure 1 depicts PNP transistors
the operational concept of atotemperature
generate two voltages,
sensor. VBEtwo
It employs and ∆VBE
voltages are then
diode-connected combined
substrate to createtothe
PNP transistors necessary
generate PTATVand
two voltages, BE and ∆VBE . These
reference voltages [
voltages are then
sequently, thesecombined
voltagesto create the necessaryinto
are converted PTATaand reference
digital voltages [2].reading
temperature Subse- thro
quently, these voltages are converted into a digital temperature reading through an ADC
ADC thus generating a temperature reading in a digital format DOUT.
thus generating a temperature reading in a digital format DOUT .

Figure 1.1.Operating
Figure Operatingprinciple of theof
principle temperature.
the temperature.
The base-emitter voltage of a bipolar transistor in its forward-active region can be
The by
described base-emitter
the followingvoltage of alogarithmic
well-known bipolar transistor
equation: in its forward-active region
described by the following well-knownlogarithmic  equation:
kT IBI AS ( T )
VBE ( T ) = ln (1)
q IS ( T )

where k, is the Boltzmann constant, q is the electron charge, T is the absolute temperature,
IS the transistor saturation current, and IBIAS is its collector current, determined by a bias
circuit [2]. It is well known that the bipolar transistor saturation current highly depends on
 on the temperature, hence the base-emitter voltage exhibits a negative temperature
ficient of around −2 mV/°C. And it can also be shown that for two bipolar transisto
erating with a collector current ratio of 1:p, the ∆VBE can be given by the following:
Electronics 2024, 13, 2823
Δ𝑉 𝑇 = ln p 4 of 16

Hence, ∆VBE only depends on the ratio of currents p, making it an accurate me

the temperature, hence the base-emitter voltage exhibits a negative temperature coefficient
ofoftemperature. A larger current ratio p results in a larger ∆VBE, but the designer
around −2 mV/◦ C. And it can also be shown that for two bipolar transistors operating
ensure that thecurrent
with a collector two transistors remain
ratio of 1:p, the ∆VBE can in the same
be given by operating region [1]. In this w
the following:
current ratio p of 5 is used, resulting in a temperature coefficient of ~0.14 mV/°C. F
kT
ADC, a 1.2 V bandgap voltage∆V can be
BE ( T ) =usedlnto
(p)digitize ∆VBE. Such reference (2) is gen
q
by adding an amplified version of ∆VBE to VBE so as to obtain a temperature-indepe
voltage VREF∆V
Hence, only depends on the ratio of currents p, making it an accurate measure
asBEfollows:
of temperature. A larger current ratio p results in a larger ∆VBE , but the designer must
ensure that the two transistors remain𝑉in the= α ∙operating
same Δ𝑉 +region 𝑉 [1]. In this work, a
current ratio p of 5 is used, resulting in a temperature coefficient of ~0.14 mV/◦ C. For the
ADC,Inaorder to obtain
1.2 V bandgap voltage = 1.2
a VREFcan V, the
be used to digitize ∆VBEα
necessary is 14.
. Such However,
reference in our design
is generated
we
byare operating
adding an amplified ∆VV,
VDD =of1.8
withversion weVBE
BE to have
so asreduced
to obtain athe VREF to around 0.4 V so th
temperature-independent
voltage V as follows:
Σ∆ does not saturate. This was performed by properly designing the number of c
REF
VREF =α·∆VBE + VBE (3)
tances in the charge balancing Σ∆. The ADC then converts the ratio of α·∆VBE and V
order In
toorder to obtain
obtain a VREF
a digital = 1.2 V,D
reading the necessary
OUT α is 14. However, in our design, since
as follows:
we are operating with VDD = 1.8 V, we have reduced the VREF to around 0.4 V so that the Σ∆
does not saturate. This was performed 𝐷 ∙
= 𝐴designing
by properly ∙ −number
the 𝐵 of capacitances
in the charge balancing Σ∆. The ADC then converts the ratio of α·∆VBE and VREF in order
to obtain a digital reading DOUT as follows:
where the coefficients A and B are chosen so as to obtain a digital output in degrees C
[1]. In our design, these coefficients ·∆VBE to be around 600 and 273, respective
areαchosen
D = A·OUT −B (4)
VREF
3.where
Proposed Temperature
the coefficients Sensor
A and B are chosen so as to obtain a digital output in degrees Cel-
siusFigure
[1]. In our design, the
2 shows theseblock
coefficients
diagramare chosen
of thetosensor.
be around
The600 and 273, respectively.
front-end is constituted by
circuit, that generates
3. Proposed Temperature a Sensor
PTAT voltage (with an IBIAS current) and a bipolar core that
ates the voltages
Figure 2 shows∆Vthe
BE and
blockVdiagram
BE. Theseofvoltages
the sensor.serve
The as the Σ∆ modulator,
inputs istoconstituted
front-end by
produces a bitstream
a bias circuit, bs, which
that generates a PTAT average
voltagevalue
(with is
anequal to the ratio
IBIAS current) and abetween α·∆VBE and
bipolar core
thatconverter
The generates the
usesvoltages ∆VBE and VBE . scheme
a charge-balancing These voltages
whichserve
willasbeinputs to theinΣ∆
detailed Section 3
modulator, which produces a bitstream bs, which average value is equal to the ratio
filter the quantization noise from the bitstream and achieve the required scaling a
between α·∆VBE and VREF . The converter uses a charge-balancing scheme which will be
lined in Equation
detailed (3),To
in Section 3.2. a filter
decimation filter isnoise
the quantization utilized.
from the bitstream and achieve the
required scaling as outlined in Equation (3), a decimation filter is utilized.

Figure 2. Block diagram of the temperature sensor.

Figure 2. Block diagram of the temperature sensor.
3.1. Biasing Circuitry
Figure Circuitry
3.1. Biasing 3 shows the bias circuit of the front end, used to generate a PTAT current and
VBIASP . While some variance in the absolute value of the bias current can be accepted since
Figure
it can 3 shows
be trimmed, the bias
it is crucial circuit of
to minimize thesources
other front end, used
of error tobias
in the generate
current,asuch
PTATas curren
BIASP. Whilewith
Vfluctuations some the variance in the
supply voltage absolute
and value
temperature of the bias
dependence. current
Typically, can
bias be accepted
current
it iscan
obtained from a bias
be trimmed, voltage
it is through
crucial a resistor.other
to minimize Optingsources
for a biasofvoltage
error derived from current
in the bias
the difference in base-emitter voltage is favorable because, as previously mentioned, it
relies solely on a current ratio. Additionally, employing such a PTAT bias voltage offers the
advantage of reducing the temperature dependency of the bias current, thereby mitigating
 as fluctuations with the supply voltage and temperature dependence. Typically, b
as fluctuations with the supply voltage and temperature dependence. Typically, bias cur-
rent
rent is is obtained
obtained fromfrom a bias
a bias voltage
voltage through
through a resistor.
a resistor. OptingOpting forvoltage
for a bias a bias derived
voltage
from
from thethe difference
difference in base-emitter
in base-emitter voltage
voltage is favorable
is favorable because,
because, as previously
as previously mentioned, men
Electronics 2024, 13, 2823 it it relies
relies solely
solely on on a current
a current ratio.ratio. Additionally,
Additionally, employing
employing such abias
such a PTAT PTAT bias
voltage
5 of voltag
16 offers
thethe advantage
advantage of reducing
of reducing the temperature
the temperature dependency
dependency of the
of the bias bias current,
current, there
thereby miti-
gating
gating thethe curvature
curvature of Vof VBE compared
BE compared to a constant
to a constant bias voltage.
bias voltage. Furthermore,
Furthermore, choppingch
isthe
also
is
curvature of VBE compared to a constant bias voltage. Furthermore, chopping is also
alsoapplied
appliedto the current
to the source
current in Figure
source 3 to remove
in Figure unwanted
3 to remove offsets. offsets.
unwanted
applied to the current source in Figure 3 to remove unwanted offsets.

Figure 3. Bias circuit used to generate IBIAS (and VBIASP).

Figure 3. Bias circuit used to generate IBIAS (and VBIASP ).
Figure 3. Bias circuit used to generate IBIAS (and VBIASP).
Figure 4 illustrates the implementation of the complete current source used to gener-
Figure 4 illustrates the implementation of the complete current source used to generate
ate VBE and ∆VBE. One of the most important sources of inaccuracy is the mismatch of the
VBE andFigure
∆VBE4 illustrates
. One the important
of the most implementation
sources ofofinaccuracy
the complete is the current
mismatchsource
of the used t
1:p
1:p
(1:5
(1:5
in
in
our
our
design)
design)
currentratio
current
ratio depicted
depicted in
in Figure
Figure 1,
1, consequently
consequently
affecting
affecting ∆V
∆VBE. In
ate VBE and ∆VBE. One of the most important sources of inaccuracy is the BE . In
mismatc
order to improve such a mismatch and achieve the desired level of
order to improve such a mismatch and achieve the desired level of accuracy, dynamic accuracy, dynamic
1:p (1:5 in our design)
element
currentemployed
ratio depicted in Figure 1, consequently affecting
elementmatching (DEM)must
matching (DEM) mustbebeemployed to mitigate
to mitigate mismatches.
mismatches. FigureFigure 4b illustrates
4b illustrates
order
the to improve
theconfiguration such a
thecurrent
configuration of the mismatch
currentsource
source and
when
when achieve the
∆VBE
generating
generating ∆V desired
BE [2].
[2]. level of accuracy, d
element matching (DEM) must be employed to mitigate mismatches. Figure 4b ill
the configuration of the current source when generating ∆VBE [2].

(a)

(a)

(b)
Figure 4. Cont.

(b)
Electronics 2024, 13, x FOR PEER REVIEW
Electronics 2024, 13, 2823
6 of 16
6 of 16

(c)
Figure
Figure 4.
4. Current sourceused
Current source used
to to
generate ∆VBE
generate ∆Vand
BE and
VBE .V(a)
BE. Complete
(a) Complete schematic
schematic of the current
of the current
source.
source.(b)
(b) Current sourceconfiguration
Current source configuration used
used to obtain
to obtain a dynamically
a dynamically matched
matched 1:5 bias1:5 bias current
current ratio ratio
for generating ∆V
forgenerating ∆VBEBE.. (c)
(c)Current
Currentsource
source configuration
configuration usedused to obtain
to obtain a trimmable
a trimmable bias Icurrent
bias current TRIM ITRIM
for generating V
for generating VBE
BE.

Six PMOS
Six PMOS current
current sources,
sources, eacheach nominally
nominallyproviding
providing2 2µA, µA,replicate
replicatethethecurrent
current gen-
generated in the bias circuit. Through a set of switches, each current is directed to either Q1
erated in the bias circuit. Through a set of switches, each current is directed to either Q1 or
or Q (in Figure 4b). One of these switches is routed to one transistor, delivering the unit
Q2 (in2 Figure 4b). One of these switches is routed to one transistor, delivering the unit
current in the 1:5 ratio, while the remaining currents are routed to the other transistor. The
current
mismatch in the 1:5 ratio,
between while
the unit the remaining
current source and currents
the average areofrouted
the otherto sources
the other transistor. The
introduces
mismatch between the unit current source and the average of the
errors in the resulting current ratio. By alternating the unit current source in successive other sources introduces
errors in thecycles,
modulator resulting current
mismatch ratio.
errors areBy alternating
averaged the unit
out. The current
integrator source
of the in successive
modulator
modulator
performs the cycles,
required mismatch
averaging. errors are averaged
The front-end out. The
also allows us tointegrator of thetrimming,
perform current modulator per-
in order
forms thetorequired
compensate for variations
averaging. in the nominal
The front-end value ofusthe
also allows totransistor’s saturation
perform current trimming,
incurrent
order and the spread offor
to compensate thevariations
bias current initself. Traditional
the nominal valuetrimming
of the methods involve
transistor’s saturation
adjusting
current andthetheemitter area of
spread or the
bias bias
current using switchable
current binary-scaled
itself. Traditional transistors
trimming or biasinvolve
methods
current sources [2].
adjusting the emitter area or bias current using switchable binary-scaled transistors or bias
However, given the extensive required range, such techniques become complex and
current
demandsources
substantial[2]. chip area. Alternatively, in this work, the same six PMOS current
However, given the extensive
sources utilized for generating required
the 1:5 currentrange, such
ratio are techniques
repurposed for become
generatingcomplex
the and
demand
trimmedsubstantial
current. Thischip area. Alternatively,
is feasible because ∆VBE and in this work,
VBE are nevertheused
same six PMOS current
simultaneously.
sources utilized
Hence, five of these forsources
generating thecoarse
facilitate 1:5 current
trimming, ratio are repurposed
controlled by the digitalforinput,
generating
and the
the sixth current
trimmed current.source This enables fine trimming,
is feasible because ∆V byBEusing
andtheVBEIDAC
are innever
Figure 4c. Such
used small
simultaneously.
4-bit current
Hence, five ofDAC theseissources
employed to achieve
facilitate coarsea trimming
trimming, resolution
controlled of 64
bynA.
theWith a total
digital input, and
trimming range of 2–12 µA, with a 64 nA step, it adequately compensates
the sixth current source enables fine trimming, by using the IDAC in Figure 4c. Such small for practical
variations, and it is sufficient to reduce the mismatch to acceptable values. In the implemen-
4-bit current DAC is employed to achieve a trimming resolution of 64 nA. With a total
tation, unused current sources are connected to an additional diode-connected transistor
trimming
(not depictedrange of 2–12
in Figure 4), µA, with alimiting
effectively 64 nAswitching
step, it adequately
transients atcompensates
their outputs. for practical
variations, and it is sufficient to reduce the mismatch to acceptable values. In the imple-
3.2. Sigma–Delta
mentation, ADCcurrent sources are connected to an additional diode-connected tran-
unused
sistorThe
(notADC,
depicted
comprising a Σ∆
in Figure 4),modulator
effectivelyand
limiting switching
a decimation transients
filter, ∆Vtheir
converts at outputs.
BE and
VBE into a digital temperature reading DOUT . The design of the Σ∆M in smart tempera-
tureSigma–Delta
3.2. sensors greatly
ADCinfluences their performance by enhancing or degrading its accuracy,
resolution, noise immunity, and conversion speed. Σ∆s enable precise analog-to-digital
The ADC, comprising a Σ∆ modulator and a decimation filter, converts ∆VBE and VBE
conversion by oversampling the input signal and employing noise shaping techniques,
into
whichdigital
a temperature
significantly reducesreading DOUTnoise
quantization . The within
designthe
of the ΣΔM
signal in smartThis
bandwidth. temperature
results sen-
sors greatly
in more influences
accurate their performance
temperature measurements, by even
enhancing
in the or degrading
presence its accuracy,
of electronic noise resolu-
and varying environmental conditions. Additionally, Σ∆s allow for simpler and moreconver-
tion, noise immunity, and conversion speed. ΣΔs enable precise analog-to-digital
sion by oversampling
cost-effective the by
sensor design input signal high-resolution
integrating and employing noiseoutput
digital shaping techniques,
and reducing the which
need for complex analog circuitry, making the overall sensor system more reliable
significantly reduces quantization noise within the signal bandwidth. This results in more and
efficient. temperature
accurate Fundamentally, the Σ∆ requirements
measurements, even inwill
thedepend on two
presence performances,
of electronic noisenamely
and varying
environmental conditions. Additionally, ΣΔs allow for simpler and more cost-effective
sensor design by integrating high-resolution digital output and reducing the need for
complex analog circuitry, making the overall sensor system more reliable and efficient.
Fundamentally, the ΣΔ requirements will depend on two performances, namely conver-
 of similar order as the modulator. A first-order modulator is utilized, employing a fully
differential switched-capacitor implementation. The switched-capacitor implementation
of the modulator is depicted in Figure 5. Mismatch between the unit capacitors constrains
the accuracy of the integration. Hence, to limit the temperature error resulting from this
Electronics 2024, 13, 2823 7 of 16
mismatch to ~0.01 °C, it is imperative that the matching be precise, which cannot be solely
achieved through layout precision. Once again, DEM techniques are employed to the CIN
and CS capacitances to average
conversion out quantization
time and mismatch errors error. Thisbywill
alternating
impact thethe unit
choice capacitor
of topology, used
order of the
modulator, and if the decimator filter can be a simple counter
in successive modulator cycles. To ensure minimal errors due to finite gain, an operation or something more complex.
The higher the Σ∆ order, the less cycles it will need to measure the temperature, but it will
amplifier with a DC gain of around 120 dB was implemented. The comparator is designed
consume more power, area, and it will be more complex to design as well. The order of
as a dynamic latchthepreceded
modulatorby willa dictate
preamp, howwhich prevents
many cycles any
we will kickback
need to the output
for a temperature reading ofand
the second integrator. Theismodulator
therefore directly relatedadopts
to the nonoverlapping
conversion speed asclocks.well as the decimation filter. In our
Furthermore,approach, we target
while offset anda1/ƒ 14-bit resolution,
noise of theand the maximum
integrator conversion
are reduced bytime
theisapplied
set to 10 ms
and the operation frequency is 1 MHz. The modulator generates
correlated double-sampling, charge injection mismatch in the switches still exists, result- a certain number of bits,
which are converted into a single temperature reading by the decimation filter. This mode
ing in some offset.ofThe used CMOS
operation, switches were
termed “incremental”, designed
enables the use to
of aminimize this offset,
relatively simple how-filter
decimation
ever, an offset of aoffew tensorder
similar of µV remains.
as the modulator.In order to reduce
A first-order the offset,
modulator the modulator
is utilized, employing ais fully
chopped at the system level.
differential A chopper switch
switched-capacitor at the input
implementation. and a switch atimplementation
The switched-capacitor the output of
thethe
periodically reverse modulator
polarity is depicted in Figure
of the input signal 5. Mismatch between theTo
and the bitstream. unit capacitors
avoid constrains
disturbing
the accuracy of the integration. Hence, to limit the temperature error resulting from this
the operation of the modulator when chopping, its state is also inverted by swapping the
mismatch to ~0.01 ◦ C, it is imperative that the matching be precise, which cannot be solely
integration capacitors of both
achieved throughintegrators. The chopping
layout precision. Once again,is DEMdone at a slow
techniques are speed
employedto to
make
the CIN
errors due to charge
and injection in the
CS capacitances chopper
to average outswitches
mismatchnegligible. Two chopping
errors by alternating periods
the unit capacitor used
in successive modulator cycles. To ensure minimal errors
per conversion are used in order to average and cancel the offsets. The CINT capacitor is due to finite gain, an operation
amplifier with a DC gain of around 120 dB was implemented. The comparator is designed
chosen as three times the value of the CS capacitor so as to reduce the effective VREF seen at
as a dynamic latch preceded by a preamp, which prevents any kickback to the output of
the input of the modulator.
the second integrator. The modulator adopts nonoverlapping clocks.

Figure 5. Simplified circuit diagram of the front-end circuitry and the sigma–delta modulator.
Figure 5. Simplified circuit diagram of the front-end circuitry and the sigma–delta modulator.
Furthermore, while offset and 1/ƒ noise of the integrator are reduced by the applied
correlated
3.3. Decimation Filter double-sampling, charge injection mismatch in the switches still exists, resulting
in some offset. The used CMOS switches were designed to minimize this offset, however,
The Σ∆ modulator runs
an offset for tens
of a few 8192of cycles of 1 In
µV remains. µsorder
(4096to cycles times
reduce the two
offset, the complete chop-
modulator is chopped
ping periods) andatthen feedslevel.
the system suchA bitstream to the
chopper switch decimation
at the filter to
input and a switch produce
at the a deci-
output periodically
mated value which reverse the correlated
is then polarity of thetoinput signal and
a produce the bitstream. Toreading.
a temperature avoid disturbing the operation
A symmetrical
of the modulator when chopping, its state is also inverted by swapping the integration
filter function must be used in order to adequately average out the modulated offset and
capacitors of both integrators. The chopping is done at a slow speed to make errors due to
charge injection in the chopper switches negligible. Two chopping periods per conversion
are used in order to average and cancel the offsets. The CINT capacitor is chosen as three
times the value of the CS capacitor so as to reduce the effective VREF seen at the input of
the modulator.
Electronics 2024, 13, 2823 8 of 16

3.3. Decimation Filter

The Σ∆ modulator runs for 8192 cycles of 1 µs (4096 cycles times two complete chop-
ping periods) and then feeds such bitstream to the decimation filter to produce a decimated
value which is then correlated to a produce a temperature reading. A symmetrical filter
function must be used in order to adequately average out the modulated offset and dy-
namic element matching (DEM) residuals, thereby accurately representing the average
temperature during a conversion. However, during the operation of the temperature sensor,
the bitstream produces very similar codes for two consecutive temperature readings and
therefore, it may happen that the decimator “cuts” the reading before reaching different
patterns, and it would then produce an error in the output temperature. When targeting
lower accuracies, this effect would not be a problem, but when targeting an accuracy of
±0.15 ◦ C, this is problematic; hence, in this work, we developed a decimation filter in the
hardware which solves this issue.
To first illustrate the concern addressed, please consider a mid-range voltage that
would result in a bitstream “0101010101. . .”. Voltages that differ by only one or two LSBs
from the mid-range voltage result in an identical bitstream during a very long number of
clock cycles before they present a pair of “11” or “00”. If the decimator only considers 512
or 1024 bits of the bitstream, it will output a huge error. This behavior was observed when
performing the conversion of temperatures from −40 ◦ C to 125 ◦ C, with steps of 0.1 ◦ C and
it was noticed for temperatures around the ones that produce the bitstreams with patterns
“1010101. . .”, “0100100100. . .”, and “1011011011. . .”. The corrective measure was to detect
these patterns and to change the oversampling ratio to double the number of bits to include
in the analyzed bitstream when one of these patterns is present. When a start of conversion
occurs, the analog part of the ADC is expected to be powered down. The digital state
machine of the ADC has a timer that allows the analog part of the ADC to achieve a steady
state. The bitstream is ignored while the digital timer counts and waits for the analog
circuitry to power up. However, the most recent four ignored values are stored in a four-bit
shift register. When the timer ends the waiting period, the four bits in the shift register are
compared with “1010” and “0101” to detect the regular pattern “1010101. . .”. The four bits
are also compared with ”1001”, “0100”, and “0010” to detect the pattern “0100100100. . .”;
and with “0110”, “1011”, and “1101” to detect the pattern “1011011011. . .”.
To solve this issue, a second-order Σ∆ could be used, or a more complex decimation
filter. However, this would impact the power, area, and complexity of the design. Therefore,
in order to comply with the accuracy, in this work, an adaptative decimation filter is
implemented that is able to recognize such repetitive patterns in the problematic reading
areas (such as Σ∆ modulator mid-scale code) and increase the oversampling ratio in order
to compensate and avoid high errors in such mid-scale areas. When such patterns are
identified, the conversion time is increased; however, the accuracy is maintained at a low
cost, both in terms of power and area, since the decimation filter is kept simple.

4. Experimental Results
The temperature sensor was designed in a 65 nm CMOS technology operating with
supply voltages of 1.8 V/1.2 V (analog/digital). The decimation filter and the digital control
circuitry were all synthesized and implemented on a chip. The chip layout is shown in
Figure 6 (only the analog part).
In order to inspect the performances of the temperature sensor, and the impact of the
several implemented techniques for error reduction (chopping and DEM) several Monte-
Carlo (MC) and PVT simulations were performed and are shown in the following sub-
sections.
Electronics 2024, 13, x FOR PEER REVIEW
Electronics 2024, 13, 2823
9
9 of 16

Figure6.6. Layout
Figure Layoutofofthe
thetemperature
temperature sensor
sensor (only
(only analog
analog part).
part). TheThe analog
analog partpart measures 360
measures
µm.
360 × 220 µm.

4.1. Temperature Sensor Accuracy over Monte-Carlo Simulations

In order to inspect the performances of the temperature sensor, and the impact o
Although the benefits of using chopping [9–11] and DEM techniques [12,13] are widely
several implemented techniques for error reduction (chopping and DEM) several M
known, in this sub-section, several MC simulations were performed to quantify such
Carlo (MC)
benefits. Due toand PVT simulation
the large simulations were
time performed
of each sample, a and are30shown
total of samplesinand
theonly
following
sections.simulations were considered in order to keep the simulation time manageable.
pre-layout
The simulations shown here were performed at the top level, considering the entire
temperature sensor.Sensor
4.1. Temperature In order to drawover
Accuracy conclusions from Simulations
Monte-Carlo the benefits of using DEM and
chopping individually, when the intention is to observe the benefits of DEM (Section 4.1.1),
Although
the simulation the benefits
considers chopping; ofand
using chopping
on the other hand,[9–11]
when and DEM of
the benefits techniques
chopping [12,13
widely
are known,(Section
to be observed in this 4.1.2),
sub-section, severalAll
DEM is applied. MCthesimulations
simulations inwere performed
this Section were to qua
suchfor
made benefits. Due to of
the temperature the ◦
30large
C andsimulation time
therefore, the of shown
errors each sample, a total
are for this of 30 sample
temperature.
only pre-layout simulations were considered in order to keep the simulation time
4.1.1. Benefits of Dynamic Element Matching
ageable.
DEM is a critical technique for reducing mismatch due to process variations. In this
The simulations shown here were performed at the top level, considering the e
temperature sensor, DEM is being applied in the front-end to the current sources (CS) that
temperature
bias the BJT diodessensor.
and inIn
theorder
input to draw conclusions
capacitances from theInbenefits
of the Σ∆ modulator. of using DEM
this sub-section,
chopping individually, when the intention is to observe the
MC simulations were performed in two situations—with and without DEM. The results benefits of DEM (Se
4.1.1),
are shown thein simulation
Figures 7 andconsiders
8. chopping; and on the other hand, when the benefi
It can be concluded that applying
chopping are to be observed (Section DEM4.1.2),
is critical
DEM for good accuracy.
is applied. AllEspecially in
the simulations in
the case of the CSs biasing the BJT
Section were made for the temperaturediodes (Figure
of 7),
30 it
°C can be
and seen that
therefore,if DEM
the was
errors not
shown ar
applied, then errors of more than 1 ◦ C could be obtained. In this example, by applying
this temperature. ◦ ◦
DEM, the temperature error was reduced from more than 1 C to less than 0.15 C (in
some samples). Hence, applying DEM on the CS of the front-end is key for achieving good
4.1.1. Benefits
accuracy. of Dynamic
Regarding the case ofElement
the Σ∆ CMatching
IN , the results are not that critical but are still
important to have a system accuracy with less than 0.1 ◦ C error (see Figure 8). Table 1
DEM is a critical technique for reducing mismatch due to process variations. In
shows a resumption of such simulations including maximum, minimum, average, and 3σ
temperature sensor, DEM is being applied in the front-end to the current sources (CS
results of the temperature error.
bias the BJT diodes and in the input capacitances of the Σ∆ modulator. In this sub-sec
MC simulations were performed in two situations—with and without DEM. The re
are shown in Figures 7 and 8.
Electronics 2024, 13, x FOR PEER REVIEW 10 of 16
Electronics 2024, 13, x FOR PEER REVIEW 10 of 1
Electronics 2024, 13, 2823 10 of 16

Figure 7. Simulation of 30 Monte-Carlo samples showcasing the benefits of DEM in the curren
Figure7.7.Simulation
Figure Simulation of of
30 30 Monte-Carlo
Monte-Carlo samples
samples showcasing
showcasing the benefits
the benefits of DEMof in DEM in the curren
the current
sources (CS) that generate the current for the diodes which generate ∆VBE and VBE (in this case, the
sources(CS)
sources (CS) that
that generate
generate the the current
current fordiodes
for the the diodes
which which ∆VBE and
generategenerate ∆V VBE
BE and
(in V
this
BE (in
case, this
the case, th
DEM in CIN of the Σ∆ modulator is being considered).
DEMininCC
DEM ININofof
the Σ∆
the Σ∆ modulator
modulator is being
is being considered).
considered).

Figure 8.
Figure 8. Simulation
Simulation ofof 30 Monte-Carlo samplesshowcasing
Monte-Carlo samples showcasingthe
thebenefits
benefitsofof DEM
DEM inin the
the input capac
input
Figure 8. Simulation of 30 Monte-Carlo samples showcasing the benefits of DEM in the input capac
itors (CIN)(C
capacitors ) ofΣ∆
ofINthe Σ∆ modulator
themodulator (in (in
thisthis
case, the
case, theDEM
DEMin
inCS
CS is being
beingconsidered).
considered).
itors (CIN) of the Σ∆ modulator (in this case, the DEM in CS is being considered).
Table 1. Results of the simulation of 30 Monte-Carlo samples showcasing the benefits of DEM in the
ItIt can
can be concluded that applying
applying DEM
DEMis is critical
critical for
forgood
good accuracy.
accuracy.Especially
Especiallyin
inthe
be(C
input capacitors IN ) of the Σ∆
concluded that
modulator. th
case
case ofof the
the CSs
CSs biasing
biasing the
the BJT
BJT diodes
diodes (Figure
(Figure 7),
7), itit can
can be
be seen
seen that
that ifif DEM
DEM waswas not
not ap-
ap
Temperature
plied, then Error
errors of moreNo DEM
than 1 in
°CC could
IN be No DEM
obtained. in CS
In this With
example, Both byDEMs
applying DEM
plied, then errors of more than 1 °C could be obtained. In this example, by applying DEM
the Maximum (◦ C) error was reduced 0.16 1.33 1 °C to less than 0.120.15 °C (in some
the temperature
temperature
Average ◦ error was
( C) applying DEM
reduced from
from more
−0.01 on the CS of the
more than
than
−0.07
1 °C to less than
−0.01
0.15 °C (in som
samples).
samples). Hence,
Hence, applying DEM on the CS of the front-end is key
front-end is key for for achieving
achieving good
good ac-ac
Minimum (◦ C) −0.13 −1.01 −0.09
curacy. Regarding
curacy.3σRegarding the
the case
case of
of the
the Σ∆
Σ∆ C
CIN, the results are not that critical but are still im-
IN, the results are not that critical but are still im
(◦ C) 0.18 1.82 0.14
portant
portant to to have
have aa system
system accuracy
accuracy with
with less
less than
than 0.1
0.1 °C °C error
error (see
(see Figure
Figure 8).8). Table
Table 11 shows
show
aaresumption
resumption of such simulations including maximum, minimum, average, and 3σ results
4.1.2. Benefits ofofChopping
such simulations including maximum, minimum, average, and 3σ result
of
of the
the temperature
temperature error. error.
In order to quantify the benefits of chopping, two different MC experiments were
performed as follows:
Table 1. Results A total ofof3030MC
of the simulation samples with
Monte-Carlo sampleschopping ∅1 active
showcasing and 30ofMC
the benefits DEM in the
Table 1. in
samples Results of the∅simulation
chopping active of 30
were Monte-Carlo
tested. In order samples
to see showcasing
the benefits ofthe benefits such
chopping, of DEM in th
input capacitors (CIN) of the Σ∆ modulator.
2
input capacitors IN) of the Σ∆ modulator.
(Cwere
temperature errors then averaged. Figure 9 shows the results of such an experiment.
It can be seen that the errors are large (>±in0.4C◦ C) in both ∅ and ∅ , but the average error is
Temperature
Temperature ErrorError No
No DEM
DEM in CIN
IN
No
No1DEM
DEM in 2 CS
in CS With
With Both
Both DEMs
DEMs
subsequently reduced to less than 0.1 ◦ C; hence, performing chopping does not have such
Maximum
Maximum (°C) 0.16 1.33 0.12
a large impact as (°C) 0.16
DEM but it is still important 1.33of around 0.1 ◦ C. Table
to achieve errors 0.122
Average
Average (°C)
(°C) −0.01
−0.01 −0.07
−0.07 −0.01
−0.01
Minimum
Minimum (°C)
(°C) −0.13
−0.13 −1.01
−1.01 −0.09
−0.09
3σ (°C)
3σ (°C) 0.18
0.18 1.82
1.82 0.14
0.14
 performed as follows: A total of 30 MC samples with chopping ∅ active and 30 MC sam-
ples in chopping ∅ active were tested. In order to see the benefits of chopping, such tem-
perature errors were then averaged. Figure 9 shows the results of such an experiment. It
Electronics 2024, 13, 2823
can be seen that the errors are large (>±0.4 °C) in both ∅ and ∅ , but the average error is
11 of 16
subsequently reduced to less than 0.1 °C; hence, performing chopping does not have such
a large impact as DEM but it is still important to achieve errors of around 0.1 °C. Table 2
shows
shows aa resumption
resumption ofofsuch
suchsimulations
simulations including
including maximum,
maximum, minimum,
minimum, average,
average, and 3σ and 3σ
results
results of the
the temperature
temperatureerror
error
in in order
order to inspect
to inspect the benefits
the benefits of chopping.
of chopping.

Figure
Figure 9.
9. Simulation
Simulation ofof3030Monte-Carlo
Monte-Carlo samples,
samples, showing
showing the benefits
the benefits of chopping
of chopping with
with the the average
average
ofofchopping
chopping ∅ and∅2∅. 2 .
∅11 and

Table 2.
Table Results of
2. Results ofthe
thesimulation
simulationof of3030Monte-Carlo
Monte-Carlosamples, showing
samples, the benefits
showing of chopping
the benefits with
of chopping with
theaverage
the average of chopping∅1∅and
of chopping 1 and
∅ 2 .∅ 2 .
Temperature Error
Temperature Error With Ø1
With Ø1 With With
Ø1 Ø1 Average Ø1 and Ø
Average Ø21 and Ø2
Maximum (◦ C) 0.50 0.52 0.12
Maximum (°C) 0.50 0.52 0.12
Average (◦ C) 0.05 −0.04 −0.01
Average (°C) 0.05 −0.04 −0.01
Minimum (◦ C) −0.33 −0.36 −0.09
Minimum
3σ (◦ C) (°C) 0.62−0.33 0.65 −0.36 0.14 −0.09
3σ (°C) 0.62 0.65 0.14
4.2. Temperature Sensor Accuracy over PVT Variations
4.2. Temperature Sensor Accuracy
In this sub-section, the resultsover
are PVT Variations
presented over 64 corners with varying PVT con-
Electronics 2024, 13, x FOR PEER REVIEW
ditions as shown
In this in Figurethe
sub-section, 10.results
The supply voltage was
are presented considered
over withwith
64 corners a 10% PVT12con-
variation,
varying of 16
◦ ◦
and theas
ditions temperature
shown in range 10.−The
Figurewas 40 C up to 125
supply C. These
voltage was simulations
considered were
withperformed
a 10% variation,
considering both DEM and chopping (average of Ø1 and Ø2 ).
and the temperature range was −40 °C up to 125 °C. These simulations were performed
considering both DEM and chopping (average of Ø1 and Ø2).

Figure10.
Figure 10.Simulation
Simulationof of
64 64 pre-layout
pre-layout PVTPVT corners.
corners.

4.3. Post-Layout Results

In this sub-section, the post-layout results are presented. In Figures 10 and 11, it is
possible to observe the temperature error for the same PVT (for pre-and post-layout re
spectively). It is possible to observe that the post-layout results do not differ much from
the pre-layout since the layout respected all the necessary constraints in order to maintain
 Figure 10. Simulation of 64 pre-layout PVT corners.

Electronics 2024, 13, 2823 12 of 16

4.3. Post-Layout Results
In this sub-section, the post-layout results are presented. In Figures 10 and 11, it is
possible to observe
4.3. Post-Layout Results the temperature error for the same PVT (for pre-and post-layout re-
spectively).
In this It is possiblethe
sub-section, to post-layout
observe that the post-layout
results are presented. results do not10differ
In Figures and 11,muchit from
the pre-layout since the layout respected all the necessary constraints
is possible to observe the temperature error for the same PVT (for pre-and post-layout in order to maintain
accuracy. ThereIt isisonly
respectively). possibleone tocorner where
observe thatthe
theerror increased
post-layout from
results do0.13
not °C to 0.25
differ much °C; how-
from this
ever, the pre-layout
is still a very since the layouttemperature
acceptable respected all error.
the necessary
Apart from constraints in order
the corners, it to
was also
◦ C to
important to study how the post-layout parasitics impacted the performance of the Σ∆
maintain accuracy. There is only one corner where the error increased from 0.13
0.25 ◦ C; however,
modulator. Hence, thisinisorder
still a very acceptable
to observe this,temperature error. Apartwere
several simulations from performed
the corners, it (34 tem-
was also important to study how the post-layout parasitics impacted the performance of
perature points) and its error was observed for each temperature point at the input and
the Σ∆ modulator. Hence, in order to observe this, several simulations were performed
output of the modulator.
(34 temperature points) andThe objective
its error was to for
was observed seeeach
if there was some
temperature degradation
point at the input due to
the Σ∆ modulator. The result of this simulation is shown in
and output of the modulator. The objective was to see if there was some degradationFigure 12, where it is possible
todue
observe
to the that there is almost
Σ∆ modulator. no degradation
The result from the
of this simulation inputin
is shown toFigure
the output of the
12, where Σ∆ mod-
it is
ulator,
possiblewhich means
to observe thatthat theispost-layout
there parasitics from
almost no degradation Σ∆input
of thethe modulator do not
to the output ofimpact
the the
Σ∆ modulator, which means
performance of the temperature sensor. that the post-layout parasitics of the Σ∆ modulator do not
impact the performance of the temperature sensor.

Electronics 2024, 13, x FOR PEER REVIEW 13 of 16

Figure
Figure 11.
11. Simulation
Simulation ofof6464post-layout
post-layout PVT
PVT corners.
corners.

Figure12.
Figure 12.Temperature
Temperature error
error versus
versus temperature
temperature (error(error
at the at the of
input input of the sigma–delta
the sigma–delta and errorand
at error a
the output
the outputofofthe
the sigma–delta).
sigma–delta).

Furthermore, it is also interesting to compare the temperature sensor described in

this work against the other state-of-the-art sensors. Table 3 shows how this temperature
sensor fares against similar temperature sensors that are also using bipolars as diodes and
a 1st order modulator (in particular, a Σ∆).
Electronics 2024, 13, 2823 13 of 16

Furthermore, it is also interesting to compare the temperature sensor described in this

work against the other state-of-the-art sensors. Table 3 shows how this temperature sensor
fares against similar temperature sensors that are also using bipolars as diodes and a 1st
order modulator (in particular, a Σ∆).

Table 3. Comparison against state-of-the-art temperature sensors which use bipolar transistors as
diodes and a 1st order Σ∆ as a modulator.

Tech. Area Trim PP IA Min-Max RIA 2 TCONV Power. Energy Resolu.

Source R-FOM 3
(nm) (mm2 ) Points (◦ C) (◦ C) (%) (ms) (µW) (nJ) (K)
[14] 1
2000 1.5 1 2.0 −40~120 1.3 20 55.0 1100 0.100 11.0
JSSC‘96
[15]
700 3 0 3.0 −40~120 1.9 250 300 75,000 0.050 187.50
ESSCIRC‘99
[16] 1
700 2.8 0 3.0 −50~125 1.7 100 280 28,000 0.125 437.50
ISCAS‘01
[17]
65 0.1 1 0.4 −70~125 0.2 455 10.0 4532 0.030 4.079
ISSCC‘10
[18] 1
14 0.0087 2 3.3 0~100 3.3 0.02 1111 24 0.500 6.112
JSSC‘15
[19] 1
16 0.0126 0 4.0 −50~150 2.0 0.27 1210 327 0.400 52.272
ESSCIRC‘15
[19] 1
20 0.018 1 5.0 −25~125 3.3 0.16 1100 176 0.400 28.160
ESSCIRC‘15
[20]
180 0.198 1 0.4 25~45 2.0 500 1.1 550 0.010 0.055
Sensors‘16
[21]
28 0.0095 0 3.70 −25~125 2.47 8.2 18.8 154 0.150 3.456
ISSCC‘17
[22] 1
65 0.003 2 2.70 −10~110 2.25 4.10 111.8 458 0.130 7.747
TCAS-I‘20
[23]
55 0.0146 0 3.40 −40~125 2.06 32.8 37.0 1214 0.020 0.485
TCAS-II‘19
This
65 0.079 1 0.25 −40~125 0.15 8.53 232 1979 0.039 3.269
work1,4
1 Works that have the digital back-end implemented on-chip (including the decimation filter).
2RIA = 100 × PP IA/Specified temperature range. 3 R-FOM: Resolution Figure-of-Merit. 4 Post-Layout
Results. R-FOM = (Energy/conversion) × (Resolution)2 .

Table 3 describes the technology in which the sensors were designed and some per-
formance metrics. Some are self-explanatory, but others need further explanation. For
example, the PP IA measure is the worst-case inaccuracy (IA) over a specified temperature
range. The values given for each temperature sensor are either max–min or 6σ values.
Since inaccuracy is a statistical measure, measurements on a large number of samples
(>12) are required to obtain realistic numbers. Inaccuracy is a function of sensor type,
readout architecture, process, and the number of trimming points. Due to the presence of
non-linearity, a sensor’s spread is usually less than its inaccuracy. In our case, the PP IA was
considered to be the worst-case corner in post layout results (0.25 ◦ C) on over 60 corners.
The RIA is the relative inaccuracy, which is given as the slope of an imaginary box placed
around the sensor’s error vs. temperature curve.
It is possible to conclude that the temperature sensor proposed in this work compares
well against the other state-of-the-art sensors. In particular, it has an exceptional PP-IA and
RIA and also presents a very good R-FOM. The results can be also seen in Figure 13a for the
FOM vs. RIA and in Figure 13b for the Resolution vs. Energy/Conversion performances.
 well against the other state-of-the-art sensors. In particular, it has an exceptional
and RIA and also presents a very good R-FOM. The results can be also seen in Figu
for the FOM vs. RIA and in Figure 13b for the Resolution vs. Energy/Conversion p
Electronics 2024, 13, 2823
mances. 14 of 16

(a)

(b)
Figure
Figure13.
13.Comparisons against
Comparisons against thethe state-of-the-art
state-of-the-art sensor.
sensor. The squares
The squares are otherare other
works, works,
and the and t
star is the temperature sensor presented in this work. (a) FOM vs. RIA and (b)
is the temperature sensor presented in this work. (a) FOM vs. RIA and (b) Resolution Resolution vs. v
Energy/Conversion performances.
ergy/Conversion performances.
5. Conclusions
In conclusion, this paper presents a significant advancement in the field of temperature
sensing with the development of a highly accurate and fast-conversion CMOS smart
temperature sensor. This sensor achieves an impressive ±0.15 ◦ C (3σ) inaccuracy over
a broad temperature range from −40 ◦ C to 125 ◦ C. These results are possible to achieve
since many analog counterparts of the circuit leverage from DEM techniques and the fast
conversion times are achieved by innovative adaptive decimation filtering techniques. The
circuit has been implemented in 65 nm CMOS technology and the sensor not only attains
exceptional accuracy but also maintains a swift 10 ms conversion time. This makes it highly
suitable for real-time temperature monitoring applications.
By integrating advanced Dynamic Element Matching (DEM) and chopping methods,
the sensor effectively minimizes its inaccuracy, ensuring reliable and precise temperature
measurements even in challenging operating conditions. This substantial advancement
underscores the potential of CMOS technology in enabling high-performance temperature
sensing solutions for a wide range of industrial, medical, and consumer electronics applica-
tions. The development of such a sensor highlights the promising future of accurate and
rapid temperature sensing technologies.
Electronics 2024, 13, 2823 15 of 16

Author Contributions: Conceptualization, G.S. and M.B.d.S.; design, G.S., M.B.d.S. and F.P.; val-
idation, G.S. and M.B.d.S.; writing—original draft preparation, F.P.; writing—review and editing,
F.P. and M.B.d.S.; supervision, G.S. All authors have read and agreed to the published version of
the manuscript.
Funding: This work was partially funded by the GreenChips-EDU project (Project 101123309) and
also funded by FCT/MCTES through national funds and when applicable co-funded EU funds under
the project (UIDB/50021/2020).
Data Availability Statement: Data supporting this study are included within the article.
Conflicts of Interest: The authors declare no conflict of interest.

References
1. Pertijs, M.A.P.; Huijsing, J.H. Precision Temperature Sensors in CMOS Technology; Springer Science: Berlin/Heidelberg,
Germany, 2006.
2. Pertijs, M.A.P.; Makinwa, K.A.A.; Huijsing, J.H. A CMOS smart temperature sensor with a 3σ inaccuracy of ±0.1 ◦ C from −55 ◦ C
to 125 ◦ C. IEEE J. Solid-State Circuits 2005, 40, 2805–2815. [CrossRef]
3. Baker, R.J. CMOS Mixed Signal Circuit Design; IEEE Press: New York, NY, USA; Wiley-Interscience: New York, NY, USA; John
Wiley & Sons: New York, NY, USA, 2002.
4. Toth, N.G.; Tang, Z.; Someya, T.; Pan, S.; Makinwa, K.A.A. 23.7 A BJT-Based Temperature Sensor with ±0.1 ◦ C (3σ) Inaccuracy
from −55 ◦ C to 125 ◦ C and a 0.85 pJ.K2 Resolution FoM Using Continuous-Time Readout. In Proceedings of the 2023 IEEE
International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 19–23 February 2023; pp. 358–360. [CrossRef]
5. Ali, I.; Asif, M.; Shehzad, K.; Rehman, M.R.U.; Kim, D.G.; Rikan, B.S.; Pu, Y.; Yoo, S.S.; Lee, K.-Y. A Highly Accurate, Polynomial-
Based Digital Temperature Compensation for Piezoresistive Pressure Sensor in 180 nm CMOS Technology. Sensors 2020, 20, 5256.
[CrossRef] [PubMed]
6. Meijer, G.C.M.; Wang, G.; Fruett, F. Temperature sensors and voltage references implemented in CMOS technology. IEEE Sens. J.
2001, 1, 225–234. [CrossRef]
7. Toth, N.G.; Tang, Z.; Someya, T.; Pan, S.; Makinwa, K.A.A. A PNP-Based Temperature Sensor With Continuous-Time Readout
and ±0.1 ◦ C (3σ) Inaccuracy From −55 ◦ C to 125 ◦ C. IEEE J. Solid-State Circuits 2024, 1–10. [CrossRef]
8. Tang, Z.; Pan, S.; Grubor, M.; Makinwa, K.A.A. A Sub-1 V Capacitively Biased BJT-Based Temperature Sensor With an Inaccuracy
of ±0.15 ◦ C (3σ) From −55 ◦ C to 125 ◦ C. IEEE J. Solid-State Circuits 2023, 58, 3433–3441. [CrossRef]
9. Klumperink, E.A.M.; Gierkink, S.L.J.; van der Wel, A.P.; Nauta, B. Reducing MOSFET 1/f noise and power consumption by
switched biasing. IEEE J. Solid-State Circuits 2000, 35, 994–1001. [CrossRef]
10. van der Ploeg, H.; Hoogzaad, G.; Termeer, H.A.H.; Vertregt, M.; Roovers, R.L.J. A 2.5-V 12-b 54-Msample/s 0.25-/spl mu/m
CMOS ADC in 1-mm/sup 2/ with mixed-signal chopping and calibration. IEEE J. Solid-State Circuits 2001, 36, 1859–1867.
[CrossRef]
11. Wang, C.B. A 20-bit 25-kHz delta-sigma A/D converter utilizing a frequency-shaped chopper stabilization scheme. IEEE J.
Solid-State Circuits 2001, 36, 566–569. [CrossRef]
12. Fogleman, E.; Galton, I. A dynamic element matching technique for reduced-distortion multibit quantization in delta-sigma
ADCs. IEEE Trans. Circuits Syst. II Analog. Digit. Signal Process. 2001, 48, 158–170. [CrossRef] [PubMed]
13. Sanyal, A.; Chen, L.; Sun, N. Dynamic Element Matching With Signal-Independent Element Transition Rates for Multibit ∆Σ
Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 2015, 62, 1325–1334. [CrossRef]
14. Bakker, A.; Huijsing, J.H. Micropower CMOS temperature sensor with digital output. IEEE J. Solid-State Circuits 1996, 31, 933–937.
[CrossRef]
15. Bakker, A.; Huijsing, J.H. A low-cost high-accuracy CMOS smart temperature sensor. In Proceedings of the 25th European
Solid-State Circuits Conference, Duisburg, Germany, 21–23 September 1999; pp. 302–305.
16. Pertijs, M.A.P.; Bakker, A.; Huijsing, J.H. A high-accuracy temperature sensor with second-order curvature correction and
digital bus interface. In Proceedings of the ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat.
No.01CH37196), Sydney, NSW, Australia, 6–9 May 2001; Volume 1, pp. 368–371. [CrossRef]
17. Sebastiano, F.; Breems, L.J.; Makinwa, K.A.A.; Drago, S.; Leenaerts, D.M.W.; Nauta, B. A 1.2V 10 µW NPN-based temperature
sensor in 65nm CMOS with an inaccuracy of ±0.2 ◦ C (3s) from −70 ◦ C to 125 ◦ C. In Proceedings of the 2010 IEEE International
Solid-State Circuits Conference—(ISSCC), San Francisco, CA, USA, 7–11 February 2010; pp. 312–313. [CrossRef]
18. Oshita, T.; Shor, J.; Duarte, D.E.; Kornfeld, A.; Zilberman, D. Compact BJT-Based Thermal Sensor for Processor Applications in a
14 nm tri-Gate CMOS Process. IEEE J. Solid-State Circuits 2015, 50, 799–807. [CrossRef]
19. Chuang, M.-C.; Tai, C.-L.; Hsu, Y.-C.; Roth, A.; Soenen, E. A temperature sensor with a 3 sigma inaccuracy of ±2 ◦ C without
trimming from −50 ◦ C to 150 ◦ C in a 16 nm FinFET process. In Proceedings of the ESSCIRC Conference 2015—41st European
Solid-State Circuits Conference (ESSCIRC), Graz, Austria, 14–18 September 2015; pp. 271–274. [CrossRef]
20. Law, M.-K.; Lu, S.; Wu, T.; Bermak, A.; Mak, P.-I.; Martins, R.P. A 1.1 µW CMOS Smart Temperature Sensor With an Inaccuracy of
±0.2 ◦ C (3σ) for Clinical Temperature Monitoring. IEEE Sens. J. 2016, 16, 2272–2281. [CrossRef]
Electronics 2024, 13, 2823 16 of 16

21. Hsu, Y.-C. An 18.75 µW Dynamic-Distributing-Bias Temperature Sensor with 0.87 ◦ C (3σ) Untrimmed Inaccuracy and 0.00946 mm2
Area. In Proceedings of the 2017 IEEE International Solid-State Circuits Conference—(ISSCC), San Francisco, CA, USA, 11–15
February 2017.
22. Bass, O.; Shor, J. A Miniaturized 0.003 mm2 PNP-Based Thermal Sensor for Dense CPU Thermal Monitoring. IEEE Trans. Circuits
Syst. I Regul. Pap. 2020, 67, 2984–2992. [CrossRef]
23. Tang, Z.; Fang, Y.; Huang, Z.; Yu, X.-P.; Shi, Z.; Tan, N.N. An Untrimmed BJT-Based Temperature Sensor With Dynamic
Current-Gain Compensation in 55-nm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 2019, 66, 1613–1617. [CrossRef]

Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual
author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to
people or property resulting from any ideas, methods, instructions or products referred to in the content.