Unit-5

Integrated Circuit Timer: Timer IC 555 pin and functional block

diagram, Monostable and Astable multivibrator using the 555 IC.

Voltage Controlled Oscillator: VCO IC 566 pin and functional block

diagram and applications.

Phase Locked Loop (PLL): Basic principle of PLL, block diagram,

working, Ex-OR gates and multipliers as phase detectors,
applications of PLL.
 Introduction to 555 Timers IC
The 555 timer is a highly stable device for generating accurate time delay or
oscillation. The 555 timer IC was introduced in the year 1970 by Signetic
Corporation and gave the name SE/NE 555 timer.

The important features of the 555 timer are:

 Wide range of power supplies ranging from + 5 Volts to + 18 Volts.
 High temperature stability.
 Sinking or sourcing 200 mA of load current.
 The duty cycle of the timer is adjustable.
 With the help of proper external components, timing intervals can be
made into several minutes and frequencies exceeding several hundred
kilohertz.
 Compatible with both transistor-transistor logic (TTL) and CMOS logic
circuit.
 Low cast, Reliable and easy to use.
 Operating temperature range from 0°C to 70°C(-55°C to +125°C--SE555)
 It has a temperature stability of 50 parts per million (ppm) per degree
Celsius change in temperature, or equivalently 0.005 %/ °C.
 The maximum power dissipation per package is 600 mW and its trigger
and reset inputs have logic compatibility. More features are listed in
the datasheet.
 Operate in two modes: 1- Monostable Mode 2- Astable Mode
The 555 Timer IC is available as an 8-pin metal can, an 8-pin mini DIP (dual-in-
package) or a 14-pin DIP. The pin configuration is shown in the figures.
Pin 1: Grounded Terminal:
All the voltages are measured with respect to the Ground terminal.
Pin 2: Trigger Terminal:
The trigger pin is used to feed the trigger input when the 555 IC is set up as a
monostable multivibrator. A negative pulse with a dc level greater than VCC/3
is applied to this terminal. In the negative edge, as the trigger passes through
VCC/3, the output of the lower comparator becomes high and the
complimentary of Q becomes zero. Thus the 555 IC output gets a high
voltage, and thus a quasi stable state.
Pin 3: Output Terminal:
Output of the timer is available at this pin. There are two ways in which a
load can be connected to the output terminal. One way is to connect
between output pin (pin 3) and ground pin (pin 1) or between pin 3 and
supply pin (pin 8). The load connected between output and ground supply
pin is called the normally on load and that connected between output and
ground pin is called the normally off load.
Pin 4: Reset Terminal:
Whenever the timer IC is to be reset or disabled, a negative pulse is applied
to pin 4, and thus is named as reset terminal. The output is reset irrespective
of the input condition. When this pin is not to be used for reset purpose, it
should be connected to + VCC to avoid any possibility of false triggering.
Pin 5: Control Voltage Terminal:
The threshold and trigger levels are controlled using this pin. The pulse width
of the output waveform is determined by connecting a POT or bringing in an
external voltage to this pin. The external voltage applied to this pin can also
be used to modulate the output waveform. Thus, the amount of voltage
applied in this terminal will decide when the comparator is to be switched,
and thus changes the pulse width of the output. When this pin is not used, it
should be bypassed to ground through a 0.01 micro Farad to avoid any noise
problem.
Pin 6: Threshold Terminal:
This is the non-inverting input terminal of comparator 1, which compares the
voltage applied to the terminal with a reference voltage of 2/3 VCC. The
amplitude of voltage applied to this terminal is responsible for the set state
of flip-flop. When the voltage applied in this terminal is greater than 2/3VCC,
the upper comparator switches to +Vsat and the output gets reset.
Pin 7: Discharge Terminal:
This pin is connected internally to the collector of transistor and mostly a
capacitor is connected between this terminal and ground. It is called
discharge terminal because when transistor saturates, capacitor discharges
through the transistor. When the transistor is cut-off, the capacitor charges
at a rate determined by the external resistor and capacitor.
Pin 8: Supply Terminal:
A supply voltage of + 5 V to + 18 V is applied to this terminal with respect to
ground (pin 1).

Functional diagram of the 555 timer:

The block diagram of a 555 timer is shown in the above figure. The 555 timer
consist of two comparators (basically 2 op-amps), an R-S flip-flop, two
transistors and a resistive network.
 Resistive network consists of three equal resistors R which acts as a
voltage divider.
 Comparator 1 (UC) compares threshold voltage with a reference
voltage + 2/3 VCC volts.
 Comparator 2 (LC) compares the trigger voltage with a reference
voltage + 1/3 VCC volts.
 In the stand by state (Stable), the output of the control FF is high.
This make output low because of power amplifier is basically an
inverter.
 A negative going trigger pulse applied to pin 2 and should have its dc
level greater than the threshold level of the lower comparator (i.e.
VCC/3). The output of lower comparator goes high and reset the FF
( = , = ).
 During positive excursion, when threshold voltage at pin 6 passes
through 2VCC/3, the output of the upper comparator goes high and
reset the FF.
 The reset input (pin 4) provides a mechanism to reset the FF in a
manner which overrides the effect of any instruction coming to FF from
lower comparator. This over riding reset is effective when the rest input
is not used, it is recommended to connect this pin to VCC.
 It is also possible to vary time electronically too, by applying a
modulating voltage to the control input terminal (pin 5). In application
where no such modulation is intended, it is recommended by
manufacturer that a capacitor (0.01µf) be connected between control
voltage terminal (pin 5) and ground to bypass noise or ripple from the
supply.
 Astable Multivibrator using to 555 Timers IC
The connection diagram of 555 timer IC which are used for astable
multivibrator operation are shown below:

For better understanding, the complete diagram of astable multivibrator

with details internal diagram of timer is shown below:
When the power supply (VCC) is connected, the external timing capacitor C
charges towards VCC with a time constant ( + ) . During this time, the
output voltage (pin 3) is high (equal to VCC) as Reset(R)=0, Set(S)=1 and this
combination make = which has unclamped the timing capacitor C.

When capacitor voltage equal to the upper comparator trigger the

control flip-flop (FF) so that = , this make transistor ON and capacitor
C starts discharge towards ground through and transistor with a time
constant .
During the discharge of timing capacitor C, as it reaches , the lower
comparator is triggered and it this stage Reset(R)=0, Set(S)=1 which make
= and thus the external capacitor C is unclamped. The capacitor C is thus
periodically charged and discharged between and respectivelly.
The timing waveform is as:

We already know that the voltage across capacitor subjected to a step input
of VCC at any time is given by following equation:
( )= + −
Where is initial voltage across capacitor and is final voltage across
capacitor.
The length of time that the output remains HIGH is the time taken by the
capacitor to charge from to . It means initial voltage across
capacitor is = and final voltage across capacitor = . Therefore

( )= + − ( )

At end of time t= , voltage across the capacitor reaches

 = + − ( )

= + − ( )

− ( )
− =

− = ( )

= ( )

= ( )

= ( )

Taking natural log on both side

( )= . ( )
( + )
So, that
= . .( + )
On the other length of time that the output remains LOW is the time taken
by the capacitor to discharge from to . It means initial voltage
across capacitor is = and final voltage across capacitor = .
Note that both & are in the charging path but only is in the
discharging path.
Therefore
( )= + − ( )

At end of time t= , voltage across the capacitor reaches

= ( )

= ( )
 = ( )

= ( )

Taking natural log on both side

( )= . ( )
( )
So, that
= . .
Hence the total time period
= = +
= = . .( + ) + . .
= . .( + )
And the frequency
.
= = =
. .( + ) ( + )
Duty cycle(D) is defined as the ratio of ON time to total time period i.e.
( ) ( ) . .( + )
%= = =
+ . .( + ) + . .
( + ) ( + )
%= =
( + ) + ( + )
Q: 1- For the Astable Multivibrator, = . Ω, = Ω and = μ .
Determine
a) The positive pulse width “ ”
b) The positive pulse width “ ”
c) Free running frequency “f0”
d) Duty Cycle “D”
Q: 2- Design an Astable Multivibrator using 555 timers to generate an output
waveform of 2 kHz with a duty cycle of 60%.
Q: 3- Design an Astable Multivibrator using 555 timers to generate an output
waveform of 5 kHz with a duty cycle of 40%.
 Astable Multivibrator to generate Square wave
( )
For the expression of duty cycle (D) i.e. =( )
, it is not possible to
obtain a duty cycle exactly 50%. Because = . ( + ) will
always be greater than = . . . In order to obtain a symmetrical
square wave i.e. D=50% the resistance must be reduce to zero. By doing
the pin 7 is directly connected to VCC and extra current will flow through Q 1
and when it is ON excess current may damage Q 1 and hence the timer.
An alternative circuit which will allow duty to be set at any level as:

During charging cycle diode D is forward biased which effectively short

circuiting resistor , so that

= .
However, during discharging cycle diode D is reverse biased, hence capacitor
discharge only with resistor , so that

= .
Hence the total time period
= = +
= = . + .
= = . ( + )
And the frequency
.
= = =
. ( + ) ( + )
Duty cycle (D)
( ) ( ) .
= = =
+ . + .

=
( + )
= =

= = = %
( + )

Q: 4- Design an Astable Multivibrator using 555 timers to generate a square

waveform of 1 kHz.
 Monostable Multivibrator using to 555 Timers IC
The connection diagram of 555 timer IC which are used for monostable
multivibrator operation are shown below:

For better understanding, the complete diagram of monostable multivibrator

with details internal diagram of timer is shown below:
A monostable multivibrator often called a one-shot multivibrator, is a pulse
generator circuit in which the duration of the pulse is determined by the R-C
network, connected externally to the 555 timer.
In standby mode, Flip-flop holds transistor Q1 ON which clamped external
capacitor C to ground, and the output remains at ground potential i.e. LOW.
When we apply a trigger pulse which passes through , the FF is set i.e.
( = , = ). This makes transistor Q1 OFF and the short circuit across the
timing capacitor C is released. As is LOW, the output goes HIGH. Timing
cycle now begins and voltage across capacitor exponentially rises through R
towards with a time constant RC as illustrated in following figure-

After a time period T the when capacitor voltage just greater than and
the upper comparator reset the FF i.e. ( = , = ), the transistor Q1 ON
and capacitor discharge towords the ground potential. The output returns to
the standby state or ground potential.
In other words, the RC time constant controls the width of the output pulse.
The time during which the timer output remains high is given as
Voltage across the capacitor at any instant during charging period is given as
( )= + −
Where is initial voltage across capacitor and is final voltage across
capacitor. Form waveform initial voltage across capacitor is = and final
voltage across capacitor = . Therefore
( )= −
At end of time t= , voltage across the capacitor reaches ( )=

= −

= −

= − =

=
Taking natural log on both side

= .

So pulse width = .
Form above equation it is clear that with the help of R and C, the pulse width
of the circuit may range from micro-seconds to many seconds. This circuit is
widely used in industry for many different timing applications.

Q: 1- In monostable multivibrator, = . Ω = μ . Find the pulse

width T.
Q: 2- Design an Astable Multivibrator using 555 timers to generate a pulse
width of 10mSec.

Applications of 555 Timers IC

a) Monostable and Astable multivibrator
b) Oscillator
c) Ramp and Square wave generator
d) Pulse generation
e) Burglar Alarms and Toxic Gas alarms
f) DC-DC Converters(Voltage Regulators)
g) Temperature measurements and control devices
 Voltage Controlled Oscillator (VCO)
Voltage controlled oscillator is a type of oscillator where the frequency of the
output oscillations can be varied by varying the amplitude of an input voltage
signal. The block diagram of a typical voltage controlled oscillator is shown
below.

Voltage controlled oscillators can be broadly classified into a linear voltage

controlled oscillators and relaxation type voltage controlled oscillators.
 Linear voltage controlled oscillators are generally used to produce a
sine wave. In such oscillators, an LC tank circuit is used for producing
oscillations. An active element like a transistor is used for amplifying
the output of the LC tank circuit, compensating the energy lost in the
tank circuit and for establishing the necessary feedback conditions.
 Relaxation-type voltage controlled oscillators are used to produce a
sawtooth or triangular waveform. This is achieved by the gradual
charging and sudden discharge of a capacitor connected appropriately
to an active element (UJT, PUT etc) or a monolithic IC (LM566 etc).
Nowadays relaxation type VCOs are generally realized using monolithic
ICs.
A common type of VCO available in IC form is Signetics NE/SE566, which
provides simultaneous square wave and triangular wave as a function of
input voltage. The pin configuration and basic block diagram of 566 VCO are
shown in figures below.
From the above figure, the timing capacitor C1 is linearly charged or
discharged by a constant current source/sink. The amount of current can be
controlled by changing the voltage VC applied at the modulating input (pin 5)
or by changing the timing resistor R1 external to the IC chip.
The voltage at pin 6 is held at the same voltage as pin 5. Thus, if the
modulating voltage at pin 5 is increased, the voltage at pin 6 also increases,
resulting in less voltage across R1 and thereby decreasing the charging
current.
The voltage across the capacitor C1 is applied to the inverting input terminal
of Schmitt trigger via buffer amplifier. The output voltage swing of the
Schmitt trigger is designed to VCC and 0.5 VCC. If Ra = Rb in the positive
feedback loop, the voltage at the non-inverting input terminal of Schmitt
trigger swings from 0.5 VCC to 0.25 VCC.
When the voltage on the capacitor C1 exceeds 0.5 VCC during charging, the
output of the Schmitt trigger goes LOW (0.5Vcc). The capacitor now
discharges and when it is at 0.25 VCC, the output of Schmitt trigger goes HIGH
(Vcc). Since the source and sink currents are equal, capacitor charges and
discharges for the same amount of time. This gives a triangular voltage
waveform across C1 which is also available at pin 4. The output of Schmitt
trigger i. e square wave goes through buffer amplifier and is available at pin
3.
The output waveforms are shown at the pins 4 and 3 as:

The output frequency of the VCO can be given as follows:

From the wave form the Capacitor charge from 0.25VCC to 0.5 VCC and
discharge from 0.5VCC to 0.25 VCC with constant source/sink current. Hence
time taking by capacitor to changing and discharging as:
∆
=
∆
 .
=
∆
. .
∆ =
The time period T of the triangular waveform = ∆
The frequency of oscillator is

= = = =
∆ ∗ . . . .
But we know that
−
=
( − )
=

From the above expression, the frequency of VCO can be changed either:
a) either by
b) either by
c) or by control voltage
The control voltage can be varied by connecting a resistance and
as shown in following figure:

The components R1 and C1 are first selected so that VCO output frequency
lies in the centre of the operating frequency range, now with the help of
modulating input voltage, frequency of out can be varied of about 10 to 1.
VCO are commonly used in frequency (FM), pulse (PM) modulators and
phase locked loops (PLL).
 Phase Locked Loop (PLL)
The phase-locked loop or phase lock loop (PLL) is a closed loop system. Its
applications are to lock its output frequency and phase to the frequency and
phase of the input signal. PLLs are available as inexpensive monolithic ICs.
This techniques for electronics frequency control is used today in satellite
communication, navigation system, FM communication system etc.
Although the evolution of phase lock loop begin in early 1930s, its cost
outweighed its advantage at first with the rapid development of integrated
circuit technology, the phase lock loop has emerged as one of the
fundamental building blocks in electronics technology.
Basic PLL Operation
The PLL circuit is basically used to tracking a particular system. It
synchronizes its output with input signal in terms of frequency and phase.
The state of synchronization between input and output is called as the locked
state. In locked state the phase error between the input and output is
minimum. Thus phase of the output signal is locked to that of the input
signal. Hence name phased locked loop.
The block diagram of PLL is shown in the following figure −

A Phase Locked Loop (PLL) mainly consists of the following three blocks −

 Phase Detector/ Comparator

 Active Low Pass Filter
 Amplifier or Error Amplifier
 Voltage Controlled Oscillator (VCO)
The working of a PLL is as follows −
 The phase detector or comparator compares the input frequency ( )
with the feedback frequency ( ) and generate a DC voltage(error),
which is proportional to the phase difference between the input signal
having input frequency ( ) and feedback frequency( ).
 The output of the phase detector is applied to the Low Pass Filter
which eliminating high frequency component presents in the output
of the phase detector and produce a dc level. It also amplifies the
signal.
 This dc voltage is applied at the input of VOC. The VCO start oscillating
and generate frequency which is directly proportional to the input dc
level. This frequency is again applied to the phase detector, phase
detector again compare it with input frequency and adjusted until it is
equal to the input frequency.
 A VCO produces a signal having a certain frequency, when there is no
input applied to it. This frequency can be shifted to either side by
applying a DC voltage to it. Therefore, the frequency deviation is
directly proportional to the DC voltage present at the output of a low
pass filter.
The above operations take place until the VCO frequency equals to the input
signal frequency. Based on the type of application, we can use either the
output of active low pass filter or output of a VCO. PLLs are used in
many applications such as FM demodulator, clock generator etc.
PLL operates in one of the following three modes −

 Free running mode

 Capture mode
 Lock mode
Initially, PLL operates in free running mode when no input is applied to it.
When an input signal having some frequency is applied to PLL, then the
output signal frequency of VCO will start change. At this stage, the PLL is
said to be operating in the capture mode. The output signal frequency of
VCO will change continuously until it is equal to the input signal frequency.
Now, it is said to be PLL is operating in the lock mode.
Some Important definition related to PLL:
[1]. Lock-in Range
The range of frequency over which the PLL can maintain lock with the
incoming signal is called Lock-in range or tracking range. The lock range is
usually expressed as percentage of VCO frequency( ).

[2]. Capture Range

The range of frequency over which the PLL can acquire lock with the
incoming signal is called Capture range. Capture range is also expressed as
percentage of VCO frequency( ).
[3]. Pull-in-time
The total time taken by the PLL to establish lock is called Pull-in time. This
depends on the initial phase and frequency difference between the two
signals as well as on the overall loop gain and loop filter characteristics.
(a)- Phase Detector/ Comparator

The phase detector is the important part of the PLL system. The phase
detector compares the input frequency and VCO frequency and generates a
dc voltage that is proportional to the phase difference between the two
frequencies.

A double balanced mixer is a classical example of analog phase detector, on

the other hand the example of digital phase detector are:

a. Exclusive-OR Phase detector

b. Edge triggered Phase detector

Exclusive-OR Phase detector

Detector that are used exclusive-OR gate is called as X-OR phase detector. A
typical XOR gate is shown as:

The output of the XOR gate is HIGH when only one of the input signals or
is high. This types of detector is used when both input signal are square
wave.
The input and output waveform = are shown above. In this figure
leading by phase angle φ degree. The variation dc output voltage
with phase difference φ is as:

From graph, it can be seen that the maximum dc output voltage occurs when
the phase difference is π because the output of the gate remains high
throughout.

The slope of the curve gives the conversion ratio ∅ of the phase detector
that is

∅ =
And for =

∅ = = . /
It can be seen that using these waveforms, the XOR logic gate can be used as
a simple but effective phase detector.
 Multiplier as Phase detector
Analog Multiplier can also be used for phase detector as

Consider the two input signal as:

= (1)
= ( + ∅) (2)
= . ( + ∅)
= [ ∅− ( + ∅)]

= ∅− ( + ∅)
The first terms is dc for phase difference of φ while the second term varies
with time and it is filter out by low pass filter and at filter output we get only
dc voltage. From above equation-
°
= , =

°
= , =
√

°
= , =
 Monolithic Phase Locked Loops (PLL IC 565)
The Signetics NE/SE 560 series is monolithic phase locked loops. The SE/NE
560, 561, 562, 564, 565 & 567 differ mainly in operating frequency range,
poser supply requirements & frequency & bandwidth adjustment ranges.

Pin Configuration of PLL IC 565:

Basic Block Diagram Representation of IC 565

 The important electrical characteristics of the 565 PLL are,

 Operating frequency range: 0.001Hz to 500 Khz.

 Operating voltage range: ±6 to ±12v
 Input level required for tracking: 10mv rms min to 3 Vpp max
 Input impedance: 10 K ohms typically.
 Output sink current: 1mA
 Output source current: 10 mA
The centre frequency of the PLL is determined by the free running frequency
of the VCO, which is given by
.
=

where R1 & C1 are an external resistor & a capacitor connected to pins 8 & 9.

 The VCO free-running frequency fOUT is adjusted externally with R1 & C1

to be at the center of the input frequency range.
 C1 can be any value, R1 must have a value between 2 k ohms and 20 K
ohms.
 Capacitor C2 connected between 7 & +V.
 The filter capacitor C2 should be large enough to eliminate variations in
the demodulated output voltage in order to stabilize the VCO frequency.
 The lock range fL & capture range fc of PLL is given by,

=±

Where = free running frequency of VCO (Hz) and = (+ ) − (− )

/
=±
( )( . ) ∗
 Application of Phase Locked Loops (PLL)
Phase Locked Loops (PLL) is a versatile device. It has a numerous application,
some of the typical applications of PLL are discussed below:

[1]. Frequency Multiplier/Divisions

[2]. Frequency Translation
[3]. AM Detection
[4]. FM Detection
[5]. Frequency Shift Keying(FSK)
Frequency Multiplier/Divisions
The block diagram of frequency multiple using PLL are shown below:

In this a Frequency divider is inserted between the VCO & phase comparator.
Since the output of the divider is locked to the , VCO is actually running at
a multiple of the input frequency.
=
The desired amount of multiplication can be obtained by selecting a proper
divide-by-N network, where N is an integer.

Frequency Translation
The frequency shifting of an oscillator using a small factor is known as a
frequency translator. The block diagram of the frequency translator using PLL
is shown following figure.
The block diagram can be built with a mixer, LPF, and the phase-locked loop.
The (input frequency) which has to be transferred is applied to the mixer.
Other i/p of the mixer is the output voltage of VCO that is . As a result, the
output of the mixer includes the difference signal and sum ( ± ).
The LPF which is connected to the mixer’s o/p discards the ( + ) signal &
provides the signal like ( − ) at the o/p. The signal like ( − ) can be
applied toward the phase detector. The offset frequency is i/p of the
detector. In the locked mode, the o/p frequency of VCO can be regulated to
make 2- input frequencies of phase detector equivalent. This gives,
( − )=
= +
By regulating (offset frequency) can move the oscillator’s frequency to the
preferred value.

AM Demodulator
A PLL may be used to demodulate AM signals as shown in the figure below.

The PLL is locked to the carrier frequency of the incoming AM signal. The
output of VCO which has the same frequency as the carrier, but unmodulated
is fed to the multiplier. Since VCO output is always 90˚ before being fed to
the multiplier. This makes both the signals applied to the multiplier and the
difference signals, the demodulated output is obtained after filtering high
frequency components by the LPF. Since the PLL responds only to the carrier
frequencies which are very close to the VCO output, a PLL AM detector
exhibits high degree of selectivity and noise immunity which is not possible
with conventional peak detector type AM modulators.
 FM Demodulator
A PLL may be used to demodulate FM signals as shown in the figure below.

If PLL is locked to a FM signal, the VCO tracks the instantaneous frequency of

the input signal. The filtered error voltage which controls the VCO and
maintains lock with the input signal is the demodulated FM output. The VCO
transfer characteristics determine the linearity of the demodulated output.
Since, VCO used in IC PLL is highly linear, it is possible to realize highly linear
FM demodulators.

Frequency Shift Keying (FSK) demodulator:

FSK demodulator is a very beneficial application of the 565 PLL. In this, the
frequency shift is generally proficient by motivating a VCO with the binary
data signal. So that the two subsequent frequencies resemble the logic 0 & 1
states of the binary data signal. These frequencies corresponding to two
states are generally called the mark and space frequencies. Numerous values
are used to set the mark & space frequencies.
An FSK signal demodulator can be made as shown in the figure. The
demodulator gets a signal at one of the two separate carrier frequencies
mark or space, respectively. The capacitive connection is used as the i/p to
eliminate a DC level.
The signal is applied at input, the loop locks to the input frequency and track
it between the two frequencies with a corresponding dc shift at the output.

The 3-stage RC ladder filter is used to remove the carrier component and the
output signal is made logic compatible by voltage comparator.