Si4730/31/34/35-D60

B ROADCAST AM/FM/SW/LW R ADIO R ECEIVER

Features
 Worldwide FM band support  Multiplexed stereo audio AUXIN
(64–108 MHz) ADC with 85 dB dynamic range
 Worldwide AM band support  Seven selectable AM channel filters
(520–1710 kHz)  AM/FM/SW/LW digital tuning
 SW band support (Si4734/35)  EN55020 compliant
(2.3–26.1 MHz)  No manual alignment necessary
 LW band support (Si4734/35)  Programmable reference clock
(153–279 kHz)  Adjustable soft mute control
 Excellent real-world performance  RDS/RBDS processor (Si4731/35)
 Integrated VCO  Digital audio out
 Advanced AM/FM seek tuning  2-wire and 3-wire control interface Ordering Information:
 Automatic frequency control (AFC)  Integrated LDO regulator See page 33.
 Automatic gain control (AGC)  Wide range of ferrite loop sticks and
 Digital FM stereo decoder air loop antennas supported Pin Assignments
 Programmable de-emphasis  QFN and SSOP packages
 Advanced Audio Processing RoHS compliant
Si473x-D60 (QFN)

GPO3/[DCLK]
GPO2/[INT]

DFS/[RIN]
Applications

GPO1
NC
 Table and portable radios  Modules for consumer electronics NC 1 20 19 18 17 16
FMI 2 15 DOUT/[LIN]
 Mini/micro systems  Clock radios RFGND 3 14 LOUT/[DFS]
GND
 CD/DVD and Blu-ray players  Mini HiFi and docking stations AMI 4 PAD 13 ROUT/[DOUT]

 Stereo boom boxes  Entertainment systems RST 5 12 GND

6 7 8 9 10 11 VA

Description
SEN

SCLK

RCLK

VD
SDIO
The Si473x-D60 digital CMOS AM/FM radio receiver IC integrates the complete Si473x-D60(SSOP)
tuner function from antenna input to digital audio output and includes a stereo
DOUT/[LIN] 1 24 LOUT/[DFS]
audio AUXIN ADC input for converting analog audio into standard I2S digital
DFS/[RIN] 2 23 ROUT/[DOUT]
audio, enabling a cost efficient digital audio platform for consumer electronic
applications with high TDMA noise immunity, superior radio performance, and GPO3/[DCLK] 3 22 DBYP

high fidelity audio power amplification. When enabling the analog inputs in stereo GPO2/[INT] 4 21 VA
AUXIN ADC-mode, the Si473x-D60 supports I2S digital audio output only (no GPO1 5 20 VD
analog output). NC 6 19 RCLK
NC 7 18 SDIO
Functional Block Diagram FMI 8 17 SCLK
RFGND 9 16 SEN
FM / SW
AN T
R IN Si473x-D60 NC 10 15 RST
LIN
RD S
NC 11 14 GND
DO UT
FM I (S i4731/
35)
DIG ITA L
DFS AMI 12 13 GND
LN A AU D IO
G PO /D CLK
AGC LO W -IF

A M / LW
A NT
AMI M ux AD C DA C RO UT This product, its features, and/or its
LN A D SP
R FG N D architecture is covered by one or more of
M ux AD C DA C LO UT
2.7~5.5 V (Q FN )
AGC
the following patents, as well as other
2.0~5.5 V (SSO P) VA
CO NTR O L patents, pending and issued, both
LD O AFC VD
+ GND INTER FAC E
1.62 - 3.6 V foreign and domestic: 7,127,217;
7,272,373; 7,272,375; 7,321,324;
7,355,476; 7,426,376; 7,471,940;
RCLK

SEN

SCLK

RST
SDIO

7,339,503; 7,339,504.

Rev. 1.1 11/11 Copyright © 2011 by Silicon Laboratories Si473x-D60

Si4730/31/34/35-D60

2 Rev. 1.1
 Si4730/31/34/35-D60
TABLE O F C ONTENTS

Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1. QFN Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2. SSOP Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1. QFN/SSOP Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.4. AM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.5. SW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.6. LW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.7. Stereo Audio AUXIN ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.8. Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.9. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.10. Received Signal Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.11. Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.12. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.13. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.14. FM Hi-Cut Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.15. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.16. RDS/RBDS Processor
(Si4731/35 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.17. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.18. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.19. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.20. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.21. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.22. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.23. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.24. 2 V Operation (SSOP Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.25. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1. Si473x-D60-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.2. Si473x-D60-GU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1. Si473x-D60 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2. Si473x-D60 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Rev. 1.1 3
Si4730/31/34/35-D60
8.1. Si473x-D60 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.2. Si473x-D60 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
9.1. Si473x-D60 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.2. Top Marking Explanation (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.3. Si473x-D60 Top Marking (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.4. Top Marking Explanation (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

4 Rev. 1.1
 Si4730/31/34/35-D60
1. Electrical Specifications

Table 1. Recommended Operating Conditions1

Parameter Symbol Test Condition Min Typ Max Unit
Analog Supply Voltage VA 2.72 — 5.5 V
Digital and I/O Supply Voltage VD 1.62 — 3.6 V
Power Supply Powerup Rise Time VDDRISE 10 — — µs
Interface Power Supply Powerup Rise Time VIORISE 10 — — µs
Ambient Temperature TA –20 25 85 C
Notes:
1. All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at
VA = 3.3 V and 25 C unless otherwise stated.
2. SSOP devices operate down to 2 V at 25 °C. See section “4.24. 2 V Operation (SSOP Only)” for details.

Rev. 1.1 5
Si4730/31/34/35-D60

Table 2. DC Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

FM Mode
VAQFN Supply Current IFMVA — 8.2 9.5
VDQFN Supply Current IFMVD — 10.5 13.5
Digital Output Mode1
VASSOP Supply Current IFMVA — 18.5 21.5
VDSSOP Supply Current IFMVD — 0.15 0.6
mA
VAQFN Supply Current IFMVA — 9.1 10.3
VDQFN Supply Current IFMVD — 9.9 12.8
Analog Output Mode2
VASSOP Supply Current IFMVA — 19.1 21.3
VDSSOP Supply Current IFMVD 0.1 0.6
AM Mode
VAQFN Supply Current IAMVA — 6.5 7.5
VDQFN Supply Current IAMVD — 8.5 11.0
Digital Output Mode
VASSOP Supply Current IAMVA — 14.5 16.5
VDSSOP Supply Current IAMVD — 0.15 0.50
mA
VAQFN Supply Current IAMVA — 7.5 8.5
VDQFN Supply Current IAMVD — 8 10.2
Analog Output Mode
VASSOP Supply Current IAMVA — 15.3 17.2
VDSSOP Supply Current IAMVD — 0.1 0.4
AUXIN Mode
VAQFN Supply Current IAUXVA — 5.7 6.3
VDQFN Supply Current IAUXVD — 6.5 8.0
mA
VASSOP Supply Current IAUXVA — 0.3 0.4
VDSSOP Supply Current IAUXVD — 11.8 13.0
Powerdown
VAQFN Powerdown Current — 4 15
IAPD µA
VASSOP Powerdown Current — 9.5 15
VDQFN Powerdown Current SCLK, RCLK inactive — 3 10
IDPD µA
VDSSOP Powerdown Current SCLK, RCLK inactive — 3 10
High Level Input Voltage3 VIH 0.7 x VD — VD + 0.3 V
Low Level Input Voltage3 VIL –0.3 — 0.3 x VD V
3
High Level Input Current IIH VIN = VD = 3.6 V –10 — 10 µA
Notes:
1. Guaranteed by characterization.
2. Backwards compatible mode to rev B and rev C. Additional features on this device may increase typical supply current.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.

6 Rev. 1.1
 Si4730/31/34/35-D60
Table 2. DC Characteristics (Continued)
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

3
Low Level Input Current IIL VIN = 0 V, –10 — 10 µA
VD = 3.6 V
High Level Output Voltage4 VOH IOUT = 500 µA 0.8 x VD — — V
Low Level Output Voltage4 VOL IOUT = –500 µA — — 0.2 x VD V
Notes:
1. Guaranteed by characterization.
2. Backwards compatible mode to rev B and rev C. Additional features on this device may increase typical supply current.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.

Rev. 1.1 7
Si4730/31/34/35-D60

Table 3. Reset Timing Characteristics1,2,3

(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Min Typ Max Unit

RST Pulse Width and GPO1, GPO2/INT Setup to RST tSRST 100 — — µs

GPO1, GPO2/INT Hold from RST tHRST 30 — — ns

Important Notes:
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
3. When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum tSRST is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and
GPO2 low.

tSRST tHRST

70%
RST
30%

70%
GPO1
30%

GPO2/ 70%

INT 30%

Figure 1. Reset Timing Parameters for Busmode Select

8 Rev. 1.1
 Si4730/31/34/35-D60

Table 4. 2-Wire Control Interface Characteristics1,2,3

(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

SCLK Frequency fSCL 0 — 400 kHz
SCLK Low Time tLOW 1.3 — — µs
SCLK High Time tHIGH 0.6 — — µs
SCLK Input to SDIO  Setup tSU:STA 0.6 — — µs
(START)
SCLK Input to SDIO  Hold tHD:STA 0.6 — — µs
(START)
SDIO Input to SCLK  Setup tSU:DAT 100 — — ns
SDIO Input to SCLK  Hold4,5 tHD:DAT 0 — 900 ns
SCLK input to SDIO  Setup tSU:STO 0.6 — — µs
(STOP)
STOP to START Time tBUF 1.3 — — µs
SDIO Output Fall Time tf:OUT — 250 ns
Cb
20 + 0.1 -----------
1pF

SDIO Input, SCLK Rise/Fall Time tf:IN — 300 ns

tr:IN Cb
20 + 0.1 -----------
1pF

SCLK, SDIO Capacitive Loading Cb — — 50 pF

Input Filter Pulse Suppression tSP — — 50 ns
Notes:
1. When VD = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si473x-D60 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum
tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated as long as all other timing parameters are met.

Rev. 1.1 9
Si4730/31/34/35-D60

tSU:STA tHD:STA tLOW tHIGH tr:IN tf:IN tSP tSU:STO tBUF

70%
SCLK
30%

70%
SDIO
30%

START tHD:DAT tSU:DAT tf:IN,

tr:IN STOP START
tf:OUT

Figure 2. 2-Wire Control Interface Read and Write Timing Parameters

SCLK

A6-A0,
SDIO D7-D0 D7-D0
R/W

START ADDRESS + R/W ACK DATA ACK DATA ACK STOP

Figure 3. 2-Wire Control Interface Read and Write Timing Diagram

10 Rev. 1.1
 Si4730/31/34/35-D60

Table 5. 3-Wire Control Interface Characteristics

(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

SCLK Frequency fCLK 0 — 2.5 MHz
SCLK High Time tHIGH 25 — — ns
SCLK Low Time tLOW 25 — — ns
SDIO Input, SEN to SCLKSetup tS 20 — — ns
SDIO Input to SCLKHold tHSDIO 10 — — ns
SEN Input to SCLKHold tHSEN 10 — — ns
SCLKto SDIO Output Valid tCDV Read 2 — 25 ns
SCLKto SDIO Output High Z tCDZ Read 2 — 25 ns
SCLK, SEN, SDIO, Rise/Fall time tR, tF — — 10 ns
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.

70%
SCLK
30%

tR tF
tS tHSDIO tHIGH tLOW tHSEN
70%
SEN tS
30%

70% A6-A5,
SDIO A7 R/W, A0 D15 D14-D1 D0
30% A4-A1

Address In Data In

Figure 4. 3-Wire Control Interface Write Timing Parameters

70%
SCLK
30%

tS tHSDIO tCDV tHSEN

tCDZ
70%
SEN tS
30%

70% A6-A5,
SDIO A7 R/W, A0 D15 D14-D1 D0
30% A4-A1

Address In ½ Cycle Bus Data Out

Turnaround

Figure 5. 3-Wire Control Interface Read Timing Parameters

Rev. 1.1 11
Si4730/31/34/35-D60

Table 6. Digital Audio Interface Characteristics

(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

DCLK Cycle Time tDCT 26 — 1000 ns
DCLK Pulse Width High tDCH 10 — — ns
DCLK Pulse Width Low tDCL 10 — — ns
DFS Set-up Time to DCLK Rising Edge tSU:DFS 5 — — ns
DFS Hold Time from DCLK Rising Edge tHD:DFS 5 — — ns
DOUT Propagation Delay from DCLK Falling tPD:DOUT 0 — 50 ns
Edge

tDCH tDCL

DCLK

tDCT

DFS
tHD:DFS tSU:DFS

DOUT
tPD:OUT

Figure 6. Digital Audio Interface Timing Parameters, I2S Mode

12 Rev. 1.1
 Si4730/31/34/35-D60

Table 7. FM Receiver Characteristics1,2

(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Input Frequency fRF 76 — 108 MHz
Sensitivity3,4,5,6 (S+N)/N = 26 dB — 2.2 3.5 µV EMF
RDS Sensitivity6,7 f = 2 kHz, — 10 — µV EMF
RDS BLER < 5%
LNA Input Resistance7,8 3 4 5 k
7,8
LNA Input Capacitance 4 5 6 pF
Input IP37,9 100 105 — dBµV EMF
AM Suppression3,4,7,8 m = 0.3 40 50 — dB
Adjacent Channel Selectivity ±200 kHz 35 50 — dB
Alternate Channel Selectivity ±400 kHz 60 70 — dB
Spurious Response Rejection7 In-band 35 — — dB
3,4,8 72 80 90 mVRMS
Audio Output Voltage
3,8,10 — — 1 dB
Audio Output L/R Imbalance
Audio Frequency Response Low7 –3 dB — — 30 Hz
Audio Frequency Response High7 –3 dB 15 — — kHz
8,10 35 42 — dB
Audio Stereo Separation
Audio Mono S/N3,4,5,8 55 63 — dB
Audio Stereo S/N4,5,7,8 — 58 — dB
Audio THD3,8,10 — 0.1 0.5 %
7
De-emphasis Time Constant FM_DEEMPHASIS = 2 70 75 80 µs
FM_DEEMPHASIS = 1 45 50 54 µs
3,4,5,6,7,11, 12
Blocking Sensitivity f = ±400 kHz — 34 — dBµV
f = ±4 MHz — 30 — dBµV
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. f = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Analog audio output mode.
7. Guaranteed by characterization.
8. VEMF = 1 mV.
9. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled.
10. f = 75 kHz.
11. Sensitivity measured at (S+N)/N = 26 dB.
12. Blocker Amplitude = 100 dBuV.
13. At temperature (25 °C).
14. At LOUT and ROUT pins.

Rev. 1.1 13
Si4730/31/34/35-D60
Table 7. FM Receiver Characteristics1,2 (Continued)
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Intermod Sensitivity3,4,5,6,7,11,12 f = ±400 kHz, ±800 kHz — 40 — dBµV
f = ±4 MHz, ±8 MHz — 35 — dBµV
Audio Output Load Resistance7,11,14 RL Single-ended 10 — — k
Audio Output Load
CL Single-ended — — 50 pF
Capacitance7,11,14
Seek/Tune Time7 RCLK tolerance — — 60 ms/channel
= 100 ppm
Powerup Time7 From powerdown — — 110 ms
RSSI Offset12,13 Input levels of 8 and –3 — 3 dB
60 dBµV at RF Input
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. f = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Analog audio output mode.
7. Guaranteed by characterization.
8. VEMF = 1 mV.
9. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled.
10. f = 75 kHz.
11. Sensitivity measured at (S+N)/N = 26 dB.
12. Blocker Amplitude = 100 dBuV.
13. At temperature (25 °C).
14. At LOUT and ROUT pins.

14 Rev. 1.1
 Si4730/31/34/35-D60

Table 8. 64–75.9 MHz Input Frequency FM Receiver Characteristics1,2,3

(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Input Frequency fRF 64 — 75.9 MHz
Sensitivity4,5,6,8 (S+N)/N = 26 dB — 3.5 — µV EMF
LNA Input Resistance3,7 3 4 5 k
3,7
LNA Input Capacitance 4 5 6 pF
9
Input IP3 — 105 — dBµV EMF
AM Suppression3,4,5,7 m = 0.3 — 50 — dB
Adjacent Channel Selectivity ±200 kHz — 50 — dB
Alternate Channel Selectivity ±400 kHz — 70 — dB
Audio Output Voltage4,5,7 72 80 90 mVRMS
Audio Output L/R Imbalance4,7,10 — — 1 dB
3 –3 dB — — 30 Hz
Audio Frequency Response Low
3 –3 dB 15 — — kHz
Audio Frequency Response High
Audio Mono S/N4,3,5,7,11 — 63 — dB
Audio THD4,7,10 — 0.1 — %
De-emphasis Time Constant FM_DEEMPHASIS = 2 70 75 80 µs
FM_DEEMPHASIS = 1 45 50 54 µs
Audio Output Load Resistance3,11 RL Single-ended 10 — — k
Audio Output Load Capacitance3,11 CL Single-ended — — 50 pF
3
Seek/Tune Time RCLK tolerance — — 60 ms/channel
= 100 ppm
Powerup Time3 From powerdown — — 110 ms
12
RSSI Offset Input levels of 8 and –3 — 3 dB
60 dBµV EMF
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. Guaranteed by characterization.
4. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
5. f = 22.5 kHz.
6. BAF = 300 Hz to 15 kHz, A-weighted.
7. VEMF = 1 mV.
8. Analog output mode.
9. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled.
10. f = 75 kHz.
11. At LOUT and ROUT pins.
12. At temperature (25 °C).

Rev. 1.1 15
Si4730/31/34/35-D60

Table 9. AM/SW/LW Receiver Characteristics1,2

(VA = 2.7 to 5.5 V, VA = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Input Frequency fRF Long Wave (LW) 153 — 279 kHz
Medium Wave (AM) 520 — 1710 kHz
Short Wave (SW) 2.3 — 26.1 MHz
3,4,5
Sensitivity (S+N)/N = 26 dB — 25 35 µV EMF
Large Signal Voltage Handling5,6 THD < 8% — 300 — mVRMS
5
Power Supply Rejection Ratio ∆VDD = 100 mVRMS, 100 Hz — 40 — dB
Audio Output Voltage3,7 54 60 67 mVRMS
3,4,7
Audio S/N — 60 — dB
Audio THD3,7 — 0.1 0.5 %
5,8
Antenna Inductance Long Wave (LW) — 2800 — µH
Medium Wave (AM) 180 — 450 µH
5
Powerup Time From powerdown — — 110 ms
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 520 kHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 30% modulation, 2 kHz channel filter.
4. BAF = 300 Hz to 15 kHz, A-weighted.
5. Guaranteed by characterization.
6. See “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure” for evaluation method.
7. VIN = 5 mVrms.
8. Stray capacitance on antenna and board must be < 10 pF to achieve full tuning range at higher inductance levels.

16 Rev. 1.1
 Si4730/31/34/35-D60

Table 10. AC Receiver Characteristics—AUXIN Analog to Digital Converter

(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Total Harmonic Distortion + THD+N f = 1 kHz; — 0.035 0.06 %
Noise measured 20 Hz—20 kHz
Dynamic Range/Signal to Noise SNR f = 1 kHz at –60 dBFS — 85 — dB
Ratio A-weighted
f = 1 kHz at –60 dBFS — 78 — dB
non-weighted
Crosstalk f = 1 kHz with 3% Bandpass — 90 — dB
filter
Gain Mismatch — 0.03 — dB
Gain Drift — 100 — PPM/°C
Input Sample Rate FS — 48 — kHz
Input Voltage VAI — — 1.8 Vpkpk
Input Resistance RAI LIATTEN[1:0] — 60 — k
Input Capacitance CAI — 10 — pF

Table 11. Digital Filter Characteristics—AUXIN Analog to Digital Converter

(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Passband Frequency Response –0.1 dB 0.02 — 20 kHz
Passband Ripple 20—20 kHz –0.1 — 0.1 dB
Stopband Corner Frequency 25 — — kHz
Stopband Attenuation 70 — — dB

Rev. 1.1 17
Si4730/31/34/35-D60

Table 12. Reference Clock and Crystal Characteristics

(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Reference Clock
RCLK Supported Frequencies1 31.130 32.768 40,000 kHz
2
RCLK Frequency Tolerance –100 — 100 ppm
REFCLK_PRESCALE 1 — 4095
REFCLK 31.130 32.768 34.406 kHz
Crystal Oscillator
Crystal Oscillator Frequency — 32.768 — kHz
Crystal Frequency Tolerance2 –100 — 100 ppm
Board Capacitance — — 3.5 pF
ESR — — 50 
CL3 7 12 22 pF
CL–single ended3 14 24 44 pF
Notes:
1. The Si473x-D60 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK
frequencies between 31.130 kHz and 40 MHz that are not supported. For more details, see Table 6 of “AN332: Si47xx
Programming Guide”.
2. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing and AM seek/tune in SW
frequencies.
3. Guaranteed by characterization.

Table 13. Thermal Conditions

Parameter Symbol Min Typ Max Unit

Thermal Resistance* JA — 80 — °C/W
Ambient Temperature TA –15 25 85 °C
Junction Temperature TJ — — 92 °C
*Note: Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad.

18 Rev. 1.1
 Si4730/31/34/35-D60

Table 14. Absolute Maximum Ratings1,2

Parameter Symbol Value Unit

Analog Supply Voltage VA –0.5 to 5.8 V
Digital and I/O Supply Voltage VD –0.5 to 3.9 V
Input Current3 IIN 10 mA
3
Input Voltage VIN –0.3 to (VIO + 0.3) V
Operating Temperature TOP –40 to 95 C
Storage Temperature TSTG –55 to 150 C
RF Input Level4 0.4 Vpk
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si473x-D60 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins DFS, SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2, GPO3, and DCLK.
4. At RF input pins FMI and AMI.

Rev. 1.1 19
Si4730/31/34/35-D60
2. Typical Application Schematic
2.1. QFN Typical Application Schematic

Optional: Digital Audio Out

16 C7
DFS RIN OPMODE: 0xB0, 0xB5
15 C8
DOUT LIN

17 R3
GP03/DCLK DCLK
R2 C9
14 GPO1
LOUT DFS
13 R1 GPO2/INT
ROUT DOUT R3
GPO3/DCLK
Si473x
R2
DFS
C9
Optional: AUXIN/Digital Audio Out R1

20

19

18

17

16
DOUT
OPMODE: 0x5B, 0x0B

NC

GPO1

GPO2/INT

GPO3/DCLK

DFS
1 NC 15
DOUT
FM Antenna C2 2 14
FMI LOUT LOUT
3 13
RFGND ROUT
L1 4
Si473x 12
ROUT
AMI D60 GND
C3 5 11 2.7 to 5.5 V
RSTB VA VA
C1
SENB

RCLK
SCLK

SDIO

VD
10
6

1.62 to 3.6 V
VD
RSTB C4
RCLK

SDIO

SCLK

SENB
Optional: AM Air Loop Antenna
L2
2
1

GPO3 RCLK

T1 1 C3 X1
AMI
C5 C6
3
RFGND
Optional: For Crystal OSC

Notes:
1. Place C1 close to VA pin and C4 close to VD pin.
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface.
6. Place Si473x-D60 as close as possible to antenna and keep the FMI and AMI traces as short as possible.

20 Rev. 1.1
 Si4730/31/34/35-D60
2.2. SSOP Typical Application Schematic

2 C7
DFS RIN
1 C8
DOUT LIN

3 R3
GP03/DCLK DCLK
24 R2
LOUT DFS
23 R1
Optional: Digital Audio Out ROUT DOUT
OPMODE: 0xB0, 0xB5 Si473x

C9
C9 Optional: AUXIN/Digital Audio Out
OPMODE: 0x5B, 0x0B

R1 1 24
DOUT DOUT LOUT LOUT
R2 2 23
DFS DFS ROUT ROUT
R3 3 22
GPO3/DCLK GPO3/DCLK DBYP
4
GPO2/INT
D60 VA
21 C1
GPO2/INT 2.0 to 5.5 V
5 20 VA 1.62 to 3.6 V
GPO1 GPO1 VD VD
6 NC 19
RCLK RCLK C4
Si473x

7 NC 18
SDIO SDIO
FM Antenna C2 8 17
FMI SCLK SCLK
9 16
RFGND SENB SENB
10 NC 15
RSTB RSTB
L1
11 NC GND 14
C3 12 GND 13
AMI

Optional: AM Air Loop Antenna

L2
2
1

GPO3 RCLK

T1 1 C3 X1
AMI
C5 C6
3
RFGND
Optional: For Crystal OSC

Notes:
1. Place C1 close to VA and C4 close to VD pin.
2. All grounds connect directly to GND plane on PCB.
3. Pins 6 and 7 are no connects, leave floating.
4. Pins 10 and 11 are unused. Tie these pins to GND.
5. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
6. Pin 8 connects to the FM antenna interface, and pin 12 connects to the AM antenna interface.
7. Place Si473x-D60 as close as possible to antenna and keep the FMI and AMI traces as short as possible.

Rev. 1.1 21
Si4730/31/34/35-D60
3. Bill of Materials
3.1. QFN/SSOP Bill of Materials

Table 15. Si473x-D60 QFN/SSOP Bill of Materials

Component(s) Value/Description Supplier
C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R Murata
C2 Coupling capacitor, 1 nF, ±20%, Z5U/X7R Murata
C3 Coupling capacitor, 0.47 μF, ±20%, Z5U/X7R Murata
C4 Supply bypass capacitor, 100 nF, 10%, Z5U/X7R Murata
L1 Ferrite loop stick, 180–450 μH Jiaxin
U1 Si47xx AM/FM Radio Tuner Silicon Laboratories
Optional Components
C5, C6 Crystal load capacitors, 22 pF, ±5%, COG Venkel
(Optional for crystal oscillator)
C7 Coupling capacitor, 0.39 μF, ±20%, Z5U/X7R Murata
(Optional for AUXIN)
C8 Coupling capacitor, 0.39 μF, ±20%, Z5U/X7R Murata
(Optional for AUXIN)
C9 Noise mitigating capacitor, 2~5 pF Murata
(Optional for digital audio)
R1 Resistor, 600 Ω Venkel
(Optional for digital audio)
R2 Resistor, 2 kΩ Venkel
(Optional for digital audio)
R3 Resistor, 2 kΩ Venkel
(Optional for digital audio)
L2 Air Loop, 10-20 µH Jiaxin
(Optional for AM Input)
T1 Transformer, 1:5 turns ratio Jiaxin, UMEC
(Optional for AM Input)
X1 32.768 kHz crystal Epson
(Optional for crystal oscillator)

22 Rev. 1.1
 Si4730/31/34/35-D60
4. Functional Description
4.1. Overview

FM / SW
ANT
RIN
LIN
Si473x-D60
RDS DOUT
FMI (Si4731/
DIGITAL
LNA 35) DFS
AUDIO
GPO/DCLK
AGC LOW-IF

AM / LW AMI Mux ADC DAC ROUT

ANT LNA DSP
RFGND
Mux ADC DAC LOUT
AGC

2.7~5.5 V VA
CONTROL
LDO AFC VD
GND INTERFACE
1.62~3.6 V

RST
RCLK

SEN

SCLK

SDIO
Figure 7. Functional Block Diagram
The Si473x-D60 CMOS AM/FM radio receiver IC audio processing.
integrates the complete tuner function from antenna In addition, the Si473x-D60 provides analog and digital
input to audio output, including a stereo audio AUXIN audio outputs and a programmable reference clock. The
ADC input for converting analog audio to digital signals. device supports I2C-compatible 2-wire control interface,
This feature enables a cost-efficient digital audio and a Si4700/01 backwards-compatible 3-wire control
platform for consumer electronics applications with high interface.
cell phone noise immunity, superior radio performance,
The Si473x-D60 utilizes digital signal processing to
and high fidelity audio power amplification. Offering
achieve high fidelity, optimal performance, and design
unmatched integration and PCB space savings, the
flexibility. The chip provides excellent pilot rejection,
Si473x-D60 requires only a few external components
selectivity, and unmatched audio performance, and
and less than 15 mm2 of board area, excluding the
offers both the manufacturer and the end-user
antenna inputs. The Si473x-D60 AM/FM radio provides
extensive programmability and a better listening
the space savings and low power consumption
experience.
necessary for portable devices while delivering the high
performance and design simplicity desired for all The Si4731/35 incorporates a digital signal processor
AM/FM solutions. for the European Radio Data System (RDS) and the
North American Radio Broadcast Data System (RBDS)
Leveraging Silicon Laboratories' proven and patented
including all required symbol decoding, block
Si4700/01 FM tuner's digital low intermediate frequency
synchronization, error detection, and error correction
(low-IF) receiver architecture, the Si473x-D60 delivers
functions. Using this feature, the Si4731/35 enables
superior RF performance and interference rejection in
broadcast data such as station identification and song
the AM, FM, SW, and LW bands. The high level of
name to be displayed to the user.
integration and complete system production test
simplifies design-in, increases system quality, and
improves reliability and manufacturability.
The Si473x-D60 is a feature-rich solution that includes
advanced seek algorithms, soft mute, auto-calibrated
digital tuning, FM stereo processing and advanced

Rev. 1.1 23
Si4730/31/34/35-D60
4.2. Operating Modes optimize sensitivity and rejection of strong interferers
allowing better reception of weak stations.
The Si473x-D60 operates in either an FM receive, AM
receive, or audio AUXIN ADC mode. In FM mode, radio The Si473x-D60 provides highly-accurate digital AM
signals are received on FMI and processed by the FM tuning without factory adjustments. To offer maximum
front-end circuitry. In AM mode, radio signals are flexibility, the receiver supports a wide range of ferrite
received on AMI and processed by the AM front-end loop sticks from 180–450 µH. An air loop antenna is
circuitry. In audio AUXIN ADC mode, stereo audio supported by using a transformer to increase the
signals on LIN/RIN are sampled, converted to digital, effective inductance from the air loop. Using a 1:5 turn
filtered, and decimated to 32, 44.1, or 48 kHz for the I2S ratio inductor, the inductance is increased by 25 times
digital audio interface. In addition to the receiver mode, and easily supports all typical AM air loop antennas
there is a clocking mode to choose to clock the Si473x- which generally vary between 10 and 20 µH.
D60 from a reference clock or crystal. On the Si473x- 4.5. SW Receiver
D60, there is an audio output mode to choose between
an analog and/or digital audio output. In the analog The Si4734/35 is the first fully integrated IC to support
audio output mode, ROUT and LOUT are used for the AM and FM, as well as short wave (SW) band reception
audio output pins. In the digital audio mode, DOUT, from 2.3 to 26.1 MHz fully covering the 120 meter to
DFS, and DCLK pins are used. Concurrent 11 meter bands. The Si4734/35 offers extensive
analog/digital audio output mode is also available shortwave features such as continuous digital tuning
requiring all five pins. with minimal discrete components and no factory
adjustments. Other SW features include adjustable
4.3. FM Receiver channel step sizes in 1 kHz increments, adjustable
The Si473x-D60 FM receiver is based on the proven channel bandwidth settings, advanced seek algorithm,
Si4700/01 FM tuner. The receiver uses a digital low-IF and soft mute.
architecture allowing the elimination of external The Si4734/35 uses the FM antenna to capture short
components and factory adjustments. The Si473x-D60 wave signals. These signals are then fed directly into
integrates a low noise amplifier (LNA) supporting the the AMI pin in a wide band configuration. See "AN332:
worldwide FM broadcast band (64 to 108 MHz). An Si47xx Programming Guide” and “AN383: Si47xx
AGC circuit controls the gain of the LNA to optimize Antenna and Schematic Guidelines" for more details.
sensitivity and rejection of strong interferers. An image-
reject mixer downconverts the RF signal to low-IF. The 4.6. LW Receiver
quadrature mixer output is amplified, filtered, and The Si4734/35 supports the long wave (LW) band from
digitized with high resolution analog-to-digital 153 to 279 kHz. The highly integrated Si4734/35 offers
converters (ADCs). This advanced architecture allows continuous digital tuning with minimal discrete
the Si473x-D60 to perform channel selection, FM components and no factory adjustments. The Si4734/35
demodulation, and stereo audio processing to achieve also offers adjustable channel step sizes in 1 kHz
superior performance compared to traditional analog increments, adjustable channel bandwidth settings,
architectures. advanced seek algorithm, and soft mute.
4.4. AM Receiver The Si4734/35 uses a separate ferrite bar antenna to
capture long wave signals.
The highly-integrated Si473x-D60 supports worldwide
AM band reception from 520 to 1710 kHz using a digital 4.7. Stereo Audio AUXIN ADC
low-IF architecture with a minimum number of external The Si473x-D60 stereo audio AUXIN ADC can be
components and no manual alignment required. This multiplexed between low-IF input for radio operation
digital low-IF architecture allows for high-precision and analog audio input for high fidelity data conversion
filtering offering excellent selectivity and SNR with at 32, 44.1, or 48 kHz sample rate. When operated in
minimum variation across the AM band. The DSP also ADC-mode, the Si473x-D60 supports I2S digital audio
provides adjustable channel step sizes in 1 kHz output only (no analog output) while enabling the analog
increments, AM demodulation, soft mute, seven inputs and the stereo ADC.
different channel bandwidth filters, and additional
features, such as a programmable automatic volume
control (AVC) maximum gain allowing users to adjust
the level of background noise.
Similar to the FM receiver, the integrated LNA and AGC

24 Rev. 1.1
 Si4730/31/34/35-D60
4.8. Digital Audio Interface
The digital audio interface operates in slave mode and
supports a variety of MSB-first audio data formats
including I2S and left-justified modes. The interface has
three pins: digital data input (DIN), digital frame
synchronization input (DFS), and a digital bit
synchronization input clock (DCLK). The Si473x-D60
supports a number of industry-standard sampling rates
including 32, 44.1, and 48 kHz. The digital audio
interface enables low-power operation by eliminating
the need for redundant DACs and ADCs on the audio
baseband processor.
4.8.1. Audio Data Formats
The digital audio interface operates in slave mode and
supports three different audio data formats:
 I2S
 Left-Justified
 DSP Mode
In I2S mode, by default the MSB is captured on the
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
In left-justified mode, by default the MSB is captured on
the first rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
In DSP mode, the DFS becomes a pulse with a width of
1DCLK period. The left channel is transferred first,
followed right away by the right channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
In all audio formats, depending on the word size, DCLK
frequency, and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. In addition, if
preferred, the user can configure the MSB to be
captured on the falling edge of DCLK via properties.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
4.8.2. Audio Sample Rates
The device supports a number of industry-standard
sampling rates including 32, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs on the audio
baseband processor.

Rev. 1.1 25
Si4730/31/34/35-D60

(OFALL = 1) INVERTED
DCLK

(OFALL = 0) DCLK

DFS LEFT CHANNEL RIGHT CHANNEL

I2S
(OMODE = 0000)
1 DCLK 1 DCLK

DOUT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n

MSB LSB MSB LSB

Figure 8. I2S Digital Audio Format

(OFALL = 1) INVERTED
DCLK

(OFALL = 0) DCLK

DFS LEFT CHANNEL RIGHT CHANNEL

Left-Justified
(OMODE = 0110)
DOUT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n

MSB LSB MSB LSB

Figure 9. Left-Justified Digital Audio Format

(OFALL = 0) DCLK

DFS

LEFT CHANNEL RIGHT CHANNEL

(OMODE = 1100) DOUT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n

st
(MSB at 1 rising edge)
MSB LSB MSB LSB
1 DCLK LEFT CHANNEL RIGHT CHANNEL
DOUT
nd 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n
(OMODE = 1000) (MSB at 2 rising edge)
MSB LSB MSB LSB

Figure 10. DSP Digital Audio Format

26 Rev. 1.1
 Si4730/31/34/35-D60
4.9. Stereo Audio Processing 4.10. Received Signal Qualifiers
The output of the FM demodulator is a stereo The quality of a tuned signal can vary depending on
multiplexed (MPX) signal. The MPX standard was many factors including environmental conditions, time of
developed in 1961, and is used worldwide. Today's day, and position of the antenna. To adequately manage
MPX signal format consists of left + right (L+R) audio, the audio output and avoid unpleasant audible effects to
left – right (L–R) audio, a 19 kHz pilot tone, and the end-user, the Si473x-D60 monitors and provides
RDS/RBDS data as shown in Figure 11 below. indicators of the signal quality, allowing the host
processor to perform additional processing if required
by the customer. The Si473x-D60 monitors signal
Modulation Level

quality metrics including RSSI, SNR, and multipath

Mono Audio interference on FM signals. These metrics are used to
Left + Right Stereo
Stereo Audio RDS/
optimize signal processing and are also reported to the
Pilot
Left - Right RBDS host processor. The signal processing algorithms can
use either Silicon Labs' optimized settings
(recommended) or be customized to modify
0 15 19 23 38 53 57 performance.
Frequency (kHz)
4.11. Volume Control
Figure 11. MPX Signal Spectrum
The audio output may be muted. Volume is adjusted
4.9.1. Stereo Decoder digitally by the RX_VOLUME property.
The Si473x-D60's integrated stereo decoder
automatically decodes the MPX signal using DSP 4.12. Stereo DAC
techniques. The 0 to 15 kHz (L+R) signal is the mono High-fidelity stereo digital-to-analog converters (DACs)
output of the FM tuner. Stereo is generated from the drive analog audio signals onto the LOUT and ROUT
(L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is pins. The audio output may be muted.
used as a reference to recover the (L–R) signal. Output
left and right channels are obtained by adding and 4.13. Soft Mute
subtracting the (L+R) and (L–R) signals respectively. The soft mute feature is available to attenuate the audio
4.9.2. Stereo-Mono Blending outputs and minimize audible noise in very weak signal
Adaptive noise suppression is employed to gradually conditions. The soft mute feature is triggered by the
combine the stereo left and right audio channels to a SNR metric. The SNR threshold for activating soft mute
mono (L+R) audio signal as the signal quality degrades is programmable, as are soft mute attenuation levels
to maintain optimum sound fidelity under varying and attack and release rates.
reception conditions. Three metrics, received signal 4.14. FM Hi-Cut Control
strength indicator (RSSI), signal-to-noise ratio (SNR),
and multipath interference, are monitored Hi-cut control is employed on audio outputs with
simultaneously in forcing a blend from stereo to mono. degradation of the signal due to low SNR and/or
The metric which reflects the minimum signal quality multipath interference. Two metrics, SNR and multipath
takes precedence and the signal is blended interference, are monitored concurrently in forcing hi-cut
appropriately. of the audio outputs. Programmable minimum and
maximum thresholds are available for both metrics. The
All three metrics have programmable stereo/mono transition frequency for hi-cut is also programmable with
thresholds and attack/release rates. If a metric falls up to seven hi-cut filter settings. A single set of attack
below its mono threshold, the signal is blended from and release rates for hi-cut are programmable for both
stereo to full mono. If all metrics are above their metrics from a range of 2 ms to 64 s. The level of hi-cut
respective stereo thresholds, then no action is taken to applied can be monitored with the FM_RSQ_STATUS
blend the signal. If a metric falls between its mono and command. Hi-cut can be disabled by setting the hi-cut
stereo thresholds, then the signal is blended to the level filter to audio bandwidth of 15 kHz.
proportional to the metric’s value between its mono and
stereo thresholds, with an associated attack and
release rate.

Rev. 1.1 27
Si4730/31/34/35-D60
4.15. De-emphasis The Si473x-D60 uses RSSI, SNR, and AFC to qualify
stations. Most of these variables have programmable
Pre-emphasis and de-emphasis is a technique used by
thresholds for modifying the seek function according to
FM broadcasters to improve the signal-to-noise ratio of
customer needs.
FM receivers by reducing the effects of high-frequency
interference and noise. When the FM signal is RSSI is employed first to screen all possible candidate
transmitted, a pre-emphasis filter is applied to stations. SNR and AFC are subsequently used in
accentuate the high audio frequencies. The Si473x-D60 screening the RSSI qualified stations. The more
incorporates a de-emphasis filter which attenuates high thresholds the system engages, the higher the
frequencies to restore a flat frequency response. Two confidence that any found stations will indeed be valid
time constants are used in various regions. The de- broadcast stations. The Si473x-D60 defaults set RSSI
emphasis time constant is programmable to 50 or 75 µs to a mid-level threshold and add an SNR threshold set
and is set by the FM_DEEMPHASIS property. to a level delivering acceptable audio performance. This
trade-off will eliminate very low RSSI stations while
4.16. RDS/RBDS Processor keeping the seek time to acceptable levels. Generally,
(Si4731/35 Only) the time to auto-scan and store valid channels for an
entire FM band with all thresholds engaged is very short
The Si4731/35 implements an RDS/RBDS* processor
for symbol decoding, block synchronization, error depending on the band content. Seek is initiated using
detection, and error correction. the FM_SEEK_START command. The RSSI, SNR, and
AFC threshold settings are adjustable using properties.
The Si4731/35 device is user configurable and provides
an optional interrupt when RDS is synchronized, loses 4.19. Reference Clock
synchronization, and/or the user configurable RDS
The Si473x-D60 reference clock is programmable,
FIFO threshold has been met.
supporting RCLK frequencies listed in Table 12,
The Si4731/35 reports RDS decoder synchronization “Reference Clock and Crystal Characteristics,” on
status and detailed bit errors in the information word for page 18. Refer to Table 2, “DC Characteristics,” on
each RDS block with the FM_RDS_STATUS command. page 6 for switching voltage levels and Table 12 for
The range of reportable block errors is 0, 1–2, 3–5, or
frequency tolerance information.
6+. More than six errors indicates that the
corresponding block information word contains six or An onboard crystal oscillator is available to generate the
more non-correctable errors or that the block checkword 32.768 kHz reference when an external crystal and load
contains errors. The pilot does not have to be present to capacitors are provided. Refer to "2. Typical Application
decode RDS/RBDS. Schematic" on page 20. This mode is enabled using the
POWER_UP command. Refer to “AN332: Si47xx
*Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document. Programming Guide”.
The Si473x-D60 performance may be affected by data
4.17. Tuning activity on the SDIO bus when using the integrated
The tuning frequency is directly programmed using the internal oscillator. SDIO activity results from polling the
FM_TUNE_FREQ and AM_TUNE_FREQ commands. tuner for status or communicating with other devices
The Si473x-D60 supports channel spacing steps of that share the SDIO bus. If there is SDIO bus activity
10 kHz in FM mode and 1 kHz in AM mode. while the Si473x-D60 is performing the seek/tune
function, the crystal oscillator may experience jitter,
4.18. Seek which may result in mistunes, false stops, and/or lower
The Si473x-D60 seek functionality is performed SNR.
completely on-chip and will search up or down the For best seek/tune results, Silicon Laboratories
selected frequency band for a valid channel. A valid recommends that all SDIO data traffic be suspended
channel is qualified according to a series of during Si473x-D60 seek and tune operations. This is
programmable signal indicators and thresholds. The achieved by keeping the bus quiet for all other devices
seek function can be made to stop at the band edge and on the bus, and delaying tuner polling until the tune or
provide an interrupt, or wrap the band and continue seek operation is complete. The seek/tune complete
seeking until arriving at the original departure frequency. (STC) interrupt should be used instead of polling to
The device sets interrupts with found valid stations or, if determine when a seek/tune operation is complete.
the seek results in zero found valid stations, the device
indicates failure and again sets an interrupt. Refer to
“AN332: Si47xx Programming Guide”.

28 Rev. 1.1
 Si4730/31/34/35-D60
4.20. Control Interface edges of SCLK. The Si473x-D60 acknowledges each
data byte by driving SDIO low for one cycle, on the next
A serial port slave interface is provided, which allows an
falling edge of SCLK. The user may write up to 8 data
external controller to send commands to the Si473x-
bytes in a single 2-wire transaction. The first byte is a
D60 and receive responses from the device. The serial
command, and the next seven bytes are arguments.
port can operate in two bus modes: 2-wire mode and 3-
wire mode. The Si473x-D60 selects the bus mode by For read operations, after the Si473x-D60 has
sampling the state of the GPO1 and GPO2 pins on the acknowledged the control byte, it will drive an 8-bit data
rising edge of RST. The GPO1 pin includes an internal byte on SDIO, changing the state of SDIO on the falling
pull-up resistor, which is connected while RST is low, edge of SCLK. The user acknowledges each data byte
and the GPO2 pin includes an internal pull-down by driving SDIO low for one cycle, on the next falling
resistor, which is connected while RST is low. edge of SCLK. If a data byte is not acknowledged, the
Therefore, it is only necessary for the user to actively transaction will end. The user may read up to 16 data
drive pins which differ from these states. See Table 16. bytes in a single 2-wire transaction. These bytes contain
the response data from the Si473x-D60.
Table 16. Bus Mode Select on Rising Edge of A 2-wire transaction ends with the STOP condition,
RST which occurs when SDIO rises while SCLK is high.
Bus Mode GPO1 GPO2 For details on timing specifications and diagrams, refer
2-Wire 1 0 to Table 4, “2-Wire Control Interface Characteristics” on
3-Wire 0 (must drive) 0 page 9; Figure 2, “2-Wire Control Interface Read and
Write Timing Parameters,” on page 10, and Figure 3, “2-
After the rising edge of RST, the pins GPO1 and GPO2 Wire Control Interface Read and Write Timing Diagram,”
are used as general purpose output (O) pins, as on page 10.
described in Section “4.21. GPO Outputs”. In any bus 4.20.2. 3-Wire Control Interface Mode
mode, commands may only be sent after VD and VA When selecting 3-wire mode, the user must ensure that
supplies are applied. a rising edge of SCLK does not occur within 300 ns
In any bus mode, before sending a command or reading before the rising edge of RST.
a response, the user must first read the status byte to The 3-wire bus mode uses the SCLK, SDIO, and SEN_
ensure that the device is ready (CTS bit is high). pins. A transaction begins when the user drives SEN
4.20.1. 2-Wire Control Interface Mode low. Next, the user drives a 9-bit control word on SDIO,
When selecting 2-wire mode, the user must ensure that which is captured by the device on rising edges of
SCLK is high during the rising edge of RST, and stays SCLK. The control word consists of a 9-bit device
high until after the first start condition. Also, a start address (A7:A5 = 101b), a read/write bit (read = 1, write
condition must not occur within 300 ns before the rising = 0), and a 5-bit register address (A4:A0).
edge of RST. For write operations, the control word is followed by a
The 2-wire bus mode uses only the SCLK and SDIO 16-bit data word, which is captured by the device on
pins for signaling. A transaction begins with the START rising edges of SCLK.
condition, which occurs when SDIO falls while SCLK is For read operations, the control word is followed by a
high. Next, the user drives an 8-bit control word serially delay of one-half SCLK cycle for bus turn-around. Next,
on SDIO, which is captured by the device on rising the Si473x-D60 will drive the 16-bit read data word
edges of SCLK. The control word consists of a 7-bit serially on SDIO, changing the state of SDIO on each
device address, followed by a read/write bit (read = 1, rising edge of SCLK.
write = 0). The Si473x-D60 acknowledges the control A transaction ends when the user sets SEN high, then
word by driving SDIO low on the next falling edge of pulses SCLK high and low one final time. SCLK may
SCLK. either stop or continue to toggle while SEN is high.
Although the Si473x-D60 will respond to only a single In 3-wire mode, commands are sent by first writing each
device address, this address can be changed with the argument to register(s) 0xA1–0xA3, then writing the
SEN pin (note that the SEN pin is not used for signaling command word to register 0xA0. A response is
in 2-wire mode). Refer to “AN332: Si47xx Programming retrieved by reading registers 0xA8–0xAF.
Guide”
For details on timing specifications and diagrams, refer
For write operations, the user then sends an 8-bit data to Table 5, “3-Wire Control Interface Characteristics,” on
byte on SDIO, which is captured by the device on rising page 11; Figure 4, “3-Wire Control Interface Write

Rev. 1.1 29
Si4730/31/34/35-D60
Timing Parameters,” on page 11, and Figure 5, “3-Wire 4.25. Programming with Commands
Control Interface Read Timing Parameters,” on page 11.
To ease development time and offer maximum
4.21. GPO Outputs customization, the Si473x-D60 provides a simple yet
powerful software interface to program the receiver. The
The Si473x-D60 provides three general-purpose output
device is programmed using commands, arguments,
pins. The GPO pins can be configured to output a
properties, and responses.
constant low, constant high, or high-impedance. The
GPO pins can be reconfigured as specialized functions. To perform an action, the user writes a command byte
and associated arguments, causing the chip to execute
4.22. Firmware Upgrades the given command. Commands control an action such
The Si473x-D60 contains on-chip program RAM to as powerup the device, shut down the device, or tune to
accommodate minor changes to the firmware. This a station. Arguments are specific to a given command
allows Silicon Labs to provide future firmware updates and are used to modify the command.
to optimize the characteristics of new radio designs and Properties are a special command argument used to
those already deployed in the field. modify the default chip operation and are generally
configured immediately after powerup. Examples of
4.23. Reset, Powerup, and Powerdown properties are de-emphasis level, RSSI seek threshold,
Setting the RST pin low will disable analog and digital and soft mute attenuation threshold.
circuitry, reset the registers to their default settings, and Responses provide the user information and are
disable the bus. Setting the RST pin high will bring the echoed after a command and associated arguments are
device out of reset. issued. All commands provide a 1-byte status update,
A powerdown mode is available to reduce power indicating interrupt and clear-to-send status information.
consumption when the part is idle. Putting the device in For a detailed description of the commands and
powerdown mode will disable analog and digital circuitry properties for the Si473x-D60, see “AN332: Si47xx
while keeping the bus active. Programming Guide.”
4.24. 2 V Operation (SSOP Only)
The Si473x-D60 is capable of operating down to 2 V as
the battery drains in an application. Any power-up or
reset is not guaranteed to work below the DC
characteristics defined in Table 2. This capability
enables a much longer run time in battery operated
devices.

30 Rev. 1.1
 Si4730/31/34/35-D60
5. Pin Descriptions
5.1. Si473x-D60-GM

GPO3/[DCLK]
GPO2/[INT]

DFS/[RIN]
GPO1
NC
NC 1 20 19 18 17 16
FMI 2 15 DOUT/[LIN]
RFGND 3 GND 14 LOUT/[DFS]
AMI 4 PAD 13 ROUT/[DOUT]
RST 5 12 GND
6 7 8 9 10 11 VA
SEN

SCLK

RCLK

VD
SDIO

Pin Number(s) Name Description

1, 20 NC No connect. Leave floating.
2 FMI FM RF inputs. FMI should be connected to the antenna trace.
3 RFGND RF ground. Connect to ground plane on PCB.
4 AMI AM RF input. AMI should be connected to the AM antenna.
5 RST Device reset input (active low).
6 SEN Serial enable input (active low).
7 SCLK Serial clock input.
8 SDIO Serial data input/output.
9 RCLK External reference oscillator input.
10 VD Digital and I/O supply voltage.
11 VA Analog supply voltage. May be connected directly to battery.
12, GND PAD GND Ground. Connect to ground plane on PCB.
13 ROUT/[DOUT] Right audio line output for analog output mode.
14 LOUT/[DFS] Left audio line output for analog output mode.
15 DOUT/[LIN] Digital output data for digital output mode or Left channel input for AUXIN ADC
mode.
16 DFS/[RIN] Digital frame synchronization input for digital output mode or Right channel input
for AUXIN ADC mode.
17 GPO3/[DCLK] General purpose output, crystal oscillator, or digital bit synchronous clock input
in digital output mode.
18 GPO2/[INT] General purpose output or interrupt pin.
19 GPO1 General purpose output.

Rev. 1.1 31
Si4730/31/34/35-D60
5.2. Si473x-D60-GU

DOUT/[LIN] 1 24 LOUT/[DFS]
DFS/[RIN] 2 23 ROUT/[DOUT]

GPO3/[DCLK] 3 22 DBYP
GPO2/[INT] 4 21 VA
GPO1 5 20 VD
NC 6 19 RCLK
NC 7 18 SDIO
FMI 8 17 SCLK
RFGND 9 16 SEN
NC 10 15 RST
NC 11 14 GND
AMI 12 13 GND

Pin Number(s) Name Description

1 DOUT/[LIN] Digital output data for digital output mode or Left channel input for AUX IN ADC
mode.
2 DFS/[RIN] Digital frame synchronization input for digital output mode or Right channel input
for AUXIN ADC mode.
3 GPO3/[DCLK] General purpose output, crystal oscillator, or digital bit synchronous clock input
in digital output mode.
4 GPO2/[INT] General purpose output or interrupt pin.
5 GPO1 General purpose output.
6,7 NC No connect. Leave floating.
8 FMI FM RF inputs. FMI should be connected to the antenna trace.
9 RFGND RF ground. Connect to ground plane on PCB.
10,11 NC Unused. Tie these pins to GND.
12 AMI AM/SW/LW RF input.
13,14 GND Ground. Connect to ground plane on PCB.
15 RST Device reset input (active low).
16 SEN Serial enable input (active low).
17 SCLK Serial clock input.
18 SDIO Serial data input/output.
19 RCLK External reference oscillator input.
20 VD Digital and I/O supply voltage.
21 VA Analog supply voltage. May be connected directly to battery.
22 DBYP Bypass capacitor.
23 ROUT/[DOUT] Right audio line output in analog output mode.
24 LOUT/[DFS] Left audio line output in analog output mode.

32 Rev. 1.1
 Si4730/31/34/35-D60
6. Ordering Guide

Part Number1 Description Package Operating

Type Temperature/Voltage
Si4730-D60-GM QFN
Pb-free –20 to 85 °C
2
AM/FM Broadcast Radio Receiver
Si4730-D60-GU SSOP 2.7 to 5.5 V
Pb-free
Si4731-D60-GM QFN
AM/FM Broadcast Radio Receiver with Pb-free –20 to 85 °C
Si4731-D60-GU 2 RDS/RBDS SSOP 2.7 to 5.5 V
Pb-free
Si4734-D60-GM QFN
Pb-free –20 to 85 °C
2
AM/FM/SW/LW Broadcast Radio Receiver
Si4734-D60-GU SSOP 2.7 to 5.5 V
Pb-free
Si4735-D60-GM QFN
AM/FM/SW/LW Broadcast Radio Receiver Pb-free –20 to 85 °C
Si4735-D60-GU 2 with RDS/RBDS SSOP 2.7 to 5.5 V
Pb-free
Notes:
1. Add an “(R)” at the end of the device part number to denote tape and reel option.
2. SSOP devices operate down to VA = 2 V at 25 °C.

Rev. 1.1 33
Si4730/31/34/35-D60
7. Package Outline
7.1. Si473x-D60 QFN
Figure 12 illustrates the package details for the Si473x. Table 17 lists the values for the dimensions shown in the
illustration.

Figure 12. 20-Pin Quad Flat No-Lead (QFN)

Table 17. Package Dimensions

Symbol Millimeters Symbol Millimeters
Min Nom Max Min Nom Max
A 0.50 0.55 0.60 f 2.53 BSC
A1 0.00 0.02 0.05 L 0.35 0.40 0.45
b 0.20 0.25 0.30 L1 0.00 — 0.10
c 0.27 0.32 0.37 aaa — — 0.05
D 3.00 BSC bbb — — 0.05
D2 1.65 1.70 1.75 ccc — — 0.08
e 0.50 BSC ddd — — 0.10
E 3.00 BSC eee — — 0.10
E2 1.65 1.70 1.75
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

34 Rev. 1.1
 Si4730/31/34/35-D60
7.2. Si473x-D60 SSOP
Figure 13 illustrates the package details for the Si473x. Table 18 lists the values for the dimensions shown in the
illustration.

Figure 13. 24-Pin SSOP

Table 18. Package Dimensions

Dimension Min Nom Max
A — — 1.75
A1 0.10 — 0.25
b 0.20 — 0.30
c 0.10 — 0.25
D 8.65 BSC
E 6.00 BSC
E1 3.90 BSC
e 0.635 BSC
L 0.40 — 1.27
L2 0.25 BSC
θ 0° — 8°
aaa 0.20
bbb 0.18
ccc 0.10
ddd 0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AE.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.

Rev. 1.1 35
Si4730/31/34/35-D60
8. PCB Land Pattern
8.1. Si473x-D60 QFN
Figure 14 illustrates the PCB land pattern details for the Si473x-D60-GM QFN. Table 19 lists the values for the
dimensions shown in the illustration.

Figure 14. PCB Land Pattern

36 Rev. 1.1
 Si4730/31/34/35-D60

Table 19. PCB Land Pattern Dimensions

Symbol Millimeters Symbol Millimeters
Min Max Min Max
D 2.71 REF GE 2.10 —
D2 1.60 1.80 W — 0.34
e 0.50 BSC X — 0.28
E 2.71 REF Y 0.61 REF
E2 1.60 1.80 ZE — 3.31
f 2.53 BSC ZD — 3.31
GD 2.10 —
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Notes: Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Notes: Stencil Design

1. A stainless steel, laser-cut, and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.

Notes: Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.

Rev. 1.1 37
Si4730/31/34/35-D60
8.2. Si473x-D60 SSOP
Figure 15 illustrates the PCB land pattern details for the Si473x-D60-GU SSOP. Table 20 lists the values for the
dimensions shown in the illustration.

Figure 15. PCB Land Pattern

Table 20. PCB Land Pattern Dimensions

Dimension Min Max
C 5.20 5.30
E 0.635 BSC
X 0.30 0.40
Y1 1.50 1.60
General:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Solder Mask Design:
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design:
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly:
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.

38 Rev. 1.1
 Si4730/31/34/35-D60
9. Top Markings
9.1. Si473x-D60 Top Marking (QFN)

3060 3160 3460 3560

DTTT DTTT DTTT DTTT
YWW YWW YWW YWW
9.2. Top Marking Explanation (QFN)

Mark Method: YAG Laser

Line 1 Marking: Part Number 30 = Si4730, 31 = Si4731, 34 = Si4734, 35 = Si4735.
Firmware Revision 60 = Firmware Revision 6.0.
Line 2 Marking: Die Revision D = Revision D Die.
TTT = Internal Code Internal tracking code.
Line 3 Marking: Circle = 0.5 mm Diameter Pin 1 Identifier.
(Bottom-Left Justified)
Y = Year Assigned by the Assembly House. Corresponds to the last
WW = Workweek significant digit of the year and work week of the mold date.

Rev. 1.1 39
Si4730/31/34/35-D60
9.3. Si473x-D60 Top Marking (SSOP)

473XD60GU
YYWWTTTTTT
9.4. Top Marking Explanation (SSOP)

Mark Method: YAG Laser

4730 = Si4730; 4731 = Si4731; 4734 = Si4734;
Part Number
4735 = Si4735.
Line 1 Marking: Die Revision D = Revision D die.
Firmware Revision 60 = Firmware Revision 6.0.
Package Type GU = 24-pin SSOP Pb-free package
YY = Year
Line 2 Marking: WW = Work week Assigned by the Assembly House.
TTTTTT = Manufacturing code

40 Rev. 1.1
 Si4730/31/34/35-D60
10. Additional Reference Resources
Contact your local sales representatives for more information or to obtain copies of the following references:
 EN55020 Compliance Test Certificate
 AN332: Si47xx Programming Guide
 AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines
 AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure
 Si47xx EVB User’s Guide
 Customer Support Site: www.silabs.com
This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA
is required for complete access. Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support
request.

Rev. 1.1 41
Si4730/31/34/35-D60
DOCUMENT CHANGE LIST
Revision 1.0 to Revision 1.1
 Updated part number throughout.
 Updated pin assignments on front page.
 Updated block diagram on front page.
 Updated Table 6, “Digital Audio Interface
Characteristics,” on page 12.
 Updated Table 12, “Reference Clock and Crystal
Characteristics,” on page 18.
 Added Table 13, “Thermal Conditions,” on page 18.
 Updated Section "2. Typical Application Schematic"
on page 20.
 Updated Section "4. Functional Description" on page
23.
 Updated Section "5. Pin Descriptions" on page 31.

42 Rev. 1.1
 Si4730/31/34/35-D60
NOTES:

Rev. 1.1 43
Si4730/31/34/35-D60
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: [email protected]
Internet: www.silabs.com

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

44 Rev. 1.1