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Verilog programming solutions 4

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6 views2 pages

solution_4

Verilog programming solutions 4

Uploaded by

sipossandor1980
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© © All Rights Reserved
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E2.

1 – Digital Electronics II

Solution to Problem Sheet 4


(Question ratings: A=Easy, …, E=Hard. All students should do questions rated A, B or C as a minimum)

1B. As seen in problem sheet 1, an XOR gate can be used to invert a signal or pass it through unchanged
according to whether a control input is high or low.

D
T =1
Q
1D
C
C1

2C. We define t=0 as the falling edge of CA.


Setup requirement: max(DB↑↓)+12 < min(CB↑)
50+22+12 <(13 + ½T)
½T > 71 ⇒ f < 7 MHz
Hold requirement: max(CB↑) + 27 > min(T + DB↑↓)
½T+22 + 27 > T + 5+13
½T > 31 (less severe restriction than above)
Note the extra T term in the hold requirement: this is because we want the second transition of DB to
occur >27 ns after CB↑. The Hold requirement is so easily satisfied that it wouldn’t normally be
necessary to calculate it exactly.

3C.

µPA → Setu max(DA↑↓) +5 < Hol max(CA↑)+3<


flipflop p: min(CA↑) d: min(T+DA↑↓)
CA↓=0 50+5 < ½T ½T+3< T + 5
½T > 55 ⇒ f < 9 ½T > –2 þ
MHz

flipflop → Setu max(DB↑↓)+5 < Hol max(CB↓)+3<


flipflop p: min(CB↓) d: min(T+DB↑↓)
CA↑=0 10+22+5 < ½T+13 ½T+22+3< T +2+13
½T > 24 ⇒ f < 21 ½T > 10 ⇒ f < 50
MHz MHz

flipflop → Setu max(FB↑↓)+12<mi Hol max(CB↑)+27<min(T


µPB p: n(CB↑) d: +FB↑↓)
CB↓=0 10+12<½T ½T+27<T + 2
½T > 22 ⇒ f < 23 ½T > 25 ⇒ f < 20
MHz MHz
It can be seen that the critical figure is the setup time for the first flipflop: this is because the
microprocessor takes such a long time (up to 50 ns) to output its data.
Question 4 (which doesn’t work) and question 5 (which does) show how to relax this constraint. In the
third row of the previous table, I have cancelled out the delay of the clock line driver/receiver from the
two sides of the inequality. This is only valid if we can assume that the propagation delays for rising
and falling edges are the same (not generally true).

Rev: Dec 2016 Digital Electronics II: Solution Sheet 4 Page 1


4C. The first flipflop now responds to a falling clock edge: this means that µPA now has a full clock cycle
to output its data rather than only a half cycle. We have therefore doubled maximum clock frequency
of the circuit. (Note that the middle row of this table is unchanged from the previous question).
The problem is that the output from the second flipflop now changes on the rising clock edge and
therefore fails to meet the hold time of µPB.

µPA → Setu max(DA↑↓)+5<min(T Hol max(CA↓)+3<min(D


flipflop p: +CA↓) d: A↑↓)
CA↓=0 50+5<T 0+3<5 þ
T > 55 ⇒ f < 18 MHz

flipflop → Setu max(DC↑↓)+5<min(C Hol max(CB↑)+3<min(T


flipflop p: B↑) d: +DC↑↓)
CA↓=0 10+22+5 < ½T+13 ½T+22+3<T + 2+13
½T > 24 ⇒ f < 21 ½T > 10 ⇒ f < 50
MHz MHz

flipflop → Setu max(DD↑↓)+12<min( Hol max(CB↑)+27<min(


µPB p: T+CB↑) d: DD↑↓)
CB↑=0 10+12<T 2 > 27 ý
T > 22 ⇒ f < 46 MHz

5D. We can fix the hold problem by adding a third flipflop. The last row of the previous table is now
replaced by the two rows below and the maximum frequency is now 18 MHz.

flipflop → Setu max(DD↑↓)+5<min( Hol max(CB↓)+3<min(T


flipflop p: CB↓) d: +DD↑↓)
CB↑=0 10+5<½T ½T+3<T + 2
½T > 15 ⇒ f < 33 ½T > 1 ⇒ f < 500
MHz MHz

flipflop → Setu max(DE↑↓)+12<min( Hol max(CB↑)+27<min(T


µPB p: CB↑) d: +DE↑↓)
CB↓=0 10+12<½T ½T+27<T + 2
½T > 22 ⇒ f < 23 ½T > 25 ⇒ f < 20
MHz MHz
The timing of this circuit with a clock period of about 60 ns (16.7 MHz) is shown below with
setup/hold windows shaded:

CA
CB
DA
DB
DC
DD
DE

Rev: Dec 2016 Digital Electronics II: Solution Sheet 4 Page 2

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