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Verilog programming solutions 5

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8 views3 pages

solution_5

Verilog programming solutions 5

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sipossandor1980
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© © All Rights Reserved
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E2.

1 – Digital Electronics II

Solution Sheet 5 – Data Conversion


(Question ratings: A=Easy, …, E=Hard. All students should do questions rated A, B or C as a minimum)

1B. Full-scale range = 3998 so the accuracy is 2/3998 of full-scale range. For an N-bit binary A/D
converter, the full-scale range is (2N–1) LSB giving an accuracy of 0.5/(2N–1).

0.5 2
Hence ≤ ⇒ 2 N ≥ 1000.5 ⇒ N ≥ 9.96 ⇒ N = 10
2 N − 1 3998

2B. –2047 mV ±0.5 mV, i.e. –2047.5 mV to –2046.5 mV.

3B. 1 V and 8 V correspond to output values of 100 and 800 respectively, so if 1 V < x < 8 V, the output
will be in the range 100 to 799.

4C. A change of 5 V in V3 must give a change of –1 V in VOUT, a gain of –0.2. Hence RF/R3 = 0.2 ⇒
R3 = 50 kΩ.

When V3=0, the op-amp may be viewed an a non-inverting amplifier with a gain of (1 + RF/R3) =
1.2. The voltage at VOUT due to V2:0 is therefore given by:

where G4:0 are the reciprocals of R4:0.

To minimize the effect of op-amp bias currents, we should make the Thévenin impedances at the
input terminals equal. This means that G4+G2+G1+G0 = G3+GF = 120 µS.

The gains from V2, V1 and V0 to VOUT must be 0.1, 0.05 and 0.025 respectively. Thus we have
G2 = 120 µS × 0.1/1.2 = 10 µS ⇒ R2 = 100 kΩ. Similarly, R1 = 200 kΩ and R0 = 400 kΩ.

Finally G4 = 120 µS – G2 – G1 – G0 = 102.5 µS ⇒ R4 = 9.8 kΩ.

5C. The SYNC signal needs inverting because SYNC going high must cause the output to decrease. We
will need a negative bias voltage in order to obtain –0.3 V. Our circuit is therefore:

Taking Gn = 1/Rn we must have G1+G2+G3+G4 = 1/50Ω = 20 mS.

Rev: Dec 2016 Digital Electronics II: Solution Sheet 5 Page 1


Then VOUT = (V1G1 + V2G2 – 5G3) / 20 mS.
From the truth table, we see that changes of 5 V in V1 and V2 must give changes in VOUT of 0.3
and 0.7 volts respectively; this means we need gains of 0.06 and 0.14. Hence:

G1 = 0.06 × 20 mS = 1.2 mS ⇒ R1 = 833Ω.


G2 = 0.14 × 20 mS = 2.8 mS ⇒ R2 = 357Ω.
To generate the –0.3 V offset: 5G3 = 0.3 × 20 mS = 6 mS ⇒ R3 = 833Ω.
G4 = 20 mS – G1 – G2 – G3 = 14.8 mS ⇒ R4 = 67.6Ω.
Note it is possible to take R4 to +5 V instead in which case R3 and R4 are 116Ω and 135Ω.
This circuit is very fast since it has no op-amps.

6B. The range of a 16-bit signed number is ±32767 and so to avoid distortion, the RMS value must be no
higher than 3276.7. From the notes, the RMS value of quantisation noise is 0.289 LSB which gives a
signal-to-noise ratio of 11338 which equals 81 dB

7B. (a) z will equal –1 when x < −0.5 , so

pr ( z = −1) = pr ( x < −0.5) = pr (q < −0.5 − w)


− 0.5 − w − 0.5 − w − 0.5 − w
= ∫ p(q)dq = ∫1− | q | dq = ∫1 + q dq
q = −1 q = −1 q = −1

[
= q + 0.5q 2 ]
− 0.5 − w
q = −1 = 0.125 × (2w − 1) 2

Note that because | w |< 0.5 is given in the question, both integration limits are always negative and
so we can replace | q | → − q in the integrand. You can also get this answer graphically (and more
easily) by drawing the pdf and finding the area of the triangle representing pr (q < −0.5 − w) .

2
(b) pr ( z = +1) = 0.125 × ( 2 w + 1)

pr ( z = 0) = 1 − pr ( z = −1) − pr ( z = +1) = 0.75 − w2

(c) We have

E ( z ) = 1 × pr ( z = +1) − 1 × pr ( z = −1)
(
= 0.125 × (2w + 1)2 − (2w − 1)2 = w )
Var ( z ) = E ( z 2 ) − E ( z ) 2 = E ( z 2 ) − w2
= 1 × pr ( z = +1) + 1 × pr ( z = −1) − w2
(
= 0.125 × (2w + 1) 2 + (2w − 1) 2 − w2 )
2 2
= w + 0.25 − w = 0.25

8C. Full-scale range of 20 V equals 4096 LSB so 0.5 LSB = 0.5 × 20/4096 = 2.44 mV.
The peak rate of change of a 10 V sinewave is 20πf volts per second. The voltage change in 5 ns is
therefore πf × 10-7. These are equal when f = 2.44 × 10-3 × 107 / π = 7.77 kHz.
For the second part I = C dV/dt from which Δt = C×ΔV/I = 2×10-10×2.44×10-3/10-9 = 488 µs.

Rev: Dec 2016 Digital Electronics II: Solution Sheet 5 Page 2


9D. We send the all zero state to the initial state of a conversion.

NDONE = DONE ⋅ START + DONE ⋅ X 0


NX 2 = DONE ⋅ ( X 2 + START ) + DONE ⋅ X 2 ⋅ ( X 0 + X 1 + HI ) + DONE ⋅ X 2 ⋅ X 1⋅ X 0
NX 1 = DONE ⋅ X 1⋅ START + DONE ⋅ X 1⋅ ( X 0 + HI ) + DONE ⋅ X 2 ⋅ X 1⋅ X 0
NX 0 = DONE ⋅ X 0 ⋅ START + DONE ⋅ X 0. HI + DONE ⋅ X 1⋅ X 0

10B. We call the answer w or z according to whether it is unsigned or signed:


(a) 0<=w<=15, Wi=!Ui
(b) 0<=w<=1, W0=U3
(c) –8<=z<=7, Z3=!U3, Zi=Ui for i=0,1,2
(d) 0<=w<=7, Wi=Ui+1
(e) –8<=z<=7, Zi=!Xi
(f) –4<=z<=3, Zi=Xi+1
(g) 0<=w<=1, W0=X3
(h) 0<=w<=7, Wi=Xi for i=0,1,2
(i) 0<=w<=15, Wi=Xi
(j) 0<=w<=3, Wi=Ui+1 for i=0,1
(k) 0<=w<=15, W0=U3, Wi=Ui-1 for i=1,2,3
(l) –8<=z<=7, Zi=Ui

Rev: Dec 2016 Digital Electronics II: Solution Sheet 5 Page 3

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