IET Circuits, Devices & Systems

Research Article

Systematic circuit design and analysis using ISSN 1751-858X

Received on 19th May 2019

generalised g /I functions of MOS devices

Revised 15th October 2019
Accepted on 4th December 2019
m D
E-First on 1st April 2020
doi: 10.1049/iet-cds.2019.0209
www.ietdl.org

Hamed Aminzadeh1
1Department of Electrical Engineering, Payame Noor University (PNU), 19395-3697, Tehran, Iran
E-mail: [email protected]

Abstract: The conventional approach to implementing analogue integrated circuits in nano-scale complementary metal oxide
semiconductor (CMOS) technologies relies basically on circuit simulations using the SPICE models provided by the foundries.
Depending on the circuit complexity, the designer should, however, spend a significant amount of time sizing the metal oxide
semiconductor field effect transistors such that maximum efficiency is achieved for minimum power consumption and silicon
area. Analytical-based design procedures can assist the designer in confronting the sizing challenge of the metal oxide
semiconductor (MOS) devices. The procedures are, however, dependent on circuit topology, model parameters, and device
physics. This study aims at presenting a systematic approach for analysis and design of analogue circuits in scaled CMOS. For
this purpose, the behaviour of short-channel MOS devices is characterised in various process and temperature corners using an
updated matrix representation of different device scales, bias conditions, and small-signal parameters. The details to effectively
extract the matrix derivation of the technology model files are presented, enabling to devise generalised functions for the design
and analysis of the circuits. The design examples include a 0.39 V – 28 µA reference circuit, and a 7.50 µA/V operational-
transconductance amplifier with 1.0 V voltage supply in 90-nm CMOS.

1 Introduction the design process. At the end, it is difficult to gain a clear insight
into the design trade-offs and to interpret the technical reasons
The operation of nano-scale analogue integrated circuits (ICs) is leading to proper device dimensions. Analytical design procedures
affected by the underlying trade-offs between consuming power, take into account the device physics and the circuit architecture in
silicon die area, linearity, noise, bandwidth and dynamic range, the inner algorithm. This includes characterising the device
where the interactions between these parameters are not very behaviour using the square-law [1] and E.K.V. (Enz–
similar to the models found in the classical text-books [1]. Krummenacher–Vittoz) transistor models [15], or by modelling the
Implementation of high-performance analogue circuits is therefore gm /ID ratio of the integrated MOSFETs of a technology [8, 16–23].
considered as a big challenge which requires a high level of
The standard square-law model cannot quantify the long-channel
knowledge and expertise in nano-scale complementary metal oxide
transistors operating in weak or moderate inversion and fails to
semiconductor (CMOS) design. SPICE simulations can be
explain the second-order effects posing during the normal
performed to realise complex micro-systems in advanced IC
operation of nano-scale devices. The quadratic model is therefore
fabrication technologies, by evaluating the electrical state of the
applied only to present a general description of the circuit
metal oxide semiconductor field effect transistors (MOSFETs)
operation. The E.K.V. model is used to explain the MOSFET
concerning the inherent relations between drain current, ID and
operation irrespective of its operating regime. The model
gate-source, drain-source and source-bulk voltage (V GS, V DS and parameters are not, however, provided by many fabrication
V SB, respectively). In the shadow of the second-order effects, the companies [20], leading to unknown variables in the design
designer should, however, render multiple sweeps on the channel expressions. The correct ratio of device transconductance (gm) over
length (L) and width (W) of different devices such that the ID (gm /ID) is evaluated through experimental or simulation
minimum operation requirement is ensured in various process,
procedures within the framework of each gm /ID methodology. This
voltage and temperature (PVT) corners. Computer-aided design
(CAD) tools can assist in simplifying the transistor sizing minimises the difference between the results from SPICE
procedure, exploring the possible solutions to meet the target simulation and analytical results, enabling to predict the MOS
design specifics with a certain topology [2–4]. The intrinsic trade- device characteristics using gm /ID plots or pre-computed lookup
offs between various parameters, however, complicates the design tables. The effectiveness of the original gm /ID methodology is
algorithm encoded to the CAD tool, leaving design automation explored in [16], where an operational-transconductance amplifier
procedures of the CMOS circuits still a key research area. The (OTA) is designed based on the gm /ID ratio of the MOSFETs.
multi-dimensional nature of circuit behaviour promotes the Several design methodologies are presented afterward to
application of evolutionary algorithms for the design and synthesis implement the circuits based on the similar strategies with gm /ID,
of the ICs. Several design methodologies are therefore proposed, ID and L considered as inputs. The original gm /ID method ignores,
including the use of genetic algorithm (GA) [5], genetic however, the effect of channel length modulation, body effect and
programming [6], non-dominated sorting GA (NSGA-II) [7, 8], gate sizing on the gm /ID factor, necessitating the requirement of
simulated annealing [9, 10], geometric programming [11],
adapting the original methodology for the design of advanced
imperialist competitive algorithm [12] etc. [13, 14] for sizing of the
analogue circuits. These effects are therefore studied to improvise
integrated components. Regardless of the device model and its
the improved versions of the original gm /ID methodology [17–21].
physical behaviour, and despite the inner connections of the
components, each algorithm conducts a stochastic optimisation In [17], the relationships between intrinsic gain (gm /gO, where gO is
sequence aiming at achieving the desired behaviour. This ends up the output conductance) and V DS and V SB are evaluated, and the
to an enormous number of candidates for exploration and leads to updated gm /ID curves are applied to realise a two-stage OTA based
overwhelming the number of the iterations required to finalising on current density (ID /W), transit frequency, f T and gm /gO of the

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product, common-mode rejection ratio (CMRR) and noise level is
ensured.
The design techniques addressed above emphasise mainly on
theoretical aspects of the gm /ID methodology, and not on the
implementation details for systematic design and analysis of
CMOS circuits. An updated gm /ID design flow is therefore
introduced in this paper to design and analyse analogue circuits
such as voltage amplifiers, OTAs and voltage references. The
proposed approach transfers the entire phases of circuit design and
analysis to a coding environment other than the commonly-used
circuit simulators like Cadence [24], HSPICE [25], and Mentor
Graphics [26]. Fig. 1 shows the proposed design flow, which is
based on the matrix representation of device characteristics in
CMOS technology. A practical approach is utilised to speed up
Fig. 1 Proposed approach to design and analyse CMOS circuits in a extracting the model parameters across the PVT corners and to
coding platform integrate all in the form of a monolithic SPICE-based matrix
model. The models are then utilised to elaborate on different
functions for the design and analysis of the circuits. These
functions are the building blocks for introducing CMOS circuits to
a computing environment like MATLAB [27]. A standard input to
the proposed functions is an equivalent matrix model of the
transistors’ data so that they can analyse different device variables
under the prescribed bias conditions. When used for circuit design,
the devices are sized as multiples of lambda (λ) of the technology.
No additional process is therefore required to rounding-off the
device sizes in advance to the layout drawing [28]. The circuit is
encoded in the form of the proposed functions (see Fig. 1), and the
results are finally uploaded to circuit simulator for detailed
verifications. Using the proposed design sequence, the time-to-
market will be reduced in comparison to the algorithms developed
using the random procedures, since all required transistor data are
already collected in the form of matrix model files. In the
following sections, we shall elaborate on the different phases of the
proposed flowchart. At first, the details to effectively convert the
SPICE models into trustable data matrix files are addressed in
Section 2. The proposed design and analysing functions are then
introduced in Section 3, where a simple common-source (CS)
amplifier example is designed and analysed using the
corresponding functions. Two other design examples, i.e. a folded-
cascode OTA and a voltage reference circuit, are analysed and
simulated using the sizing scripts presented in Section 4. In both
design cases, simulation results are compared to SPICE simulations
to verify the model's accuracy.

2 Matrix description of SPICE model files

The present gm /ID methodologies do not, conventionally, take into
account the effect of the gate channel width on the main design
variables such as gm /ID and gm /gO [8, 17–19, 21]. Instead, the
results from current density ID /W are used to calculate W when
gm /ID and ID are specified a priori as a function of L. Simulation
results show that the dependence of such parameters upon W is not
negligible when the gate size of the nano-scale devices is reduced
below 1 to 2 µm. Fig. 2 presents the variations of ID /W, gm /ID and
gm /gO against W for a pMOS transistor with different L scales in
Fig. 2 Dependence of ID /W, gm /ID and gm /gO upon W for a pMOS device
90-nm CMOS. The bias voltages are set to V GS = 0.45 V and
operating under V GS = 0.45 V and V DS = 0.55 V voltages (90-nm CMOS
V DS = 0.55 V. Clearly, the standard E.K.V. and square-law models
process)
predict unchanged ID /W, gm /ID and gm /gO once the device channel
MOS devices. Such methodology is extended in [19], enabling to dimensions, as well as its bias voltages, are preset. The plots in
design a single-stage gain-boosted amplifier using the gm /ID Fig. 2 show, however, that, although the main design parameters
subplots. The device sizing is according to the gm /ID and L factors are rather insensitive to W for sufficiently large gate widths, the
corresponding effect could be significant for the gate widths under
derived from intrinsic gain and transit frequency. The connections 1 to 2 µm, particularly when the channel length reaches its
between the circuit parameters and gm /ID, V DS and L have been minimum value (see Fig. 2). In the shadow of this second-order
quantified in [20], leading to an improved design flow for two- effect, we propose to store the channel width along with other
stage OTAs in nano-scale CMOS. The original gm /ID method is transistor data in the extracted SPICE-based matrix model, thereby
exploited in [8] to narrow the sizing procedure of OTA design enhancing the model accuracy for the smaller gate dimensions.
using NSGA-II. A similar OTA structure is realised in [23], and the The equivalent matrix representation of SPICE models is
design sequence is described in details as an example of employing generated here by considering MATLAB as a data platform and
the gm /ID method in 0.18-µm CMOS process. The design is such HSPICE as circuit simulator, with reference to the setup illustrated
that the expected performance in terms of gain-bandwidth (GBW) in Fig. 3. Simulation is traditionally rendered on a single MOSFET
using the SPICE model files provided by the foundry. The

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blocks into a sorted model file, a unique coding scheme is required
to distinguish between different devices and their characteristics.
Each nMOS (mn) or pMOS (mp) in the SPICE model file is
therefore labelled by a unique five-digit integer composing of L/λ
(two digits) and W /λ (three digits) in successive order (see Fig. 3).
The transistor features, as well as the gate sizes, are decoded by
dividing the associated label to 1000, and by multiplying the result
and the reminder to λ, consistent with the script presented in Fig. 4.
Suppose, e.g. that an nMOS is labelled by 02004 in 90-nm CMOS.
Dividing this number to 1000 yields 2 with a reminder of 4, leading
to L = 0.1 μm and W = 0.2 μm when λ is considered as 0.05 μm in
90-nm CMOS process. Fig. 4 contains the script to characterise the
above-stated mn02004, including the SPICE commands to measure
the threshold voltage, V TH and drain current through DC simulation
(vthn02004 and idn02004, respectively), and gm /ID, gm /gO and f T
from AC simulation. The general V GS, V DS and V SB are swept with
a step size set by MATLAB. The device current is highly sensitive
to V GS than to V DS and V SB, and the step size for V GS must be
considered smaller accordingly. In any case, reducing the step sizes
improves the accuracy at the cost of longer simulation time, owing
to the complications of interacting with larger model files. After
Fig. 3 Approach to speed up characterising the MOS devices in CMOS executing a data sorting algorithm, a matrix derivation of the
technology device parameters is generated for a particular process and
temperature corner. Referring to the matrix pattern in Fig. 4, it
contains the sorted device lengths (Column 1) along with the
corresponding ID /W, gm /ID, gm /gO and f T parameters (Columns 7
to 10), once the bias voltages were set to V GS, V DS and V SB
(Columns 4 to 6). The addition of V TH (Column 3) was to specify
the typical ranges for V GS and V DS, whereas W (Column 2) was
included in the shadow of the second-order effects quantified in
Section 2. In the end, the data file is stored with a filename which
identifies the device corner (TT: Typical nMOS, Typical pMOS;
FF: Fast nMOS, Fast pMOS; SS: Slow nMOS, Slow pMOS; FS:
Fast nMOS, Slow pMOS; SF: Slow nMOS, Fast pMOS) and
temperature, in order to be used later for circuit design and
analysis.
The model extraction procedures explained above is applied to
characterise a 90-nm CMOS process with devices operating under
1.0 V voltage supply. The possible gate sizes were considered as
L = 0.1 0.2 0.4 0.8 1.6 3.2 4.9 μ, and
W = 0.2 0.4 0.8 1.6 3.2 6.4 μ. The size of the model files is
minimised by sweeping V GS within the range of 0.15 and 0.45 V
with 0.005 V step, V DS from V GS − V TH to V GS + V TH with five
steps, and V SB ranging between 0.00 to 0.50 V by three steps. Each
model file consisting of the nMOS and pMOS devices in a process
and temperature corner occupies roughly 1.5 mega-byte (MB) disk
space. Higher gate-source voltages (VGSs) may be added to model
the operation in very strong inversion, if enlarging the size of the
model files is tolerated. The gm /ID factor spans from small to very
large quantities for operation in strong to weak inversion,
respectively. A large gm /ID realises low-power and high-gain
devices similar to bipolar devices, while small gm /ID ratios result in
high-speed devices.
Fig. 4 Generating a matrix derivation of the SPICE models
3 Systematic circuit design using matrix
variables V GS, V DS, V SB and L are swept in four dimensions, while
derivation of the SPICE models
the device specifications are stored in the form of data files for a
fixed W [8, 21]. To speed up the process of parameter extraction, 3.1 Generalised functions for design and analysis of the
we propose in this work to perform simultaneous simulations on circuits
multiple MOS devices operating with different gate scales, instead The extracted matrix derivation of SPICE models paves the way
of single device simulation in each simulation step. At this for design and analysis of the circuits in a coding environment. The
purpose, the devices are wired such that they can share common generalised functions depicted in Fig. 5 are proposed for this
V GS, V DS and V SB voltages during the simulation. These voltages purpose. The first step to analyse a CMOS circuit is to determine
are set by a data extraction program developed in MATLAB, the voltage/current dependence of the underlying MOSFETs. The
except that V SB of the pMOS devices is set to zero as long as they analysing functions presented in Fig. 5a, i.e. f I_VGS
can be realised in individual n-wells [1]. The link between (FuncPredictI_VGS) and f VGS_I (FuncPredictVGS_I), evaluate
MATLAB and HSPICE is established by filling the input file with ID of nMOS and pMOS devices from V GS and vice-versa. Assume
important specifications such as the operating temperature and the
process corner of the last run. The circuit is simulated, and the that the analysing functions are configured by the classical square-
entire transistor data block is transferred to our computing law expressions for long-channel nMOS devices operating in
environment in MATLAB. To enable converting the raw data
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Fig. 5 Generalised functions for
(a) Analysis, (b) Design of CMOS circuits

strong-inversion saturation only. Then the two functions will The following parameters are considered as input in the above
basically solve the following expressions: definitions:
TRType: Transistor type
ID = f I_VGS W, L, V DS, V SB, VGS L: Gate length,
1 W (1) W: Gate width,
= μC VGS − V TH 2 1 + λnV DS , M: Number of parallel devices,
2 n ox L
VDD: Supply voltage,
VGS = f VGS_I W, L, V DS, V SB, ID VDS: Drain-source voltage,
VSB: Source-bulk voltage,
2 × ID (2) SimType: Simulation type.
= V TH + ,
μnCox(W /L) 1 + λnV DS On the other hand, the main output is drain current (ID) or VGS,
depending on the type of the analysing function. The variations of
where μn and Cox are electron mobility and gate capacitance per ID versus VSB can also be measured by FuncPredictI_VGS, in
unit area, respectively, and λn is channel length modulation of the order to analyse the dependence of the drain current to body
nMOS devices. The equivalent relations cannot be formed voltage [29]. Other variables the proposed functions can calculate
analytically to describe the operation of short-channel MOSFETs are:
from weak to strong inversion, or from triode to saturation, gm: Device transconductance,
particularly when the effects of process and temperature variations ro: Output resistance,
are also included. Instead, the analysing functions can be Cg: Total gate capacitance,
configured to evaluate the correct I/V relationship by feeding these gmid: Device gm /ID.
functions with simulation-based matrix models. This way, the The possible options for ‘SimType’ are:
transconductance gm, and output resistance, rO can also be
evaluated from the stored gm /ID and gm /gO parameters by using the (a) Nominal: Simulation results are supplied for a typical MOSFET
following expressions between gm and rO and the elements of the operating at 25°C. The inputs and outputs are both scalars.
matrix pattern in Fig. 4: (b) Corner: Corner analysis is added, enabling to study the device
behaviour under the worst-case conditions. The input variables
∂ID VGS, VDS, VSB, and ID, as well as the output parameters, are
gm = = ID × gm /ID Matrix = ID × Col . 8. (3) vectors, specifying the parameter value at the different process and
∂V GS
temperature corners.
∂ID gm /gO Matrix Col . 9 (c) Temp: Temperature analysis is executed. The input VGS, VDS,
rO = = = . (4) VSB, and ID as well as the outputs are vectors, presenting the
∂V DS gm gm
temperature simulation results within a certain temperature range.
The sum of the gate-source, gate-drain and gate-bulk capacitors is A reference flowchart of the analysing functions is presented in
indicated by CG = CGS + CGD + CGB, and can be evaluated using Fig. 6a. After loading the device specifications, the matrix model is
f T stored in the matrix: checked for similar simulation results. Once available, the output
will be reported directly. Otherwise, interpolation is carried out
gm ID × Col . 8 based on the available data. This approach is re-iterated for all
CG = = . (5)
2π × f T Matrix 2π × Col . 10 outputs, and for other process and temperature corners once
demanded.
The generalised analysing functions are invoked in MATLAB by Several methodologies have been proposed to design the
using the following commands: analogue circuits based on devices transconductances and bias
TRType = ‘pMOS’; % ‘nMOS’, ‘pMOS’ currents [30–36]. We, therefore, present in Fig. 5b three design
SimType = ‘Temp’; % Simulation Type: functions to scale the gate sizes according to the required gm and
‘Nominal’, ‘Corners’, ‘Temp’ ID. This includes f W_Gm (FuncPredictW_Gm), f W_I
[gm,ro,Cg,VGS,gmid] = FuncPredictVGS_I (FuncPredictW_I), and f WL_IVGS (FuncPredictWL_IVGS),
(TRType,L,W,M,VDD,VDS,VSB,ID,SimType); which measure W from gm, W from ID and, ultimately, W and L
[gm,ro,Cg,ID,gmid] = FuncPredictI_VGS from ID and V GS, respectively, using the matrix model available for
(TRType,L,W,M,VDD,VDS,VSB,VGS,SimType); typical condition (TT + 25). When configured by the square-law
model of long-channel nMOS devices operating in strong inversion

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Fig. 6 Flowchart of the proposed functions for
(a) Analysis, (b) Design of CMOS circuits

saturation, the proposed design functions basically find a solution definitions are used to configure different design functions in
for the following expressions between the small- and large-signal MATLAB:
parameters: [W,M,ID,gm,ro,Cg,VGS,gmid] =
FuncPredictW_Gm(TRType,Lambda,L,VDD,VDS,VSB,gmidra
W, ID = f W_Gm L, V DS, V SB, gm /ID, gm nge,gm,SimType);
W, gm = f W_I L, V DS, V SB, gm /ID, ID ⇒ [W,M,gm,ro,Cg,VGS,gmid] =
FuncPredictW_I(TRType,Lambda,L,VDD,VDS,VSB,gmidran
W, L, gm = f WL_IVGS V DS, V SB, VGS, ID ge,ID,SimType);
W 1 + λnV DS [L,W,M,gm,ro,Cg,VGS,gmid] =
nMOS gm / ID = 2μnCOX
L ID (6) FuncPredictWL_IVGS(TRType,Lambda,VGS,VDD,VDS,VSB
in ,gmidrange,ID,SimType);
Strong gm = μnCOX W . In addition to the primary variables explained formerly for the
VGS − V TH
L analysing functions, the above functions take as input the desired
Inversion
W gm /ID range (gmidrange). This parameter allows a design function
Saturation gm = 2μnCOX 1 + λnV DS × ID
L to specify the device operating regime and to size it accordingly. In
the end, the exact gm /ID (gmid) value is made available at the
The required ID (or gm) will also be measured by the design output. Another input fed to the design functions is Lambda, which
functions in addition to the channel sizes evaluated from (6). In specifies the minimum allowable channel length along with the
presence of many second-order effects, the results should be, W /L scales available for the internal algorithm. Larger devices are
however, evaluated by feeding the generalised design functions the configured by smaller parallel devices fitted to allowable W range.
trustable transistor data stored in the matrix files. The following The factor M, therefore, determines the number of the parallel

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Fig. 7 Circuit design example using generalised design functions
(a) Implementation of CS amplifier using the proposed design functions, (b) Device sizing based on transconductance

devices required to achieve the desired gm and ID from TT + 25 The use of interpolation is reduced by exploring a nominee whose
model. Similar to the analysing functions, the results at other W is closest to the feasible device widths stored into the matrix.
process and temperature corners can be reported by activating This method minimises the second-order effect of W on gm /ID and
‘Corner’ or ‘Temp’ through the SimType variable. These options ID /W (Section 2), since the required simulation data for the new
are useful for investigation of the circuit robustness in the presence nominee are available already in the same matrix. The device is
of temperature and process variations, and to adopt a worst-case ultimately simulated using FuncPredictVGS_I to extract its
scenario. parameters across the process and temperature corners.
A reference flowchart for implementing the design functions is
displayed in Fig. 6b, which is, basically, to find the nominees of the 3.2 Circuit design using generalised design functions
devices' dimensions by using the data available for L, gm /ID, V DS
and V SB. Two items limit the search space in this case, enabling to Consider the CS amplifier with the resistive load, RL in Fig. 7a [8,
determine the required W (and L) from the given specifications. 16, 20]. It is a simple example for exploring the effectiveness of the
The first item is the desired gmidrange, while the second one is proposed design functions for short-channel devices operating with
the number of simulated points stored within the matrix data file. V DD = 1.0 V. The design is aimed at minimum voltage gain of
Regardless of the method of interpolation, interpolation causes AV = 6 V/V, once the DC bias point output voltage is set to
error at the points where no simulation data is available. The error V DC, O = 0.5 V. A GBW of 1 Mrad/s = 2π × 160 kHz is also
depends typically on the absolute distance of the vector between required for load capacitor of CL = 100 pF, while CG of the input
the unknown point and the adjacent points where simulation data is device, M1 should be kept to minimum in order to maximise the
available. The use of interpolation is minimised in the proposed fan-out, i.e. F . O . = CL /Cin.
algorithm, by limiting the scales of W and L to those quantities In the presence of the channel-length modulation, the voltage-
available already in the SPICE-based matrix models. The algorithm gain is expressed by [1]:
finds the results fitting to the desired gm /ID range, and detects those
values close to the input V DS and V SB. A list of nominees is vO
subsequently generated by intersecting the independent results. AV = = − gm1 rO1 ∥ RL . (8)
vi
Once unavailable, the required ID is also estimated for each
nominee by dividing the gm /ID ratio to gm, such that the gate width The only dominant pole at the output node is also algebraically
can be calculated as: assessed by:

ID 1
W= . (7) ωP ≃ − , (9)
ID /W Matrix rO1 ∥ RL CL

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yielding a GBW product of: higher power consumption. The choice of the device scales can be,
alternatively, based on the noise constraints [21], which yields
gm1 another gm for the function, FuncPredictW_Gm.
GBW = AV × ωP = . (10)
CL
4 Design examples
Fig. 7a lists the MATLAB script for design of such amplifier when
the generalised functions introduced in Section 3.1 are exploited. The systematic design flow explained in the previous sections is
The required transconductance of M1 is, at first, calculated from applied to design and simulate two principle blocks with extensive
gm1 = GBW × CL ≃ 100 μA/V. The function, FuncPredictW_Gm use in analogue design. A low-power reference generator and a
low-voltage CMOS OTA are designed in 90-nm CMOS process,
is then invoked to evaluate the required W for
using devices with a maximum voltage supply of 1.0 V. Analytical
V DS = V DC, O = 0.5 V, V SB = 0.0 V, along with a gm /ID of 10 to 15
analysis is carried out to accomplish the sizing procedures based on
for operation in moderate inversion. Using this function, the device the given specifications. The process corners considered for the
length can be swept over the feasible range to study the effect of simulation are TT, FF, and SS, while the temperature range is set to
the device length on the transistor parameters. Fig. 7b shows the [−25°C, 85°C].
result, reporting the device width (W), drain current (ID), gate-
source voltage (V GS), output resistor (rO), gate capacitance (CG), 4.1 Design of a low-voltage folded-cascode OTA
and gm /ID for each design candidate as a function of the gate
length. The effect of process and temperature variations on the Fig. 8 illustrates the structure of the low-voltage folded-cascode
parameters such as gm1 = 100 μA/V is additionally sketched by OTA simulated in this section. It is a single-stage fully-differential
choosing SimType = ‘Corners’. The device corner is shown by T, topology with one dominant pole at the output node, which results
F and S; to account for the typical, fast, and slow cases, in a GBW relation similar to (10). The target design specification is
respectively. Table 1 summarises the device parameters along with to maintain GBW = 2π × 1 MHz for CL = 1.2 pF, when the input
the amplifier's specifications corresponding to each nominee. The and output common-mode voltages are set to
choice of the device length is according to DC gain, consuming V CM, i = V CM, O = V DD /2 = 0.50 V. The transconductance of the
current, input capacitor, and layout area. For instance, choosing input pair, M1a − M1b, is therefore approximated as
L = 1.6 μ yields a DC gain of 7.0329 for rO1 = 1.1876 MΩ. The gm1 ≃ 7.50 μA/V. The second pole is located at the folding node
resulting gate capacitor (52.7213 fF) is, however, larger than the with a frequency of:
capacitor at the fourth row (CG1 = 13.2834 fF) which offers
AV = 6.5568 V/V. We, therefore, pick L = 0.8 μ and W = 1.6 μ gm3
ωp2 = , (11)
and M = 1 (number of the parallel devices) to satisfy a minimum CP3
voltage gain of 6.0 for ID = 6.8 μA, rO1 = 0.7043 MΩ,
CG1 = 13.2834 fF and gm /ID = 14.4827 V−1. A load resistance of where gm3 is the transconductance of the cascode devices,
0.0735 MΩ is then obtained for V DC, O = 0.5 V, while the M3a − M3b, and CP3 is the parasitic capacitor seen at the source
consuming power is limited to 1.0 V × 6.8 μA = 6.8 μW. Suppose terminal of these devices. Assuming an average parasitic capacitor
in the next step that we are restricted to a maximum power of of CP3 = 0.15 pF based on the possible device scales, a
5 μW. This restricts the bias current to ID1 = 5 μA, resulting to transconductance of gm3 = 10.50 μA/V is obtained to move the
RL = 0.10 MΩ for V CM, O = 0.5 V. The device sizing is thus second pole well beyond the GBW product at
accomplished by employing FuncPredictW_I instead of ωp2 = 10 × GBW = 2π × 10 MHz. We start the design procedures
FuncPredictW_Gm for a bias current of 5 μA. The possible device by choosing L0 = 3.2μ, L1 = 1.6μ, and L2 = L3 = L4 = 4.9μ for M0
sizes, along with design specifications, are shown in Table 2. There and M1a − M1b to M4a − M4b, respectively, after taking into account
are different options to scale the gate channel according to the new the role of the gate lengths on DC gain, bandwidth, voltage offset
design condition. For instance, choosing L = 3.2 μ and W = 3.2 μ and CMRR (see Section 3.2) [23]. The length of M5 is determined
yields gm1 = 63.1745 μA/V, rO1 = 2.9020 MΩ, CG1 = 107.0067 fF, later by the design flow. An optimal gm /ID range of 10 to 14 is
gm /ID = 12.6349 V−1 and AV = 6.1070 V/V, leading to considered for operation in moderate inversion. The bias voltages
GBW ≃ 630 krad/s = 2π × 100 kHz instead of the 1 Mrad/s are set to V B3 = 0.60 V, V B4 = 0.40 V, whereas a common-mode
achieved by the previous design solution which is at the cost of

Table 1 Possible device sizes along with the amplifier specifications for gm1 = 100 μA/V
Lμ W μ M ID, μA V GS, V gm, μA/V rO, MΩ CG, fF gm /ID, V−1 RL, MΩ AV
0.1 0.2 1.0 8.8 0.4073 103.1445 0.1142 0.2264 11.7210 0.0568 3.9134
0.2 0.4 1.0 7.9 0.3871 100.2281 0.2614 0.8740 12.6871 0.0633 5.1069
0.4 0.8 1.0 7.3 0.3636 99.7281 0.4384 3.3964 13.6614 0.0685 5.9078
0.8 1.6 1.0 6.8 0.3449 98.4824 0.7043 13.2834 14.4827 0.0735 6.5568
1.6 3.2 1.0 6.5 0.3314 97.3498 1.1876 52.7213 14.9769 0.0769 7.0329
3.2 6.4 1.0 6.4 0.3234 97.5416 2.0392 212.9717 15.2409 0.0781 7.3393
4.9 6.4 1.0 8.8 0.3809 99.3097 2.4137 334.6873 11.2852 0.0568 5.5128

Table 2 Possible device sizes and the amplifier specifications for ID1 = 5 μA
Lμ W μ M ID, μA V GS, V gm, μA/V rO, MΩ CG, fF gm /ID, V−1 RL, MΩ AV
0.2 0.2 1.0 5.0 0.3875 57.4490 0.4467 0.4572 11.4898 0.1000 4.6941
0.4 0.4 1.0 5.0 0.3833 58.4346 0.7033 1.7764 11.6869 0.1000 5.1160
0.8 0.8 1.0 5.0 0.3772 60.3516 1.0870 6.9259 12.0703 0.1000 5.5267
1.6 1.6 1.0 5.0 0.3674 62.2048 1.7304 27.1467 12.4410 0.1000 5.8806
3.2 3.2 1.0 5.0 0.3600 63.1745 2.9020 107.0067 12.6349 0.1000 6.1070
4.9 3.2 1.0 5.0 0.3957 52.6040 4.3860 167.5988 10.5208 0.1000 5.1431

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Fig. 8 Circuit topology and MATLAB design script of the OTA

feedback (CMFB) voltage of V CMFB = 0.70 V is applied to the gate ID2a, b = ID1a, b + ID3a, b, (15)
of M5a − M5b.
Fig. 8 presents the list of the commands to implement the full V DS2a, b = V B3 − V GS3a, b, (16)
OTA structure in MATLAB, regarding the generalised functions
introduced in Section 3. It is necessary to perceive how the prior to estimation of W 2 using FuncPredictW_I. The size of
voltages are generated and, in turn, to specify which parameter M4a − M4b is found similarly by setting ID4a, b = ID3a, b after
should be defined earlier in the program. At first, the bias current, assuming V DS4a . b = 0.3 V for the first design iteration. The drain
ID1a, b as well as the channel width, W 1 of the input devices is current ID5a, b, is set to ID4a, b, whereas V DS5a . b is calculated from:
obtained by calling FuncPredictW_Gm for gm1 = 7.50 μA/V,
which is the overall OTA transconductance required. To use this V DS5a . b = V DD − V B4 + V GS4a, b . (17)
function, it is, however, essential to assume an initial state for the
drain-source voltages of the input devices. We, therefore, start the The function FuncPredictWL_IVGS is therefore used to calculate
design loop by considering V DS1a, b = 0.5 V, and by revising this W and L of M5a − M5b according to the derived voltages and
parameter based on subsequent simulation data. The tail device, M0 currents for these devices. The last step for the current design
is sized after the input pair by invoking FuncPredictW_I for iteration is to update the initial state of V DS1a, b and V DS4a . b
ID0 = 2ID1a, b, obtaining W 0 as well as V GS0 through the calculation consistent with expressions (18) and (19):
of V DS0 from:
V DS1a, b = V CM, i + V GS1a, b − V B3 − V GS3a, b , (18)
V DS0 = V DD − V CM, i + V GS1a, b . (12)
V DS4a . b = V B4 + V GS4a, b − V CM, O . (19)
The voltages
The design is converged after few iterations when V DS1a, b and
V SB3a, b = V DD − V DS0 − V DS1a, b, (13) V DS4a . b are settled down to their quiescent condition. This is
fulfilled irrespective of the prescribed V DS1a, b and V DS4a . b ,
V DS3a, b = V CM, O − V SB3a, b, (14) consistent with the results in Fig. 9 where the evolution of V DS1a, b
and V DS4a . b is shown as a function of design iteration. Despite the
are derived from the V GS0, V DS0 and V DS1a, b values, enabling to find
different initial voltages considered for the first design iteration, the
W 3 of M3a − M3b by executing FuncPredictW_Gm for
loop is able to settle down to the correct V DS1a, b = 0.6201 V and
gm3 = 10.50 μA/V. The voltage and the current of M2a − M2b are
V DS4a . b = 0.2527 V after 3 to 5 iterations. Table 3 summarises the
calculated as:
final device sizes and bias currents. The same structure is simulated

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Fig. 9 Evolution of the initial V DS1a, b and V DS4a . b to the final value

Table 3 Device sizes and bias currents

Transistor Lμ W μ ID, μA
M0 3.2 6.4 1.2
M1a,b 1.6 0.8 0.6
M2a,b 4.9 1.6 1.5
M3a,b 4.9 0.8 0.9
M4a,b 4.9 3.2 0.9
M5a,b 0.8 0.8 0.9

Fig. 10 Comparison of MATLAB and SPICE

(a) gm /ID, (b) Overall transconductance

Fig. 11 Circuit architecture and MATLAB code used for the simulated reference circuit

in 90-nm CMOS to verify the accuracy of the results in the the MATLAB and SPICE simulation results for devices’ gm /ID
presence of process and temperature variations. Fig. 10a compares across the process and temperature corners. SPICE simulations

440 IET Circuits Devices Syst., 2020, Vol. 14 Iss. 4, pp. 432-443
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Table 4 Element values and bias currents from the design
script
Element Lμ W μ Value, MΩ ID, μA
M1 4.9 0.8 — 0.2769
M2 4.9 0.8 — 0.2496
M3 1.6 0.8 — 0.2496
M4 1.6 0.2 — 0.2769
R1 — — 0.226 0.2769
R2 — — 0.365 0.2769

predict almost identical values extracted from the MATLAB

program. The error percentage exceeds barely 15% across the
different corners, despite the fact that minimum simulation points
are added to the MATLAB model files to limit their sizes to 1.5
MB (Section 2). Fig. 10b depicts the overall transconductance in
different process and temperature corners. The 13% gm variation
from SPICE is predicted almost correctly by the algorithm,
demonstrating the benefits of the adopted gm /ID functions for
circuit design and analysis with sufficient accuracy.

4.2 Design of a low-power reference generator

The effectiveness of the generalised design and analysing functions
is also validated through simulation of the reference circuit shown
in Fig. 11 [37, 38]. The bias current and voltage of the OTA in
Section 4.1 are generated by another bias circuit, whereas the
reference circuit in this section is a self-biased topology with the
low-frequency operation. In the absence of serious line voltage and
load current variations, the upper limit of the device sizes will not,
therefore, be bounded by AC operation. The circuit generates the
temperature-insensitive V REF voltage, by combining the effect of a
proportional-to-absolute-temperature (PTAT) IPTAT current with a
complementary-to-absolute-temperature V GS4 voltage. The PTAT
current is originating from the VGS difference of the nMOS
devices, M3 and M4 operating in weak inversion as shown as
follows:

V GS4 − V GS3
IPTAT = ID1 = . (20)
R1

In theory, the voltage–current dependence of an nMOS operating in

weak inversion is approximated by [39]:

W V GS V DS
ID = I exp 1 − exp − , (21)
L 0 NV T VT

where N denotes the slope factor, I0 is a temperature-dependent Fig. 12 Comparison between SPICE and MATLAB simulation results
parameter, and V T = kT /q refers to the thermal PTAT voltage (k is (a) gm /ID of the devices versus temperature, (b) PTAT current against temperature, (c)
Boltzmann's factor, T is absolute temperature, and q is the electron Variation of V REF in different process and temperature corners
charge). Combining (20) and (21), and by neglecting the channel
length-modulation, the PTAT current will be therefore related to expression. We, therefore, start the sizing sequence by choosing a
temperature by [38]: gm /ID range of [10–14] and [22–25] for the pMOS and nMOS
devices, respectively, in line with the sizing commands listed in
NV T W /L 2 W /L 4
IPTAT ≃ ln Fig. 11. The device lengths are also set to L1 = L2 = 4.9 μ and
R1 (W /L)1 (W /L)3
(22) L3 = L4 = 1.6 μ. The gate width of M1 is scaled by invoking
NkT W /L 2 W /L 4 FuncPredictW_I for the required IPTAT. To improve the
= ln .
qR1 (W /L)1 (W /L)3 matching, the gate width of M2 is set equal to that of M1, and the
exact ID2 is calculated by invoking FuncPredictVGS_I for
A temperature-independent output V REF is finally established by V GS2 = V GS1. Subsequently, the gate width of M3 is determined by
adding V GS4 with the voltage drop across R1 + R2 through IPTAT: configuring FuncPredictW_I with ID3 = ID2. The sizing of W 4 is
based on the current peaking condition from the analytical
V REF = V GS4 + R1 + R2 × IPTAT . (23) expression shown in (21) [40–42]:

Under the nominal temperature condition of +25°C, the circuit is W /L 4 W

= e ⇒ W4 = 3 , (24)
designed for the desired voltage reference and PTAT current of (W /L)3 e
0.39 V and 0.28 μA, respectively. The pMOS devices, M1 and M2
are working in strong inversion as current mirror, whereas the
nMOS devices are operating in weak inversion to support the IPTAT

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