Combinational Circuits

Dr. Nilesh Patidar and Mr. Shiraz Husain

Combinational Circuits

X1 Y1
X2 Y2
Combinational
n number X3 Circuit Y3 m number
of inputs X4 Y4 of outputs
(Logic Gates)

….
….

Xn Ym

Does not contain any memory element/feedback path

Dr. Nilesh Patidar and Mr. Shiraz Husain 2
Half adder
◼ Half adder is used for addition of 2 bits.

A B Sum Carry

A Sum 0 0 0 0
Half Truth 0 1 1 0
Adder Table
B Carry 1 0 1 0

1 1 0 1

Dr. Nilesh Patidar and Mr. Shiraz Husain 3

 Half adder
B B’ B B B’ B
A (0) (1) A (0) (1)

A’ A’
K-map 0 1 K-map
0 0
(0) 0 1 (0) 0 1
for for
Sum A Carry A
1 0 0 1
(1) (1) 2 3
2 3

Sum = AB’+A’B Carry = AB

= AB

Dr. Nilesh Patidar and Mr. Shiraz Husain 4

Half adder

A
Sum
B

Carry

Logic Circuit of Half adder

Dr. Nilesh Patidar and Mr. Shiraz Husain 5

Full adder
A B C Sum Carry

◼ Full adder is used for 0 0 0 0 0

0 0 1 1 0
addition of 3 bits.
0 1 0 1 0

0 1 1 0 1
Truth
A Sum
Full Table 1 0 0 1 0
B Adder 1 0 1 0 1
C Carry
1 1 0 0 1

1 1 1 1 1

Dr. Nilesh Patidar and Mr. Shiraz Husain 6

Full adder
BC B’C’ B’C BC BC’
A (00) (01) (11) (10)
A’
K-map 0 1 0 1
(0) 0 1 3 2
for
Sum A
1 0 1 0
(1) 4 5 7 6

Sum = AB’C’+ABC+A’B’C+A’BC’
= A(B’C’+BC)+A’(B’C+BC’)
= A(BC)’+ A’(BC)
= ABC
Dr. Nilesh Patidar and Mr. Shiraz Husain 7
Full adder
BC B’C’ B’C BC BC’
A (00) (01) (11) (10)

K-map A’
0 0 1 0
for (0) 0 1 3 2
Carry A
0 1 1 1
(1) 4 5 7 6

Carry = AC + BC + AB

Dr. Nilesh Patidar and Mr. Shiraz Husain 8

Full adder
BC B’C’ B’C BC BC’
A (00) (01) (11) (10)

K-map A’
0 0 1 0
for (0) 0 1 3 2
Carry A
0 1 1 1
(1) 4 5 7 6

Carry = AB’C+A’BC+AB
= (AB’+A’B)C+AB
= (AB)C+AB
Dr. Nilesh Patidar and Mr. Shiraz Husain 9
Full adder

?
A
B Sum

Carry

logic circuit of full adder

Dr. Nilesh Patidar and Mr. Shiraz Husain 10
Design of Full adder using Half adders
◼ Full adder can be designed by using 2 half adders and 1
OR gate.
AB
A Sum (ABC)
Half Half
Adder AB Adder (AB).C
B

C OR Carry
(AB).C +AB
Dr. Nilesh Patidar and Mr. Shiraz Husain 11
Half Subtractor
◼ Half Subtractor is used for subtraction of 2 bits.

Differe
A B Borrow
nce

A Difference 0 0 0 0
Half Truth 0 1 1 1
Subtractor Table
B Borrow 1 0 1 0

1 1 0 0

Dr. Nilesh Patidar and Mr. Shiraz Husain 12

 Half subtractor
B B’ B B B’ B
A (0) (1) A (0) (1)

A’ A’
0 1 K-map
0 1
K-map (0) 0 1 (0) 0 1
for for
Differ A Borrow A
1 0 0 0
ence (1) (1) 2 3
2 3

Difference = AB’+A’B Borrow = A’B

= AB

Dr. Nilesh Patidar and Mr. Shiraz Husain 13

Half subtractor

A
Difference
B

Borrow

Logic Circuit of Half subtractor

Dr. Nilesh Patidar and Mr. Shiraz Husain 14

Full Subtractor Differe
A B C Borrow
nce

◼ Full Subtractor is used for 0 0 0 0 0

subtraction of 3 bits. 0 0 1 1 1
Truth 0 1 0 1 1
Table
0 1 1 0 1
A Full Difference
1 0 0 1 0
B Subtra-
ctor 1 0 1 0 0
C Borrow
1 1 0 0 0

1 1 1 1 1

Dr. Nilesh Patidar and Mr. Shiraz Husain 15

Full subtractor
BC B’C’ B’C BC BC’
A (00) (01) (11) (10)
A’
K-map 0 1 0 1
(0) 0 1 3 2
for
Diff. A
1 0 1 0
(1) 4 5 7 6

Difference = AB’C’+ABC+A’B’C+A’BC’
= A(B’C’+BC)+A’(B’C+BC’)
= A(BC)’+ A’(BC)
= ABC
Dr. Nilesh Patidar and Mr. Shiraz Husain 16
Full subtractor
BC B’C’ B’C BC BC’
A (00) (01) (11) (10)
A’
K-map 0 1 1 1
(0) 0 1 3 2
for
Borrow A
0 0 1 0
(1) 4 5 7 6

Borrow = A’C + BC + A’B

Dr. Nilesh Patidar and Mr. Shiraz Husain 17

Full subtractor

Dr. Nilesh Patidar and Mr. Shiraz Husain 18

Parallel Adder (4-bit)

◼ Example: C 4C 3C 2C 1 Initial Carry

0010
1001 Input A (A4A3A2A1)
+1101 Input B (B4B3B2B1)
Cout 10110 Sum
S4S3S2S1

Dr. Nilesh Patidar and Mr. Shiraz Husain 19

Parallel Adder (n-bit)

It is also known as ripple carry adder

Dr. Nilesh Patidar and Mr. Shiraz Husain 20
Parallel Adder (n-bit) - Working
1. As shown in the figure, firstly the full adder FA1 adds A1 and B1 along
with the carry C1 to generate the sum S1 (the first bit of the output sum)
and the carry C2 which is connected to the next adder in chain.
2. Next, the full adder FA2 uses this carry bit C2 to add with the input bits A2
and B2 to generate the sum S2(the second bit of the output sum) and the
carry C3 which is again further connected to the next adder in chain and so
on.
3. The process continues till the last full adder FAn uses the carry bit Cn to
add with its input An and Bn to generate the last bit of the output along
last carry bit Cout.

Dr. Nilesh Patidar and Mr. Shiraz Husain 21

 Advantages
Parallel Adder • The parallel adder/subtractor performs the
addition operation faster as compared to serial
adder/subtractor.
• Time required for addition does not depend on
the number of bits.
• The output is in parallel form i.e all the bits are
added/subtracted at the same time.
• It is less costly.

Disadvantages

• Each adder has to wait for the carry which is to

be generated from the previous adder in chain.
• The propagation delay( delay associated with the
travelling of carry bit) is found to increase with the
increase in the number of bits to be added.

Dr. Nilesh Patidar and Mr. Shiraz

Husain 22
Multiplexer (MUX)
I0
I1 Multiplexer
I2 2n x 1
2n number
of inputs Y
I3 (Combinational (only one
….

Circuit) output)
I(2n-1)
….
Sn-1 S1 S0

n select lines Symbolic

It is also called Data
Dr. Nilesh PatidarSelector
and Mr. Shiraz Husain Representation 26
2x1 Multiplexer S I0 I1 Y
0 0 0 0
Truth
Table 0 0 1 0
I0 0
2x1 0 1 0 1
Y
MUX 0 1 1 1
I1 1
1 0 0 0
1 0 1 1
S 1 1 0 0
S Y 1 1 1 1
Function
0 I0
Table
1 I1 Y = S’I0 +SI1
Dr. Nilesh Patidar and Mr. Shiraz Husain 27
2x1 Multiplexer

I0 I1 I0’I1’ I0’I1 I0I1 I0I1’

S (00) (01) (11) (10)
K-map S’
for 0 0 1 1
(0) 0 1 3 2
2x1 MUX
S
0 1 1 0
(1) 4 5 7 6

Y = S’I0 +SI1

Dr. Nilesh Patidar and Mr. Shiraz Husain 28

2x1 Multiplexer

Y = S’I0 +SI1
Dr. Nilesh Patidar and Mr. Shiraz Husain 29
4x1 Multiplexer
S1 S0 Y

I0 00 0 0 I0
I1 01 4x1
Y Function 0 1 I1
I2 10 MUX
Table
I3 11 1 0 I2

S1 S0 1 1 I3

Y = S1’S0’I0+ S1’S0I1 + S1S0’I2 + S1S0I3

Dr. Nilesh Patidar and Mr. Shiraz Husain 30
4x1 Multiplexer

Y = S1’S0Dr.
’I0Nilesh ’S0I1and
+ S1Patidar 0’I2 Husain
+ SMr.1SShiraz + S1S0I3 31
4x1 MUX using 2x1 MUX S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
i2
i0
i1
i3 1 1 I3
1
0 Y

S0=1
=0 S1=1
=0
Dr. Nilesh Patidar and Mr. Shiraz Husain 32
Dr. Nilesh Patidar and Mr. Shiraz Husain 33
Mux quantity as per design

Given Mux To be implemented Required Quantity

2:1 16:1 8+4+2+1 = 15
4:1 16:1 4+1 = 5
4:1 64:1 18+4+1=21
8:1 64:1 8+1=9
8:1 256:1 32+4+1=37

Dr. Nilesh Patidar and Mr. Shiraz Husain 34

8x1 Multiplexer
• To implement the 8×1
multiplexer, we need two 4×1
multiplexers and one 2×1
multiplexer. The 4×1
multiplexer has 2 selection
lines, 4 inputs, and 1 output.
The 2×1 multiplexer has only
1 selection line.
• For getting 8 data inputs, we
need two 4×1 multiplexers.
The 4×1 multiplexer produces
one output. So, in order to get
the final output, we need a
2×1 multiplexer.
Dr. Nilesh Patidar and Mr. Shiraz
Husain 35
 De-Multiplexer (De-MUX)
Y0

De-Multiplexer Y1
1 x 2n Y2 2n number
Din of outputs
(only one (Combinational Y3
Circuit)

….
input)
Y(2n-1)
….
Sn-1 S1 S0 Symbolic
Representation
n select lines
Dr. Nilesh Patidar and Mr. Shiraz Husain 36
1x2 De-Multiplexer
S Din Y0 Y1

0 Y0 0 0 0 0
Din 1:2
De-MUX Truth 0 1 1 0
1 Y1 Table
1 0 0 0

S 1 1 0 1

S Y0 Y1
Function
0 Din 0 Y0 = S’Din
Table
1 0 Din Y1 = SDin
Dr. Nilesh Patidar and Mr. Shiraz Husain 37
1x2 De-Multiplexer

Y0 = S’Din

Y1 = SDin

Dr. Nilesh Patidar and Mr. Shiraz Husain 38

1x4 De-Multiplexer
S1 S0 Y0 Y1 Y2 Y3

00 Y0 0 0 Din 0 0 0

1x4 01 Y1
Din 0 1 0 Din 0 0
DeMUX 10 Y2 Function
Table 1 0 0 0 Din 0
11 Y3
1 1 0 0 0 Din
S1 S0
Y0= S1’S0’Din Y2= S1S0’Din

Y1= S1’S0Din Y3= S1S0Din

Dr. Nilesh Patidar and Mr. Shiraz Husain 39
1x4 De-Multiplexer
Y3= S1S0Din

Y2= S1S0’Din

Y1= S1’S0Din

Y0= S1’S0’Din
Dr. Nilesh Patidar and Mr. Shiraz Husain 40
Multiplexer (as universal logic gate)
◼ Multiplexer is also act as universal logic gate.
◼ It means that any of the logic circuit/gate can be
implemented with the help of multiplexer.

Dr. Nilesh Patidar and Mr. Shiraz Husain 41

Implementation using MUX (Method 1)
◼ Example: Design 2-input OR gate with the help of MUX.
 The Boolean equation for OR gate is-
F(A,B) = A+B
 First choose the size of MUX-
◼ No. of select lines (n) = No. of variables in given Boolean function
◼ No. of select lines (n) = 2 (A,B)
◼ No. of inputs (2n) = 4
◼ It requires 4:1 MUX to implement OR gate

Dr. Nilesh Patidar and Mr. Shiraz Husain 42

Implementation using MUX (Method 1)
A B F
I0 00 F(A,B) = A+B 0 0 0 I0
I1 01 4x1 0 1 1 I1
Y Truth Table
I2 10 MUX of OR 1 0 1 I2
I3 11 1 1 1 I3

S1 S0 S1 S0 Y 0 00
0 0 I0 1 01 4x1
F = A+B
Function
0 1 I1 1 10 MUX
Table
of MUX
1 11
1 0 I2
1 1 Dr.I3Nilesh Patidar and Mr. Shiraz Husain
A B 43
Implementation using mux (Method 1)
◼ F(A,B,C) = ∑m(1,3,5,6)

Dr. Nilesh Patidar and Mr. Shiraz Husain 44

Implementation using MUX (Method 2)
◼ Example: Design 2-input OR gate with the help of 2:1
MUX.
 The Boolean equation for OR gate is-
F(A,B) = A+B
 First choose the size of MUX-
◼ No. of select lines (n) = No. of variables - 1
◼ No. of select lines (n) = 2 – 1 = 1
◼ No. of inputs (2n) = 2
◼ It requires 2:1 MUX to implement OR gate
Dr. Nilesh Patidar and Mr. Shiraz Husain 45
Implementation using MUX (Method 2)
A 0 F(A,B) = A+B
2x1 Decim A B F
Y al
MUX
1 Truth Table 0 0 0 0
1 of OR
1 0 1 1
2 1 0 1
B
3 1 1 1
Column I0 I1
A’ 0 1
A 2 3 S=B
A 1
Dr. Nilesh Patidar and Mr. Shiraz Husain 46
Implementation using mux (Method 2)
F(A,B,C) = ∑m(1,3,5,6)

Dr. Nilesh Patidar and Mr. Shiraz Husain 47

Implementation using MUX (Method 2)
Design the following function by using MUX
F(A,B,C) = Ʃm(0,4,5,7)

Solution: First choose the size of required MUX-

◼ No. of select lines (n) = No. of variables - 1
◼ No. of select lines (n) = 3 – 1 = 2
◼ No. of inputs (2n) = 4
◼ It requires 4:1 MUX to implement the given function

Dr. Nilesh Patidar and Mr. Shiraz Husain 48

Implementation using MUX (Method 2)
1 00 F(A,B,C) = Ʃm(0,4,5,7) Deci A B C F
A mal
01 4x1
Y 0 0 0 0 1
0 10 MUX
Truth 1 0 0 1 0
A 11 Table
2 0 1 0 0

B C 3 0 1 1 0
4 1 0 0 1
Column I0 I1 I2 I3 S1 = B
5 1 0 1 1
A’ 0 1 2 3 S0 = C
A 4 5 6 7 6 1 1 0 0
1 A 0 A 7 1 1 1 1
Dr. Nilesh Patidar and Mr. Shiraz Husain 49
Question
◼ Implement the following function using 8:1 Mux
 F(P,Q,R,S) = ∑m(0,1,3,4,8,9,15)

Dr. Nilesh Patidar and Mr. Shiraz Husain 50

 Question
◼ Implement the following
function using 8:1 Mux
 F(P,Q,R,S) =
∑m(0,1,3,4,8,9,15)

Dr. Nilesh Patidar and Mr. Shiraz Husain 51

 Question
◼ Implement the following
function using 8:1 Mux
 F(A,B,C,D) =
∑m(0,2,6,10,11,12,13) +d(3,8,14)

Dr. Nilesh Patidar and Mr. Shiraz Husain 52

 Question
◼ Implement the following
function using 8:1 Mux
 F(A,B,C,D) =
∑m(0,2,6,10,11,12,13) +d(3,8,14)

Taking Don’t care as 1

we have removed the
inverter
Dr. Nilesh Patidar and Mr.for Abar
Shiraz Husain 53
Decoder
X0 Y0

X1 Decoder Y1
N x 2N Y2
N number X2 2N number
of inputs Y3 of outputs
X3 (Combinational

….
Circuit)
….

XN-1 Y(2N-1)

E (enable)

Dr. Nilesh Patidar and Mr. Shiraz Husain 54

2x4 Decoder
A Y0
E A B Y0 Y1 Y2 Y3
B Y1
2x4 Truth 0 X X 0 0 0 0
Decoder Y2 Table
E 1 0 0 1 0 0 0
Y3
1 0 1 0 1 0 0
Y0 = EA’B’ Y2 = EAB’ 1 1 0 0 0 1 0
Y1 = EA’B Y3 = EAB 1 1 1 0 0 0 1

Dr. Nilesh Patidar and Mr. Shiraz Husain 55

2x4 Decoder

Dr. Nilesh Patidar and Mr. Shiraz Husain 56

3x8 Decoder
A Y0
B Y1
Y2
C
3x8 Y3
Decoder Y4
Y5
Y6
E
Y7

Dr. Nilesh Patidar and Mr. Shiraz Husain 57

3x8 Decoder
E A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 X X X 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 1 0 0 0 0 0 0
Truth
Table
1 0 1 0 0 0 1 0 0 0 0 0
1 0 1 1 0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0 1 0 0 0
1 1 0 1 0 0 0 0 0 1 0 0
1 1 1 0 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 1
Dr. Nilesh Patidar and Mr. Shiraz Husain 58
3x8 Decoder
Y0 = EA’B’C’
Y1 = EA’B’C
Y2 = EA’BC’
Y3 = EA’BC
Y4 = EAB’C’
Y5 = EAB’C
Y6 = EABC’
Y7 = EABC
Dr. Nilesh Patidar and Mr. Shiraz Husain 59
Dr. Nilesh Patidar and Mr. Shiraz Husain 60
4:16 Decoder using 3:8
Decoder

Dr. Nilesh Patidar and Mr. Shiraz

Husain 61
Encoder
X0 Y0
X1 Encoder Y1
X2 2N x N Y2
2N number N number
of inputs X3 Y3 of outputs
(Combinational

….
Circuit)
….

X(2N-1) YN

Dr. Nilesh Patidar and Mr. Shiraz Husain 62

4x2 Encoder
D0 D1 D2 D3 Y1 Y0
D0
Y0
D1 1 0 0 0 0 0
4x2 Truth
D2 Encoder Table 0 1 0 0 0 1
Y1
D3 0 0 1 0 1 0

0 0 0 1 1 1
Y0 = D1+D3
X X X X X X
Y1 = D2+D3

Dr. Nilesh Patidar and Mr. Shiraz Husain 63

4x2 Encoder
D2D3
D0D1

0 1 3 2
K-map for
Y0 of 4x2
Encoder 4 5 7 6

12 13 15 14

8 9 10 11

Y0 = D1+D3
Dr. Nilesh Patidar and Mr. Shiraz Husain 64
4x2 Encoder
D2D3
D0D1

0 1 3 2
K-map for
Y1 of 4x2
Encoder 4 5 7 6

12 13 15 14

8 9 10 11

Y1 = D2+D3
Dr. Nilesh Patidar and Mr. Shiraz Husain 65
4x2 Encoder

Y1 = D2+D3

Y0 = D1+D3

Dr. Nilesh Patidar and Mr. Shiraz Husain 66

8x3 Encoder (Octal to Binary)
D0 D1 D2 D3 D4 D5 D6 D7 Y2 Y1 Y0
D0
D1 Y0 1 0 0 0 0 0 0 0 0 0 0
D2 8x3
D3 0 1 0 0 0 0 0 0 0 0 1
Octal to
D4 Binary
Y1
0 0 1 0 0 0 0 0 0 1 0
D5 Encoder
D6 0 0 0 1 0 0 0 0 0 1 1
Y2
D7
0 0 0 0 1 0 0 0 1 0 0

Y0 = D1+D3+D5+D7 0 0 0 0 0 1 0 0 1 0 1
Truth 0 0 0 0 0 0 1 0 1 1 0
Y1 = D2+D3+D6+D7 Table
Y2 = D4+D5+D6+D7 0 0 0 0 0 0 0 1 1 1 1
X X X X X X X X X X X
Dr. Nilesh Patidar and Mr. Shiraz Husain 67
8x3 Encoder (Octal to Binary)

Y2 = D4+D5+D6+D7

Y1 = D2+D3+D6+D7

Y0 = D1+D3+D5+D7

Dr. Nilesh Patidar and Mr. Shiraz Husain 68

Decoder (as universal logic gate)
◼ Decoder is also act as universal logic gate.
◼ It means that any of the logic circuit/gate can be
implemented with the help of Decoder.

Dr. Nilesh Patidar and Mr. Shiraz Husain 69

Implementation of Half adder using decoder
◼ First, find out the no. of inputs required.

A Sum
Half
Adder
B Carry

◼ So, half adder has 2 inputs.

◼ It means 2x4 decoder is required to design a half adder.

Dr. Nilesh Patidar and Mr. Shiraz Husain 70

Implementation of Half adder using decoder
Decimal A B Sum Carry

0 0 0 0 0
Truth 1 0 1 1 0
Table of
Half adder 2 1 0 1 0

3 1 1 0 1

Sum = Ʃm(1,2)

Carry = Ʃm(3)

Dr. Nilesh Patidar and Mr. Shiraz Husain 71

Implementation of Half adder using decoder

Sum =Ʃm(1,2)

Carry = Ʃm(3)

Dr. Nilesh Patidar and Mr. Shiraz Husain 72

Decoder (as universal logic gate)
◼ Implement a full adder with the help of decoder.
 First, find out the no. of inputs required.

A Sum
Full
B Adder
C Carry

 So, full adder has 3 inputs.

 It means 3x8 decoder is required to design a full adder.
Dr. Nilesh Patidar and Mr. Shiraz Husain 73
Implementation of full adder using decoder
Decimal A B C Sum Carry

0 0 0 0 0 0
Truth 1 0 0 1 1 0
Table of
Full adder 2 0 1 0 1 0

3 0 1 1 0 1

4 1 0 0 1 0
Sum = Ʃm(1,2,4,7)
5 1 0 1 0 1
Carry = Ʃm(3,5,6,7)
6 1 1 0 0 1

7 1 1 1 1 1
Dr. Nilesh Patidar and Mr. Shiraz Husain 74
Implementation of full adder using decoder

Sum =Ʃm(1,2,4,7)

Carry = Ʃm(3,5,6,7)

Dr. Nilesh Patidar and Mr. Shiraz Husain 75

BCD Adder
◼ BCD stand for binary coded decimal. (Range from 0 to 9)

Maximum value of any BCD numbers is 9. So, maximum sum of two

BCD numbers are 18 (without any carry) and 19 (in case of previous
carry)
BCD Sum = 9 + 9 + 1(carry) = 19
Dr. Nilesh Patidar and Mr. Shiraz Husain 76
BCD Adder

◼ Example: Add two BCD numbers.

1001 9 (in BCD)
+0101 5 (in BCD)
Binary Sum 1110 14 (in Decimal)
+0110 add 6 (in case of sum>9)
BCD Sum 0 0 0 1 0 1 0 0 1 4 (in BCD)

Dr. Nilesh Patidar and Mr. Shiraz Husain 77

BCD Adder

Dr. Nilesh Patidar and Mr. Shiraz Husain 78

BCD Adder
We are adding “0110” (=6) only to the second half of the
table.
The conditions are:
 If C’ = 1 (Satisfies 16-19)
 If S3′.S2′ = 1 (Satisfies 12-15)
 If S3′.S1′ = 1 (Satisfies 10 and 11)

◼ So, our logic is

C' + S3'.S2' + S3'.S1' = 1 (used to generate 6)
Dr. Nilesh Patidar and Mr. Shiraz Husain 79
BCD Adder (Implementation)
1

1
1
1
C' + S3'.S2' + S3'.S1' = 1

0110

Dr. Nilesh Patidar and Mr. Shiraz Husain 80

Thank You

Dr. Nilesh Patidar and Mr. Shiraz Husain 81