SBC-PC-assembly-guidelines
SBC-PC-assembly-guidelines
Manufacturability Guidelines
For
Printed Circuit Board
Assemblies
Design for Manufacturability Guidelines
Revision History
REVISION
REV DESCRIPTION ORIGINATOR DATE
A Initial Release Tom Tindale 03/12/02
Table of Contents
Revision History.................................................................................................................................................... 2
1 References ......................................................................................................................................................... 6
2 Workmanship Standards ................................................................................................................................. 6
3 Hierarchy of Documents .................................................................................................................................. 6
4 Documentation Requirements .......................................................................................................................... 7
4.1 Format.......................................................................................................................................................... 7
4.2 Assembly Drawings..................................................................................................................................... 7
4.3 PCB Fabrication Drawings .......................................................................................................................... 7
4.4 Parts List/Manufacturing Bill of Material ................................................................................................... 7
4.5 Gerber Files ................................................................................................................................................. 7
4.6 CAD Data .................................................................................................................................................... 8
4.7 Schematics and Test Specifications............................................................................................................. 8
4.8 Engineering Change Orders (ECO’s, ECN’s etc.)....................................................................................... 8
5 PCB Layout and Design ................................................................................................................................... 8
5.1 References ................................................................................................................................................... 9
5.2 PCB Size...................................................................................................................................................... 9
5.3 PCB Thickness ............................................................................................................................................ 9
5.4 PCB Shape................................................................................................................................................... 9
5.5 Layer Count and Construction..................................................................................................................... 9
5.6 Copper Weights/Trace Widths/ Trace Spacings........................................................................................ 10
5.7 Drill ............................................................................................................................................................ 11
5.7.1 Locating References .......................................................................................................................... 11
5.7.2 Aspect Ratio ...................................................................................................................................... 11
5.7.3 Hole Tolerancing ............................................................................................................................... 11
5.7.4 Annular Ring ..................................................................................................................................... 12
5.7.5 Pad Sizing .......................................................................................................................................... 12
5.7.6 Standard Drill Sizes ........................................................................................................................... 13
5.8 Soldermask ................................................................................................................................................ 14
5.8.1 Types ................................................................................................................................................. 14
5.8.2 Soldermask Clearances ...................................................................................................................... 14
5.8.3 Soldermask Dams .............................................................................................................................. 15
5.8.4 Via Masking ...................................................................................................................................... 15
5.9 Surface Finishes......................................................................................................................................... 16
5.10 Silk-screened Legends............................................................................................................................... 16
5.11 Panelization ............................................................................................................................................... 16
5.11.1 Size and Shape................................................................................................................................... 17
5.11.2 Array Design...................................................................................................................................... 17
5.11.3 Retention Methods............................................................................................................................. 17
5.11.4 X-outs ................................................................................................................................................ 18
6 Surface Mount Assembly ............................................................................................................................... 19
6.1 PCB Size/ Shape........................................................................................................................................ 19
6.2 Bow and Twist........................................................................................................................................... 20
6.3 Board/Panel Clearances ............................................................................................................................. 20
6.4 SMT Panelization guidelines..................................................................................................................... 21
6.4.1 Breakaway rails ................................................................................................................................. 21
6.4.2 Retention Method .............................................................................................................................. 21
6.5 Fiducials .................................................................................................................................................... 21
6.5.1 Definition........................................................................................................................................... 21
6.5.2 Global/Panel Fiducials....................................................................................................................... 21
6.5.3 Block Fiducials .................................................................................................................................. 21
6.5.4 Local Fiducials................................................................................................................................... 22
Introduction
The purpose of this document is to provide our customers with a set of guidelines that will allow them to design
products that are both manufacturable and testable. Assemblies that are designed for manufacturability and
testability will be easier (and faster) to produce, require less rework/repair, and generate less scrap. All of which
will result in a more cost effective product for our customers. These guidelines are based on industry standard
specifications, with the exception of those that pertain directly to equipment used at South Bay Circuits, Inc. Refer
to Appendix A “South Bay Circuits, Site Capability Matrix”, for specific capabilities within the facility.
Please note: For maximum impact, DFM reviews must be accomplished during the design stage, when changes are
easy and cost effective.
1 References
2 Workmanship Standards
1). All Electronic and Electro-Mechanical assemblies will conform to IPC-A-610, Acceptability of Electronic
Assemblies, Class 2. for Dedicated Service Electronic Products, unless otherwise specified.
2). Dedicated Service Electronic Products includes: “communications equipment, sophisticated business machines,
and instruments where high performance and extended life is required, and for which uninterrupted service is
desired but not critical. Typically, the end-use environment would not cause failures.”
3). Exceptions to Classification 2 level of assembly require management approval and will require a different
response to an RFQ (Request for Quotation).
3 Hierarchy of Documents
In the event of conflicting requirements between applicable documents, the documents will take precedence in the
following order:
1). The Purchase Order - Highest Priority
2). Applicable assembly and detail drawings including BOM Notes and Specifications
3). The customer standards manual if specified.
4). IPC-A-610, Acceptability of Electronic Assemblies guidelines
4 Documentation Requirements
4.1 Format
All documentation must be 1:1 copies of the original. Size “C” reductions to Size “A”, and faxes are not acceptable
for quotation, or the planning/programming phase of the project. Electronic files over 2 megabytes should be
transferred to SBC via the FTP site. Electronic files are preferred in all cases.
Centroid Data may be used in lieu of CAD data, provided the following information is included:
1). Reference Designator
2). Package Description (0805, SOIC16, SOT-23, etc.)
3). Part Number
4). X ,Y Data (SMT centroids, PTH pin 1 location)
5). Theta Rotation (see Detail A below)
6). Top or Bottom Identification
Files may be provided on 3.5” floppy, CD ROM, or transferred via e-mail or South Bay Circuits, Inc.’s FTP server.
Detail A
Internal, external signal and ground layers should be designed so that every square inch of the layer has
approximately the same percentage of retained copper. This will enable the fabricator to hold tighter tolerances on
internal dielectrics and can help keep warpage to a minimum. This can be accomplished by adding non-functional
pads and traces to the design. Often, non-standard constructions are chosen and are not necessary for meeting final
product performance. This can add considerably to the board cost and diminish quality due to dimensional
instability. Non standard designs should be reviewed with the fabricator for potential cost saving options.
Internal and external layers should have all copper relieved a minimum of .050” from board edges to accommodate
panelization requirements.
Layer 2 - Power
Layer 3 - Signal
Layer 4 - Signal
Centerline
Layer 5 - Signal
Layer 6 - Signal
Layer 7 - Ground
Layer 8 - Signal
5.6.1 Inner Layers – Internal layers should be designed with ½ oz copper foil, where current handling capacity
permits. Where higher copper weights are required, 1oz is preferred over 2 oz. (2 oz copper can add as much
as 20% to material costs).
5.6.2 Outer Layers - External layers are more effectively produced on ½ oz copper. The following guidelines
should be used when choosing external layer copper.
5.7 Drill
- Plated through holes are normally drilled 4-6 mils over the nominal finished hole size. Copper and
solder plating generally reduce the hole diameter by approximately 3-5 mils.
- Plated holes over .100” located at the edges of the board should have large outer layer pads to
prevent them from plating too fast. Typically a pad .200” larger than the hole will help
FHS – nominal finished hole size; A/R – finished annular ring requirement (.002” typical)
Smaller pad sizes may be possible, but can result in reduced producibility for the fabricator.
5.8 Soldermask
5.8.1 Types
C D
A
B
COPPER PAD
COPPER TRACE
Dams ARE achievable on ALL fine pitch devices down to .0197” pitch.
Example: .0197” pitch - .011” pad = .0087” space between pads - .005” (.0025” soldermask relief on either side) =
.0037” solder mask dam.
1). Covered vias – soldermask is allowed to encroach on via pad. The mask relief is slightly larger than the
via hole.
2). Flooded vias – Soldermask is allowed to completely cover the pad, and flow into the via hole. A
meniscus may or may not be present after cure.
3). Plugged vias – Same mask relief as Covered via, but with a secondary plugging process. Can fill up to
2/3 of the barrel. Should be used where vacuum draw is needed for in-circuit test. To prevent bridging or
thieving, covered or flooded vias may be used.
Constraints:
1). Can only be accomplished with vias .018” (finished hole size) or less.
2). To avoid entrapped contaminants, boards should never be plugged from both sides.
Other considerations:
- Legend should be clipped from all pad surfaces. Do not rely on the PCB fabricator to fix this.
- Component polarity markings should be outside the body when possible to allow inspection.
- Legend over covered or plugged vias should be avoided underneath components. The build up of
material can effect component coplanarity.
5.11 Panelization
Panelization is required when one or more of the following conditions exist:
- The PCB shape does not have parallel edges along the 2 longest sides for conveyor transport. (See
section 6.1 for detail)
- The PCB does not have sufficient clearance between components and the edge of the board. (See
section 6.3 for detail)
- The size of the PCB does not meet the minimum requirement for the assembly equipment (See
section 5.2 for detail)
- Facilitate processing and handling of higher volume assemblies.
In most cases, SBC receives one-up data from our customers, and designs the panels in house, to ensure compliance
with assembly equipment requirements. In the case of a customer supplied panel design, SBC requests to review
and approve, prior to PCB fabrication. Breakaway rails may contain holes ≥ .250”, plating marks, clamp marks, etc,
as long as fiducial and hole keep out areas are maintained.
1). Array size should not cause overall panel design to approach maximum board handling limits.
3). Keep array numbers comparable with average lot requirements. If average lot size is 24, an 8 up panel will work
better than a 10 up configuration.
4). Unused material in the fabricator’s master panel will increase board cost.
5). Assemblies with overhanging components must be panelized with sufficient space between boards.
0.015”
5.11.3.2 Tab/Routing
The routed slot and tab pattern is widely used for panel construction and break- away tab extensions.
Routing is more precise than scoring, and edge surfaces are smooth, but the break-away “tab” points will
require consideration. Tabs can be cut and ground flush with the board edge or pre-drilled in a pattern. The
drilled pattern furnishes a low stress break point on the “tab”. If the hole pattern is recessed within the board
edge, secondary sanding or grinding can be bypassed. However drilled tabs are inherently less stable than
solid tabs, and careful consideration should be given to the array size and area available per board to locate
the tabs. Solid tabs due however require a secondary sanding or grinding processes that increases the labor
content of the assembly. Typical residual material is .020”-.040”. Sanding is not necessary if there are no
clearance issues. The below diagram is for .062” thick boards only. Please consult South Bay Circuits, Inc.
Engineering for recommendations on other fab thickness breakaways.
0.040" (1.0mm)DIA
3 places
PCB Edge 0.060" (1.5mm) centers
.050" (1.27mm)
.025"(.63mm)
.200" (5.08mm)
0.040" (1.0mm)DIA
6 places
0.060" (1.5mm) centers
PCB Edge
.050" (1.27mm)
TYP 4 places
.025"(.63mm)
TYP 2 places
.200" (5.08mm)
PCB Edge
5.11.4 X-outs
X-outs are individual boards in a panel array that fail electrical test at the board fabricator. While not allowing x-
outs will raise fab costs slightly, the impact to assembly is far greater. Panels with X-outs require special marking
so that the placement equipment will skip them during the placement cycle. In some cases allowing x-outs is
acceptable, with prior SBC Engineering authorization. Contact SBC engineering for further information regarding
the use of X-outs.
1). Minimum PCB size – With the use of panelization, there really is no minimum board size constraint. Smaller
boards can be panelized into a useable size array. The smallest array or individual board that can be handled is
4” X 4”
2). Maximum PCB size - Varies by line and facility. Please see Appendix “A” for details.
6.5 Fiducials
6.5.1 Definition
A Fiducial Mark is a printed artwork feature which is created in the same process as the circuit artwork. The fiducial
and a circuit pattern artwork must be etched in the same fabrication step. Fiducial alignment is used to compensate
for X, Y, and theta offsets in the position of the circuit pattern relative to the expected position. The fiducial
alignment system is an opto-electronic system which performs geometric measurements of fiducial marks on the
PCB in order to calculate the deviations from their expected positions. The system needs minimally two fiducials
per board, or panel. For optimum correction, they should be diagonally opposed and as far apart as possible on the
circuit or panel.
4). Material: The fiducial mark may be bare copper, gold, bare
copper protected by a clear anti-oxidant, nickel or tin plated, or
solder coated (HASL). The preferred thickness of plating or
solder coating it 0.0002” to 0.0004” (0.0005 to 0.0010mm).
Solder coating should never exceed 0.001” (0.025mm). If solder
mask is used, it should never cover the fiducial mark or the clearance area. It should be noted that oxidation of a
fiducial mark’s surface may degrade its readability.
5). Flatness: The flatness of the surface of the fiducial mark should be within 0.0006” (0.015mm).
6). Edge Clearance: The fiducial shall be located no closer to the PCB edge than the sum of 0.200” (5mm)
(SMEMA Standard Transport Clearance) and the minimum fiducial clearance required.
7). Contrast: Best performance is achieved when high contrast is present between the fiducial mark and the PCB
base material.
1). Single Sided Assembly - All SMT and PTH components located on the same side of the board.
2). Double Sided Assembly – All SMT active devices and all PTH devices located on the topside, only
SMT passives on the bottomside.
3). Double Sided Reflow – All SMT devices reflowed, and all PTH devices hand soldered.
4). Mixed Double Sided Assembly – SMT active devices and PTH devices located on both the top and
bottomside of the assembly. This will require hand soldering and/or wave solder fixturing.
- No discretes or passives larger than an 1810 size package. This includes C size or large
tantalum capacitors.
- No active components larger than 16 pin SOIC’s
- See section 10 for proper wave solder component orientation guidelines.
- Orient all polarity marking the same direction to facilitate identification of reversed
components
- Keep all placement angles at 0/90/180/270
6.7 Component
Spacing
Minimum
component spacing
specifications exist
to ensure that
assemblies will be
manufacturable
within an automated
SMT process.
Minimum spacing
requirements also
ensure that solder
joints can be 0.020”
( 0.5mm)
visually inspected,
and if necessary,
reworked or
repaired.
1). Soldermask dams are achievable down to .0197” pitch. Example - .0197” pitch - .011” pad width -
.005” soldermask relief (.0025 each side) = .0037 soldermask dam.
2) . Excessive joint length will not improve joint integrity, but will starve the solder joint by allowing
solder to cover the pad and flow away from the joint.
BGA’s are by far a preferable package to high lead count, ultra fine pitch devices, if the following
guidelines are followed with regard to pad geometry and escape routing.
For either pad design, the goal is to have the pad diameter equal to that on the package.
The above drawing represents a comparison of PBGA solder joints with soldermask defined and conventional non
soldermask defined pads. Note the greater solder volume and greater effective joint diameter for the non soldermask
defined pad to achieve the same stand-off height.
The following diagram is an example of a 1.27mm pitch PBGA containing a 23 mil pad. In this figure, the via, via
pad, and via soldermask clearance shown are recommended, but some variation is permissible. It is recommended
that the width of the trace attached should not be much greater than the 8 mils shown. A trace much wider, will
cause the pad to begin to resemble a mixture between NSMD and SMD. Also, a fillet should be present where the
trace joins the solder pad, and no more than one trace should be joined to any NSMD pad.
23 mil Soldermask
8 mil trace width Opening Diameter
23 mil pad
4 mil soldermask
diameter
overlap
4 mil Soldermask to
35.4 mils pad clearance
31 mil Solder
Pad Diameter
31 mil Soldermask
Opening
= Soldermask over laminate = Soldermask over copper = Solderable Surface = Bare Laminate
6.9 Vias
Size of the via holes should be selected based upon the PCB thickness vs. hole diameter or aspect ratio limits as
defined by the PCB fabricator. Specific via lands and holes can also be accessed for automatic in-circuit test (ICT).
Care must be exercised in the initial board layout to ensure that the insertion hole locations and the board locating
references are only “one tolerance” apart. If this consideration is not met, tolerance build -up during insertion will
reduce insertion reliability. The “one tolerance” requirement can easily be accomplished by establishing X-Axis and
Y-Axis dimensional reference lines through the centerlines of the locating references and using these pre-drilled
holes to locate the board for insertion hole drilling.
Recommended Dimensioning
Location &
Reference
Holes Dia. +/-
0.001” (3 Plcs.)
X1 & Tol.
Y1 & Tol.
X2 & Tol.
While some hole diameters may seem somewhat large in size, they take into account typical production floor
conditions. They deal with nominal dimensions plus the tolerances of all elements of the insertion system regardless
of type. It can be said that components can be inserted into smaller holes. It is difficult to accomplish it in a
production environment. Taking this into account, the hole sizes established in these guidelines can generally be
used without special considerations and with excellent results for production yield.
Clean Lead
Clean
0.300” (7.62mm)
1.300” (33.02mm)
Insertion
For Axial Lead Insertion machines with rotary tables, the maximum machine tolerances for the head, X - Y table,
rotary table and workboard holder is a true position accuracy of 0.005” (0.12mm). This value requires a starting
hole diameter of 0.010” (0.25mm) larger than the lead diameter being inserted. The manufacturing tolerance of the
PCB insertion hole pattern must be added top this hole diameter. The formula for determining hole diameter is:
Minimum Hole Diameter = Lead Diameter + 0.010” (0.25mm) + Hole Location Tolerance
The formula normally produces insertion reliability of 99.9 percent (0.999). Reduced clearance from wire diameter
to hole diameter to as low as 0.005” (0.13mm), may be used with small, high accuracy boards and still maintain
reasonable successful insertion. The insertion reliability will be reduced.
As a general rule, the minimum uninsertable area in the vicinity of any reference hole is approximately 0.5”
(12.7mm) radius from the edge of the workboard holder which supports the locating pin. Edge locating and support
methods usually require 0.5” (12.7mm) along the edge guides. With the use of inserts, these requirements can be
reduced. See the figure below.
Clinch Length
o Clinch Length
o
90 Clinch 45 Clinch
The Automatic DIP Insertion Machines are capable of processing a combination of two of the following devices:
3). 2 and 4 lead DIP devices with 0.300” (7.62mm) lead span
The Automatic DIP Insertion Machines can also be tooled to insert DIP sockets, with exception to 2 and 4 leaded
devices, which meet the specification shown in Appendix 6.6 and which are loaded in carrier sticks as shown in
Optional tooling, permits longer devices to be automatically processed by Automatic DIP Insertion Machines, but
unless otherwise specified herein all dimensions, clearances, and references shown apply to the devices listed in the
General Section.
The guidelines stated herein will provide optimum reliability in the production environment. As stated previously,
more generous clearances will improve insertion reliability; pushing dimensions to the lower limits will reduce
insertion reliability. Other configurations and dimensions are often possible. Consult your Manufacturing Engineer
for any deviations.
The minimum component lead hole size required for reliable DIP component insertion is a function of:
The accumulated tolerances of the insertion tooling, Positioning System and the design of the Workboard Holder
provides a positioning accuracy of 0.005” (0.12mm), relative to true position, for a machine that is equipped with a
standard, rotary positioning system. In order to determine the minimum acceptable lead hole diameter, this
positioning accuracy dictates a starting diameter of 0.010” (0.25mm) larger than the Effective Lead Diameter of the
component to be inserted. To this must be added the manufacturing tolerance of the PCB hole pattern (Hole
Location Tolerance).
1). This is expressed as: Effective Lead Diameter + Hole Location Tolerance + 0.010”
2). Effective Lead Diameter is a function of the tooling lead slot [0.022” (0.056mm)] and component lead thickness
where: Effective Lead Diameter = 0.0222lead thickness2
3). The minimum component hole diameter should not be less than 0.037” (0.94mm), except as described in
“Component Lead Considerations” for pointed or tapered leads, nor should the maximum hole diameter exceed
0.041” (1.04mm).
4). Whenever insertion into PCB holes smaller than those specified herein, the Manufacturing Engineer should be
consulted.
enhance insertion reliability and can effectively reduce the required hole diameter by 0.003” (0.08mm) to 0.006”
(0.15mm) depending upon the degree of taper, length of taper, lead material, and PCB hole plating.
The outward clinch pattern is not recommended for DIP socket component insertion.
11 Wave Solder
General – Designing for Wave Solder is a critical step in producing a lower cost assembly. Poorly designed panels
will result in higher defect rates and/or increased labor costs due to increased hand soldering and wave solder
fixturing.
11.2 Clearances
Panels that meet the following criteria may be wave soldered without the use of additional tooling:
1). The PCB/Panel must be rectangular, with 2 parallel sides along the longer axis
2). These parallel sides must have a minimum of .080” (2mm) clearance to any component leads or bodies.
3). Under board clearance for leads or previously mounted SMT components must not exceed .100”
4). PCB’s/Panels exceeding 6” in width, must have additional keep out areas of at least 0.3” (7.6mm) along the
front and rear edges to accommodate PCB stiffeners
PCB n
o
f
D Tr
11.3.1 DIP/Connectors
11.4.2 Vias
All non test point vias should be masked to minimize solder migration to the topside of the board. Spacing
guidelines should be the same as for SMT.
12 Materials
Whenever possible, SMT devices should be selected from standard configurations. The standard components will
be available from multiple sources and will usually be compatible will all assembly processes. For those devices
developed to meet specific applications, standard packaging is often available. Select a package type that will be
similar in materials and plating of standard device types when possible.
Illustrations of component dimensions beginning in each component section of IPC-SM-782 are accompanied by
table of figures for each of the different part numbers, as taken from EIA- PDP-100, JEDEC-95 and other world
wide component standards. EIA-PDP-100 is a catalogue listing of outline drawings illustrating the dimensions of
supplier registered passive components; JEDEC-95 is the outlining document for solid state products. At times, the
component tolerances or component gauge requirements do not necessarily reflect the exact tolerance on a
manufacturers data sheet. Usually, this occurs when industry component specification ranges are so broad that they
defy good surface mount design principles.
Refer to IPC-D-275, Design Standard for Rigid Printed Board and Rigid Printed Board Assemblies, Section 8.2
Material Selection.
12.2 Terminations
Whenever possible standard tin/lead alloy terminations should be specified. Other alloys containing silver, gold, or
palladium may require special processing, increasing assembly costs.
12.3 BGA’s
Whenever possible Overmolded plastic BGA’s should be specified as opposed to the Encapsulated type.
Encapsulated BGA’s allow more of the BT substrate to be exposed, resulting in increased flex during heating
cycles. While normal reflow is possible, rework or replacement of these parts becomes more difficult.
13 Appendix Listing