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DRC

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42 views

DRC

Uploaded by

Sukirtha s
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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In VLSI (Very Large Scale Integration), DRC (Design Rule Check) is a crucial step in the verification

process. It ensures that the physical layout of a chip adheres to the manufacturing process's design
rules, which are specified by the semiconductor foundry.

What is DRC?

DRC (Design Rule Check) is the process of verifying that the physical layout of a chip complies with
the geometrical, spacing, and connectivity constraints imposed by the semiconductor manufacturing
process. These rules ensure the layout can be fabricated correctly and will function as intended.

Why is DRC Important?

1. Manufacturability

o Ensures the layout can be fabricated using the target process technology.

2. Yield Improvement

o Prevents issues like shorts, opens, and reliability problems that can reduce chip yield.

3. Process Compatibility

o Guarantees that the design adheres to the specific constraints of the fabrication
process node (e.g., 28nm, 7nm).

4. Cost Savings

o Catching errors during the design phase avoids costly rework or redesigns after
fabrication.

Common Design Rules Verified in DRC

DRC checks are based on the foundry-provided Design Rule Manual (DRM), and the rules vary with
the process technology. Common rules include:

1. Width Rules

 Minimum width for metal lines, polysilicon, or diffusion layers to ensure they are
manufacturable.

2. Spacing Rules

 Minimum spacing between adjacent objects (e.g., metal lines, vias, or transistors) to avoid
shorts or unintended interactions.

3. Enclosure Rules

 Minimum overlap or enclosure of one layer by another (e.g., via by a metal layer).

4. Alignment Rules
 Proper alignment of layers, such as polysilicon over diffusion, to ensure correct transistor
functioning.

5. Density Rules

 Ensures a uniform density of metal, polysilicon, or other layers to avoid issues like chemical-
mechanical polishing (CMP) problems.

6. Antenna Rules

 Checks for antenna effects that could damage gates during fabrication.

7. Corner or Edge Rules

 Verifies acute angles or edge overlaps to prevent weak spots in the design.

8. Contact and Via Rules

 Ensures vias and contacts are placed correctly and are of sufficient size for reliable
connections.

DRC Process Workflow

1. Input Preparation

 The physical layout is finalized and stored in a format like GDSII or OASIS.

 Foundry provides a DRC rule deck tailored for the specific process technology.

2. DRC Run

 A DRC tool analyzes the layout against the rule deck.

 The tool checks each layer of the layout for rule violations.

3. Error Reporting

 DRC generates a detailed error report, highlighting the location and type of violations.

4. Debugging

 Designers inspect and fix the violations in the layout.

5. Iterative Verification

 After fixing errors, DRC is rerun to ensure all violations are resolved.

Common Tools for DRC

1. Calibre by Mentor Graphics (Siemens EDA)

2. Assura by Cadence

3. IC Validator by Synopsys

4. DRC+ by Mentor Graphics (for advanced nodes and pattern matching)


Challenges in DRC

1. Increasing Complexity

o Advanced nodes (e.g., 7nm, 5nm) have more stringent and complex design rules.

2. Runtime

o Checking large designs with billions of transistors can be time-consuming.

3. False Positives

o The tool may flag issues that are not true violations, requiring manual review.

4. Debugging

o Fixing violations can be tedious, especially when multiple iterations are needed.

Best Practices for Successful DRC

1. Run DRC Early and Often

o Perform incremental checks during layout creation to catch errors early.

2. Automate Fixes

o Use layout tools that can automatically fix common violations.

3. Understand the Rules

o Familiarize yourself with the design rule manual to avoid unnecessary violations.

4. Hierarchical DRC

o Divide the design into smaller blocks and check them individually to save time.

5. Collaborate with Foundry

o Clarify ambiguous rules with the foundry to ensure compliance.

Conclusion

DRC is an essential step in the VLSI design flow to ensure the physical layout adheres to the
manufacturing process's constraints. It minimizes risks, improves yield, and ensures a
manufacturable and reliable chip design.

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