Scribd
Upload
24 views

VLSI Lab Questions

VLSI Lab Questions for practice and for reference

Uploaded by

Thirandasu
Copyright
© © All Rights Reserved
Available Formats
Download as ODT, PDF, TXT or read online on Scribd
24 views

VLSI Lab Questions

VLSI Lab Questions for practice and for reference

Uploaded by

Thirandasu
Copyright
© © All Rights Reserved
Available Formats
Download as ODT, PDF, TXT or read online on Scribd
You are on page 1/ 3

1.a) Write a HDL code to verify all the combinations of 2:4 decoder.

b) Design 2 Input CMOS NAND gate and verify its Transient analysis.

2.a) Write a HDL code to simulate SR Flip flop.

b) Design and verify Transient analysis of CMOS Inverter.

3. a) Write a HDL code to simulate 8X1 MUX.

b) Design 4-bit pseudo logic All one’s Detector and verify using Cadence Virtuoso Tool.

4. Design CMOS NAND and NOR gates and Verify Transient analysis.

5. Design a CMOS inverter schematic and generate its Layout using cadence tools.

6. a) Verify 2 input CMOS NOR gate with Transient Analysis using cadence tool.

b) Write HDL Code for Full Adder using two Half Adders.

7. a) Verify CMOS NOR gate with Transient Analysis using cadence tool.

b) Write HDL Code for Behavioural model of Full Adder.

8.a) Design 8x1 MUX using Xilinx ISE tool.

b) Design and verify 2 input AND Gate using Cadence Virtuoso Tool.

9. a) Write a HDL code to simulate and verify 8x1 MUX using Behavioural style.

b) Design 4-bit pseudo logic Zero Detector and verify using Cadence Virtuoso Tool.

10.a) Write a HDL code to verify D FLIP FLOP using Xilinx XST tool.

b) Design and verify 2 input CMOS NAND gate using cadence virtuoso tool.

11. Write a HDL code to verify FULL Adder in 3 different styles

12. a) Write a HDL code to simulate all logic gates.

b) Design and verify Conventional D FLIP FLOP using cadence virtuoso tool.

13.a) Write a HDL code to verify all the combinations of 2:4 decoder.

b) Obtain Transient analysis of 2 input CMOS OR Gate using cadence virtuoso tool.

14.a) Write a HDL code to simulate Full adder using dataflow modelling style.

b) Design and verify D FLIP FLOP using cadence virtuoso tool.

15.a) Design and verify 2 Input CMOS NAND gate using Cadence Virtuoso Tool.

b) Write a HDL code to simulate 4-bit Binary Counter.


16.a) Write a HDL code to simulate D flip-flop.

b) Design CMOS Inverter and verify transient analysis using cadence virtuoso tool.

17. Design and verify 2 input CMOS XOR Gate using cadence virtuoso tool.

18.a) Write a HDL code to simulate all logic gates.

b) Design and verify CMOS 2 input NAND gate using cadence virtuoso tool.

19.a) Write a HDL code to simulate Full Adder in behavioural model style.

b) Design and verify 2 input CMOS NOR gate using cadence virtuoso tool.

20.a) Write a HDL code to simulate all logic gates.

b) Obtain Transient Analysis of CMOS Inverter using cadence virtuoso tool

21. a) Write a HDL code to simulate Full Adder in behavioural model style

b) Design and verify 2 Input CMOS NAND gate using cadence virtuoso tool.

22 a) Design 4-bit pseudo logic Zero Detector and verify using Cadence Virtuoso Tool.

b) Write a HDL code to simulate SR flip-flop.

23. a) Design 4-bit pseudo logic All one’s Detector and verify using Cadence Virtuoso Tool.

b) Write a HDL code to simulate 4-bit Binary counter.

24. a) Write a HDL code to simulate all logic gates.

b) Obtain Transient Analysis of CMOS Inverter using cadence virtuoso tool.

25. a) Design CMOS Inverter and verify transient analysis using cadence virtuoso tool.

b) Write a HDL code to simulate and verify 8x1 MUX using Behavioural style.

26.Design a CMOS inverter schematic and generate its Layout using cadence tools.

27. Design and verify 2 input CMOS XOR Gate using cadence virtuoso tool.

28.a) Write a HDL code to simulate all logic gates.

b) Obtain Transient Analysis of CMOS Inverter using cadence virtuoso tool .

29. a) Design 4-bit pseudo logic All one’s Detector and verify using Cadence Virtuoso Tool.

b) Write a HDL code to simulate 4-bit Binary counter.

30. a) Write a HDL code to simulate Full Adder in behavioural model style

b) Design and verify 2 input CMOS NAND gate using cadence virtuoso tool.
31.a) Write a HDL code to simulate Full Adder in behavioural model style.

b) Design and verify 2 input CMOS NOR gate using cadence virtuoso tool.

32.a) Write a HDL code to simulate SR flip-flop and D flip-flop.

b) Design CMOS Inverter and verify transient analysis using cadence virtuoso tool.

You might also like