ĐỀ CƯƠNG ÔN TẬP THIẾT KẾ HỆ THỐNG SỐ

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity clk_div is

Port ( clk_100M: in std_logic;

rst : in std_logic;

clk_2s: out std_logic;

clk_5s: out std_logic;

clk_1s: out std_logic );

end clk_div;

architecture Behavioral of clk_div is

signal tmp1: std_logic:= '0';

signal count1s: integer range 0 to 49999999 := 0;

signal tmp2: std_logic:= '0';

signal count2s: integer range 0 to 99999998 := 0;

signal tmp5: std_logic:= '0';

signal count5s: integer range 0 to 249999995 := 0;

begin

clk1s: process (rst, clk_100M) is

begin

if rst = '0' then

tmp1 <= '0';

count1s <= 0;
 tmp2 <= '0';

count2s <= 0;

tmp5 <= '0';

count5s <= 0;

else

if rising_edge (clk_100M) then

if (count1s = 49999999) then

tmp1 <= not tmp1;

count1s <= 0;

else

count1s <= count1s + 1;

end if;

if (count2s = 99999998) then

tmp2 <= not tmp2;

count2s <= 0;

else

count2s <= count2s + 1;

end if;

if (count5s = 249999995) then

tmp5 <= not tmp5;

count5s <= 0;

else
 count5s <= count5s + 1;

end if;

end if;

end if;

end process;

clk_5s <= tmp5;

clk_2s <= tmp2;

clk_1s <= tmp1;

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Mach_giai_ma_led is

generic (

CLK_FREQ: integer := 100000000;

MUX_FREQ: integer := 100

);

Port (clk : in std_logic;

led_7seg_chuc, Led_7seg_dvi: in std_logic_vector(3 downto 0); --bcd

cat: out std_logic;

Led_7seg_out: out std_logic_vector(6 downto 0)

 );

end Mach_giai_ma_led;

architecture Behavioral of Mach_giai_ma_led is

signal decode_led: std_logic_vector(3 downto 0);

signal led_out: std_logic_vector(6 downto 0);

signal cat1: std_logic := '0';

signal cnt : integer range 0 to CLK_FREQ/MUX_FREQ:= 0;

begin

PROCESS(clk)

BEGIN

if rising_edge(clk) then

IF ( cnt = CLK_FREQ/MUX_FREQ) then

cat1 <= not cat1;

cnt <= 0;

else

cnt <= cnt +1;

END IF;

end if;

END PROCESS;

-- cat <= clk100s gọi từ chia tần

cat <= cat1;

process(cat1, led_7seg_chuc, Led_7seg_dvi)

begin

if(cat1 = '0') then decode_led <= Led_7seg_dvi;

else decode_led <= led_7seg_chuc;

end if;

end process;

Led_7seg_out <= not led_out;

Led_out <= "0000001" when decode_led = x"0" else

"1001111" when decode_led = x"1" else

"0010010" when decode_led = x"2" else

"0000110" when decode_led = x"3" else

"1001100" when decode_led = x"4" else

"0100100" when decode_led = x"5" else

"0100000" when decode_led = x"6" else

"0001111" when decode_led = x"7" else

"0000000" when decode_led = x"8" else

"0000100" when decode_led = x"9";

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity Adder_register is

generic (N: natural := 8);

Port ( rst : in STD_LOGIC;

clk : in STD_LOGIC;

Cout : out std_logic_vector(N-1 downto 0));

end Adder_register;

architecture Behavioral of Adder_register is

component adder1

port(

B: in std_logic_vector (N-1 downto 0);

Sum: out std_logic_vector (N-1 downto 0)

);

end component;

component register_adder

port ( rst : in std_logic;

clk: in std_logic;

enable: in std_logic;

Re_in: in std_logic_vector (N-1 downto 0) ;

Re_out: out std_logic_vector (N-1 downto 0)

);

end component;

component div10
port(clk100M : in std_logic;

clk1s : out std_logic);

end component;

signal Sum : std_logic_vector (N-1 downto 0) ;

signal Re_out : std_logic_vector (N-1 downto 0) ;

signal clk1s: std_logic;

begin

Cout <= Re_out;

u1: adder1

port map(

B => Re_out,

Sum => Sum

);

u2: register_adder

port map(

rst => rst,

clk => clk,

enable => clk1s,

Re_in => Sum,

Re_out => Re_out

);

u3: div10

port map(clk100M => clk, clk1s => clk1s);

end Behavioral;

library ieee;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_unsigned.all;

entity adder1 is

generic (N : natural := 8);

port (

B: in std_logic_vector (N-1 downto 0);

Sum: out std_logic_vector (N-1 downto 0)

);

end adder1;

architecture Behavioral of adder1 is

begin

process(B)

begin

if B = x"99" then

Sum <= x"00";

elsif B(3 downto 0) = "1001" then

Sum <= B + "00000111";

else Sum <= B + "00000001";

end if;

end process;
end Behavioral;

library ieee;

use IEEE.STD_LOGIC_1164.ALL;

entity register_adder is

generic (N : natural := 8);

port (

rst : in std_logic;

clk: in std_logic;

enable: in std_logic;

Re_in: in std_logic_vector(N-1 downto 0);

Re_out: out std_logic_vector (N-1 downto 0)

);

end register_adder;

architecture Behavioral of register_adder is

begin

process(clk, rst)

begin

if rst ='1' then Re_out <= (others=> '0');

elsif rising_edge(clk) and enable ='1' then

Re_out <= Re_in;

end if;
end process;

end Behavioral;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY div10 IS

PORT (clk100M: in STD_LOGIC;

clk1s: out STD_LOGIC);

END div10;

ARCHITECTURE behav OF div10 IS

SIGNAL cnt: INTEGER range 0 to 100000000:= 0;

signal clk1ss: std_logic:= '0';

BEGIN

PROCESS(clk100M)

BEGIN

if rising_edge(clk100M) then

IF ( cnt = 100000000/10) then

clk1ss <= '1';

cnt <= 0;
else

clk1ss <= '0';

cnt <= cnt +1;

END IF;

end if;

END PROCESS;

clk1s <= clk1ss;

END behav;

Yêu cầu:

1. Nắm vững cách thiết kế mạch tổ hợp, mạch dãy

2. Hiểu cách sử dụng process
3. Hiểu cách sử dụng các câu lệnh đồng thời
4. Hiểu cách thiết kế theo máy trạng thái
5. Hiểu cách reset hoạt động đồng bộ hay không đồng bộ.

Chú ý: các trường hợp yêu cầu hiển thị trên led 7 đoạn đều sử dụng pmod_ssd

Nội dung:

1. Thiết kế mạch cộng hai số 4 bit BCD hiển thị kết quả trên led 7 đoạn

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;

entity bai1 is
Port (a,b: in std_logic_vector(3 downto 0);
sum :out std_logic_vector(4 downto 0) );
end bai1;
architecture Behavioral of bai1 is
signal temp: std_logic_vector (4 downto 0);
begin
temp <= ('0'& a) + b;
process(temp)
begin
if temp >9 then sum <= temp + 6;
else sum <= temp;
end if;
end process;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;

entity tb_bai1 is
-- Port ( );
end tb_bai1;

architecture Behavioral of tb_bai1 is

signal a,b : std_logic_vector(3 downto 0);
signal sum : std_logic_vector(4 downto 0);
begin
UUT : entity work.bai1 port map (a => a, b => b, sum => sum);
tb1 : process
constant period: time := 20 ns;
begin
a <= "0000";
b <= "0111";

wait for period;

 a <= "0101";
b <= "0100";

wait for period;

a <= "0111";
b <= "1000";

wait for period;

a <= "1111";
b <= "0100";

wait for period;

a <= "1001";
b <= "1000";

wait for period;

a <= "1001";
b <= "1001";
-- Fail test
wait; -- indefinitely suspend process
end process;
end Behavioral;
2. Thiết kế mạch cộng trừ hai số nhị phân có đầu vào load và tín hiệu reset, kết
quả hiển thị trên led.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bai2 is
 Port ( A, B : in STD_LOGIC_VECTOR (7 downto 0);
Load, Reset : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR (7 downto 0);
Borrow : out STD_LOGIC);
end bai2;

architecture Behavioral of bai2 is

signal Temp : STD_LOGIC_VECTOR (8 downto 0);
begin
process(A, B, Load, Reset)
begin
if Reset = '1' then
Temp <= (others => '0');
elsif Load = '1' then
Temp <= ('0' & A) - ('0' & B);
else
Temp <= ('0' & A) + ('0' & B);
end if;
end process;

Sum <= Temp(7 downto 0);

Borrow <= Temp(8);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_bai2 is
end tb_bai2;

architecture Behavioral of tb_bai2 is

signal A, B : STD_LOGIC_VECTOR (7 downto 0);
signal Load, Reset : STD_LOGIC;
signal Sum : STD_LOGIC_VECTOR (7 downto 0);
signal Borrow : STD_LOGIC;
 component bai2
Port ( A, B : in STD_LOGIC_VECTOR (7 downto 0);
Load, Reset : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR (7 downto 0);
Borrow : out STD_LOGIC);
end component;

begin
UUT: bai2
port map (A => A, B => B, Load => Load, Reset => Reset, Sum =>
Sum, Borrow => Borrow);

process
begin
A <= "11011010"; -- Example input A
B <= "00110101"; -- Example input B
Load <= '1'; -- Load inputs
Reset <='1';
wait for 10 ns; -- Allow time for computation
A <= "11001111"; -- Example input A
B <= "11110101"; -- Example input B
Load <= '1'; -- Load inputs
Reset <='0';
wait for 10 ns; -- Allow time for A
A <= "11000000"; -- Example input A
B <= "00110101"; -- Example input B
Load <= '0'; -- Load inputs
Reset <='0';
wait for 10 ns; -- Allow time for computation
A <= "11111111"; -- Example input A
B <= "10110101"; -- Example input B
Load <= '0'; -- Load inputs
Reset <='0';
wait for 10 ns; -- Allow time for computation
 wait;

end process;
end Behavioral;

3. Thiết kế mạch chuyển đổi mã nhị phân 4 bit sang mã Gray 4 bit, kết quả
hiển thị trên led 7 đoạn
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bai3 is
Port ( BinaryInput : in STD_LOGIC_VECTOR (3 downto 0);
GrayOutput : out STD_LOGIC_VECTOR (3 downto 0));
end bai3;

architecture Behavioral of bai3 is

begin
process(BinaryInput)
begin
GrayOutput(3) <= BinaryInput(3);
GrayOutput(2) <= BinaryInput(3) XOR BinaryInput(2);
GrayOutput(1) <= BinaryInput(2) XOR BinaryInput(1);
GrayOutput(0) <= BinaryInput(1) XOR BinaryInput(0);
end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_bai3 is
end tb_bai3;

architecture Behavioral of tb_bai3 is

signal BinaryInput : STD_LOGIC_VECTOR (3 downto 0);
signal GrayOutput : STD_LOGIC_VECTOR (3 downto 0);
 component bai3
Port ( BinaryInput : in STD_LOGIC_VECTOR (3 downto 0);
GrayOutput : out STD_LOGIC_VECTOR (3 downto 0));
end component;

begin
UUT: bai3
port map (BinaryInput => BinaryInput, GrayOutput => GrayOutput);

process
begin
BinaryInput <= "1101"; -- Example input (binary)
wait for 10 ns; -- Allow time for computation
BinaryInput <= "0010"; -- Example input (binary)
wait for 10 ns; -- Allow time for APPEND_MODE
BinaryInput <= "1111"; -- Example input (binary)
wait for 10 ns; -- Allow time for APPEND_MODE
BinaryInput <= "0001"; -- Example input (binary)
wait for 10 ns; -- Allow time for computation

wait;
end process;
end Behavioral;

4. Thiết kế mạch chuyển đổi từ mã Gray 4 bit sang mã nhị phân 4 bit, kết quả
hiển thị trên led 7 đoạn

library IEEE;
use IEEE.STD_LOGIC_1164.ALL, IEEE.numeric_std.all;

entity bai4 is
Port ( gray_value : in std_logic_vector (3 downto 0);
numeric_value: out unsigned (3 downto 0) );
end bai4;

architecture Behavioral of bai4 is

begin
--with gray_value select
--numeric_value <="0000" when "0000", "0001" when "0001",
--"0010" when "0011", "0011" when "0010",
--"0100" when "0110", "0101" when "0111",
--"0110" when "0101", "0111" when "0100",
--"1000" when "1100", "1001" when "1101",
--"1010" when "1111", "1011" when "1110",
--"1100" when "1010", "1101" when "1011",
--"1101" when "1001", "1111" when others;
numeric_value(3)<= gray_value(3);
numeric_value(2)<= gray_value(3) xor gray_value(2);
numeric_value(1)<= gray_value(3) xor gray_value(2) xor
gray_value(1);
numeric_value(0)<= gray_value(3) xor gray_value(2) xor
gray_value(1) xor gray_value(0);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL, IEEE.numeric_std.all;

entity tb_bai4 is
-- Port ( );
end tb_bai4;

architecture Behavioral of tb_bai4 is

component bai4
Port ( gray_value : in std_logic_vector (3 downto 0);
numeric_value: out unsigned (3 downto 0) );
end component;
 signal gray_value : std_logic_vector (3 downto 0);
signal numeric_value: unsigned (3 downto 0);
begin
uut: bai4
port map (gray_value =>gray_value ,
numeric_value =>numeric_value);
stim_process: process
begin
gray_value <= "0000"; wait for 10ns;
assert (numeric_value ="0000");
gray_value <= "0011"; wait for 10ns;
assert (numeric_value ="0010");
gray_value <= "0110"; wait for 10ns;
assert (numeric_value ="0100");
gray_value <= "0101"; wait for 10ns;
assert (numeric_value ="0110");
gray_value <= "1100"; wait for 10ns;
assert (numeric_value ="1000");
gray_value <= "1111"; wait for 10ns;
assert (numeric_value ="1010");
gray_value <= "1010"; wait for 10ns;
assert (numeric_value ="1100");
gray_value <= "1001"; wait for 10ns;
assert (numeric_value ="1101");

gray_value <= "0001"; wait for 10ns;

assert (numeric_value ="0001");
gray_value <= "0010"; wait for 10ns;
assert (numeric_value ="0011");
gray_value <= "0111"; wait for 10ns;
assert (numeric_value ="0101");
gray_value <= "0100"; wait for 10ns;
assert (numeric_value ="0111");
gray_value <= "1101"; wait for 10ns;
 assert (numeric_value ="1001");
gray_value <= "1110"; wait for 10ns;
assert (numeric_value ="1011");
gray_value <= "1011"; wait for 10ns;
assert (numeric_value ="1101");
gray_value <= "1000"; wait for 10ns;
assert (numeric_value ="1111");
wait;
end process;

end Behavioral;
5. Thiết kế khối nhân hai số 4 bit BCD hiển thị kết quả trên led 7 đoạn
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;

entity bai5 is
Port (
BCD1 : in STD_LOGIC_VECTOR (3 downto 0);
BCD2 : in STD_LOGIC_VECTOR (3 downto 0);
Result : out STD_LOGIC_VECTOR (7 downto 0)
);
end bai5;

architecture Behavioral of bai5 is

function BCD_to_Integer(bcd : STD_LOGIC_VECTOR(3 downto 0))

return integer is
variable decimal_value : integer := 0;
begin
case bcd is
when "0000" => decimal_value := 0;
when "0001" => decimal_value := 1;
 when "0010" => decimal_value := 2;
when "0011" => decimal_value := 3;
when "0100" => decimal_value := 4;
when "0101" => decimal_value := 5;
when "0110" => decimal_value := 6;
when "0111" => decimal_value := 7;
when "1000" => decimal_value := 8;
when "1001" => decimal_value := 9;
when others => decimal_value := 0;
end case;
return decimal_value;
end function;

function Integer_to_BCD(value : integer) return STD_LOGIC_VECTOR

is
variable temp : integer := value;
variable bcd : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
bcd(3 downto 0) := std_logic_vector(to_unsigned(temp mod 10, 4));
temp := temp / 10;
bcd(7 downto 4) := std_logic_vector(to_unsigned(temp mod 10, 4));
return bcd;
end function;

begin
process(BCD1, BCD2)
variable int1 : integer;
variable int2 : integer;
variable product : integer;
begin
int1 := BCD_to_Integer(BCD1);
int2 := BCD_to_Integer(BCD2);
product := int1 * int2;
Result <= Integer_to_BCD(product);
end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_bai5 is
end tb_bai5;

architecture behavior of tb_bai5 is

signal BCD1 : STD_LOGIC_VECTOR (3 downto 0);
signal BCD2 : STD_LOGIC_VECTOR (3 downto 0);
signal Result : STD_LOGIC_VECTOR (7 downto 0);

component bai5
Port (
BCD1 : in STD_LOGIC_VECTOR (3 downto 0);
BCD2 : in STD_LOGIC_VECTOR (3 downto 0);
Result : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;

begin
uut: bai5
Port Map (
BCD1 => BCD1,
BCD2 => BCD2,
Result => Result
);

process
begin
-- Test case 1: 4 * 3 = 12
BCD1 <= "0100"; -- 4 in BCD
BCD2 <= "0011"; -- 3 in BCD
 wait for 10 ns;

-- Test case 2: 7 * 5 = 35
BCD1 <= "0111"; -- 7 in BCD
BCD2 <= "0101"; -- 5 in BCD
wait for 10 ns;

-- Add more test cases as needed

wait;
end process;
end behavior;

6. Thiết kế khối chia hai số nhị phân 4 bit, kết quả phần thương số hiển thị trên
led RGB, và phần dư hiển thị trên led thường.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bai6 is
Port (
dividend : in STD_LOGIC_VECTOR(3 downto 0);
divisor : in STD_LOGIC_VECTOR(3 downto 0);
quotient : out STD_LOGIC_VECTOR(3 downto 0); -- thương
remainder : out STD_LOGIC_VECTOR(3 downto 0)
);
end bai6;

architecture Behavioral of bai6 is

begin
process(dividend, divisor)
variable temp_dividend : STD_LOGIC_VECTOR(7 downto 0);
variable temp_divisor : STD_LOGIC_VECTOR(7 downto 0);
variable temp_quotient : STD_LOGIC_VECTOR(3 downto 0);
 variable temp_remainder: STD_LOGIC_VECTOR(3 downto 0);
begin
if divisor /= "0000" then
-- Initialize variables
temp_dividend := (others => '0');
temp_divisor := (others => '0');
temp_quotient := (others => '0');
temp_remainder := (others => '0');

-- Copy dividend and divisor

temp_dividend(7 downto 4) := dividend;
temp_divisor(3 downto 0) := divisor;

-- Division algorithm
for i in 0 to 3 loop
temp_remainder := temp_remainder(2 downto 0) &
temp_dividend(7);
temp_dividend := temp_dividend(6 downto 0) & '0';

if temp_remainder >= temp_divisor(3 downto 0) then

temp_remainder := temp_remainder - temp_divisor(3 downto
0);
temp_quotient := temp_quotient(2 downto 0) & '1';
else
temp_quotient := temp_quotient(2 downto 0) & '0';
end if;
end loop;

quotient <= temp_quotient;

remainder <= temp_remainder;
else
quotient <= (others => 'X'); -- Undefined result if divisor is zero
remainder <= (others => 'X'); -- Undefined result if divisor is zero
end if;
end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_bai6 is
end tb_bai6;

architecture behavior of tb_bai6 is

signal dividend : STD_LOGIC_VECTOR(3 downto 0);
signal divisor : STD_LOGIC_VECTOR(3 downto 0);
signal quotient : STD_LOGIC_VECTOR(3 downto 0);
signal remainder : STD_LOGIC_VECTOR(3 downto 0);

component bai6
Port (
dividend : in STD_LOGIC_VECTOR(3 downto 0);
divisor : in STD_LOGIC_VECTOR(3 downto 0);
quotient : out STD_LOGIC_VECTOR(3 downto 0);
remainder : out STD_LOGIC_VECTOR(3 downto 0)
);
end component;

begin
uut: bai6
Port Map (
dividend => dividend,
divisor => divisor,
quotient => quotient,
remainder => remainder
);

process
begin
 -- Test case 1: 10 / 3
dividend <= "1010"; -- 10 in binary
divisor <= "0011"; -- 3 in binary
wait for 10 ns;

-- Test case 2: 15 / 2
dividend <= "1111"; -- 15 in binary
divisor <= "0010"; -- 2 in binary
wait for 10 ns;

-- Test case 3: 8 / 4
dividend <= "1000"; -- 8 in binary
divisor <= "0100"; -- 4 in binary
wait for 10 ns;

-- Add more test cases as needed

wait;
end process;
end behavior;
7. Thiết kế mạch đếm tiến/lùi có reset đồng bộ/không đồng bộ và tín hiệu load
đồng bộ… theo yêu cầu.
--Dem + Giai ma tu 4 bit sang 7 bit led 7 ðo?n
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
entity BCDto7seg is
Port (
clk: in std_logic;
reset: in std_logic;
cat: in std_logic;
led7seg: out std_logic_vector(6 downto 0)
);
end BCDto7seg;
architecture Behavioral of BCDto7seg is
signal led_out: std_logic_vector(6 downto 0);
signal decode_led: std_logic_vector( 3 downto 0);
signal temp_chuc: std_logic_vector (3 downto 0):=(others=>'0');
signal temp_donvi: std_logic_vector( 3 downto 0):=(others=>'0');
begin
process(clk,reset)
begin
if reset='0' then
temp_donvi<=(others=>'0');
temp_chuc<=(others=>'0');
elsif rising_edge(clk) then
if temp_donvi="0000" and temp_chuc= "0011" then
temp_donvi<=(others=>'0');
temp_chuc<=(others=>'0');

elsif temp_donvi="1001" then

temp_donvi<= (others=>'0');
temp_chuc <= temp_chuc +1;
else
temp_donvi <= temp_donvi +1;
end if;
-- if(temp_chuc= "1001") then
-- temp_chuc<=(others=>'0');
-- end if;
end if;
end process;
process(cat,temp_chuc,temp_donvi)
begin
if(cat='0') then
decode_led<= temp_donvi;
else
decode_led<= temp_chuc;
end if;
end process;
led7seg<= not led_out;
led_out<="0000001" when decode_led = x"0" else
"1001111" when decode_led = x"1" else
"0010010" when decode_led = x"2" else
"0000110" when decode_led = x"3" else
"1001100" when decode_led = x"4" else
"0100100" when decode_led = x"5" else
"0100000" when decode_led = x"6" else
"0001111" when decode_led = x"7" else
"0000000" when decode_led = x"8" else
"0000100" when decode_led = x"9";
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity count is
Port (
clk100M: in std_logic;
reset: in std_logic;
clk1s: out std_logic;
cat1: out std_logic;
led_7segment: out std_logic_vector(6 downto 0)
);
end count;
architecture Behavioral of count is
component frequency is
generic(
N: natural:=1e8
);
port(
clk: in std_logic;
clk1s: out std_logic;
reset: in std_logic
);
end component;
component BCDto7seg is
Port (
clk: in std_logic;
reset: in std_logic;
cat: in std_logic;
led7seg: out std_logic_vector(6 downto 0)
);
end component;
component frequency1 is
Generic (
N: integer:=1e8
);
Port(
clk: in std_logic;
reset: in std_logic;
clk100s: out std_logic
);
end component;
signal cat_temp: std_logic;
signal clk_1s: std_logic;
begin
D1: frequency Generic map(N=>1e8)
Port map(
clk=>clk100M,
clk1s=>clk_1s,
reset=>reset
);
D100: frequency1 Generic map(N=>1e8)
port map(
clk=>clk100M,
reset=>reset,
clk100s=>cat_temp
);
C1: BCDto7seg port map(
 clk=>clk_1s,
reset=>reset,
cat=>cat_temp,
led7seg=>led_7segment
);
cat1<=cat_temp;
end Behavioral;

8. Thiết kế mạch đếm tiến có reset đồng bộ/ không đồng bộ có thể là mã nhị
phân, mã BCD dư 3, mã Gray.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity demBCDdu3 is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
count_en : in STD_LOGIC;
BCD_out : out STD_LOGIC_VECTOR (3 downto 0);
BCD_div3 : out STD_LOGIC
);
end demBCDdu3;

architecture Behavioral of demBCDdu3 is

signal BCD_counter : STD_LOGIC_VECTOR (3 downto 0);
signal BCD_temp : STD_LOGIC_VECTOR (3 downto 0);
signal reset_sync : STD_LOGIC;

begin

-- Quy tr?nh đ?ng b? hóa reset

process(clk, reset)
 begin
if reset = '1' then
reset_sync <= '1';
elsif rising_edge(clk) then
reset_sync <= '0';
end if;
end process;

-- Quy tr?nh đ?m và tính toán BCD

process(clk)
begin
if rising_edge(clk) then
if reset_sync = '1' then
BCD_counter <= "0000";
elsif count_en = '1' then
BCD_temp <= BCD_counter + "0001";
if BCD_temp = "1010" then -- Đ?m t? 0 đ?n 9
BCD_counter <= "0000";
else
BCD_counter <= BCD_temp;
end if;
end if;
end if;
end process;

-- Output BCD value

BCD_out <= BCD_counter;

-- Output BCD_div3
BCD_div3 <= '1' when BCD_counter = "0011" else '0';

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_demBCDdu3 is
end tb_demBCDdu3;

architecture behavior of tb_demBCDdu3 is

signal clk : STD_LOGIC := '0';
signal reset : STD_LOGIC := '0';
signal count_en : STD_LOGIC := '0';
signal BCD_out : STD_LOGIC_VECTOR (3 downto 0);
signal BCD_div3 : STD_LOGIC;

constant clk_period : time := 10 ns; -- Clock period (100 MHz)

-- Component instantiation
component demBCDdu3
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
count_en : in STD_LOGIC;
BCD_out : out STD_LOGIC_VECTOR (3 downto 0);
BCD_div3 : out STD_LOGIC
);
end component;

begin
-- Instantiate the demBCDdu3 component
UUT: demBCDdu3
port map (
clk => clk,
reset => reset,
count_en => count_en,
BCD_out => BCD_out,
BCD_div3 => BCD_div3
);
-- Clock process
process
begin
while true loop
clk <= '0';
wait for clk_period / 2;
clk <= '1';
wait for clk_period / 2;
end loop;
end process;

-- Stimulus process
process
begin
-- Reset initially
reset <= '1';
count_en <= '0';
wait for 20 ns; -- Hold reset for a short period
reset <= '0';
wait for 10 ns;

-- Enable counting
count_en <= '1';
wait for 100 ns;

-- Hold counting
count_en <= '0';
wait for 20 ns;

-- Enable counting again

count_en <= '1';
wait for 100 ns;

-- Reset and disable counting

reset <= '1';
 count_en <= '0';
wait for 20 ns;
reset <= '0';
wait for 100 ns;

-- Enable counting
count_en <= '1';
wait for 100 ns;

-- Hold counting
count_en <= '0';
wait for 20 ns;

-- Enable counting again

count_en <= '1';
wait for 100 ns;

-- End simulation
wait;
end process;

end behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity demgray is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
Gray_out : out STD_LOGIC_VECTOR (3 downto 0)
 );
end demgray;

architecture Behavioral of demgray is

signal binary_counter : integer range 0 to 15 := 0;
signal Gray_counter : STD_LOGIC_VECTOR (3 downto 0) := "0000";

begin

process(clk, reset)
begin
if reset = '1' then
binary_counter <= 0;
Gray_counter <= "0000";
elsif rising_edge(clk) then
binary_counter <= binary_counter + 1;
case binary_counter is
when 0 => Gray_counter <= "0000";
when 1 => Gray_counter <= "0001";
when 2 => Gray_counter <= "0011";
when 3 => Gray_counter <= "0010";
when 4 => Gray_counter <= "0110";
when 5 => Gray_counter <= "0111";
when 6 => Gray_counter <= "0101";
when 7 => Gray_counter <= "0100";
when 8 => Gray_counter <= "1100";
when 9 => Gray_counter <= "1101";
when 10 => Gray_counter <= "1111";
when 11 => Gray_counter <= "1110";
when 12 => Gray_counter <= "1010";
when 13 => Gray_counter <= "1011";
when 14 => Gray_counter <= "1001";
when 15 => Gray_counter <= "1000";
when others => Gray_counter <= "0000";
end case;
 end if;
end process;

Gray_out <= Gray_counter;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_demgray is
end tb_demgray;

architecture behavior of tb_demgray is

signal clk : STD_LOGIC := '0';
signal reset : STD_LOGIC := '0';
signal Gray_out : STD_LOGIC_VECTOR (3 downto 0);

constant clk_period : time := 10 ns; -- Clock period (100 MHz)

-- Component instantiation
component demgray
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
Gray_out : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;

begin
-- Instantiate the demgray component
UUT: demgray
port map (
clk => clk,
reset => reset,
 Gray_out => Gray_out
);

-- Clock process
process
begin
while true loop
clk <= '0';
wait for clk_period / 2;
clk <= '1';
wait for clk_period / 2;
end loop;
end process;

-- Stimulus process
process
begin
-- Reset initially
reset <= '1';
wait for 20 ns; -- Hold reset for a short period
reset <= '0';
wait for 10 ns;

-- Enable counting
wait for 200 ns;

-- Hold counting
wait for 20 ns;

-- Reset and disable counting

reset <= '1';
wait for 20 ns;
reset <= '0';
wait for 100 ns;
 -- Enable counting
wait for 200 ns;

-- Hold counting
wait for 20 ns;

-- End simulation
wait;
end process;

end behavior;

9. Thiết kế mạch led 8 bit nháy theo yêu cầu: Ví dụ: yêu cầu led nháy lần lượt,
sáng lần lượt, hoặc tắt lần lượt theo thời gian yêu cầu

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sang_led is
Port (clk, rst: in std_logic;
led: out std_logic_vector(7 downto 0));
end sang_led;

architecture Behavioral of sang_led is

type sangled is (Idle, S1, S2, S3, S4, S5, S6, S7, S8);
signal pr_state, nx_state: sangled;
signal tmp: std_logic_vector(7 downto 0);
signal clk_1, clk_2, clk_5: std_logic;
component clk_div
Port ( clk_100M: in std_logic;
rst : in std_logic;

clk_2s: out std_logic;

clk_5s: out std_logic;
clk_1s: out std_logic );
 end component;
begin
clock: clk_div
port map (clk_100M => clk, rst => rst, clk_2s => clk_2, clk_5s => clk_5,
clk_1s => clk_1);
process (clk_5, rst)
begin
if (rst = '0') then
pr_state <= Idle;
else
if (rising_edge(clk_5)) then
pr_state <= nx_state;
end if;
end if;
end process;

process (pr_state)
begin
case pr_state is
when idle =>
tmp <= "00000000";
nx_state <= S1;
when S1 =>
tmp <= "00000001";
nx_state <= S2;
when S2 =>
tmp <= "00000010";
nx_state <= S3;
when S3 =>
tmp <= "00000100";
nx_state <= S4;
when S4 =>
tmp <= "00001000";
nx_state <= S5;
when S5 =>
 tmp <= "00010000";
nx_state <= S6;
when S6 =>
tmp <= "00100000";
nx_state <= S7;
when S7 =>
tmp <= "01000000";
nx_state <= S8;
when S8 =>
tmp <= "10000000";
nx_state <= S1;
when others =>
tmp <= "11111111";
nx_state <= idle;
end case;
end process;

out_fsm: process (clk_5, tmp)

begin
if (rising_edge (clk_5)) then
led <= tmp;
end if;
end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tat_led is
Port (clk, rst: in std_logic;
led: out std_logic_vector(7 downto 0));
end tat_led;
architecture Behavioral of tat_led is
type tatled is (Idle, S1, S2, S3, S4, S5, S6, S7, S8);
signal pr_state, nx_state: tatled;
signal tmp: std_logic_vector(7 downto 0);
signal clk_1, clk_2, clk_5: std_logic;
component clk_div
Port ( clk_100M: in std_logic;
rst : in std_logic;

clk_2s: out std_logic;

clk_5s: out std_logic;
clk_1s: out std_logic );
end component;
begin
clock: clk_div
port map (clk_100M => clk, rst => rst, clk_2s => clk_2, clk_5s => clk_5,
clk_1s => clk_1);
process (clk_5, rst)
begin
if (rst = '0') then
pr_state <= Idle;
else
if (rising_edge(clk_5)) then
pr_state <= nx_state;
end if;
end if;
end process;

process (pr_state)
begin
case pr_state is
when idle =>
tmp <= "11111111";
nx_state <= S1;
when S1 =>
 tmp <= "11111110";
nx_state <= S2;
when S2 =>
tmp <= "11111101";
nx_state <= S3;
when S3 =>
tmp <= "11111011";
nx_state <= S4;
when S4 =>
tmp <= "11110111";
nx_state <= S5;
when S5 =>
tmp <= "11101111";
nx_state <= S6;
when S6 =>
tmp <= "11011111";
nx_state <= S7;
when S7 =>
tmp <= "10111111";
nx_state <= S8;
when S8 =>
tmp <= "01111111";
nx_state <= S1;
when others =>
tmp <= "00000000";
nx_state <= idle;
end case;
end process;

out_fsm: process (clk_5, tmp)

begin
if (rising_edge (clk_5)) then
led <= tmp;
end if;
end process;
 end Behavioral;

10.Thiết kế mạch kiểm tra dãy tín hiệu đầu vào, yêu cầu: kiểm tra dãy tín hiệu
đầu vào là 1010….

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fsm is

Port ( reset : in STD_LOGIC;

clk : in STD_LOGIC;

x : in STD_LOGIC;

found_moore : out STD_LOGIC);

end fsm;

architecture Behavioral of fsm is

type state_moore is (IDLE, s1, s10, s100, s1001);

signal pr_moore, nx_moore: state_moore;

begin

process(clk, reset)

begin

if rising_edge(clk) then

if reset = '0' then

pr_moore <= IDLE;

else
 pr_moore <= nx_moore;

end if; end if;

end process;

-------MOORE------

moore: process(pr_moore, x)

begin

case pr_moore is

when IDLE =>

if x ='0' then

nx_moore <= IDLE;

else

nx_moore <= s1;

end if;

when s1 =>

if x ='0' then

nx_moore <= s10;

else

nx_moore <= pr_moore;

end if;

when s10 =>

if x ='0' then

nx_moore <= s100;

 else

nx_moore <= s1;

end if;

when s100 =>

if x ='0' then

nx_moore <= IDLE ;

else

nx_moore <= s1001;

end if;

when s1001 =>

if x ='0' then

nx_moore <= s10;

else

nx_moore <= s1;

end if;

end case;

end process;

------OUT_MOORE------

out_moore: process(pr_moore)

begin

case pr_moore is

when s1001 => found_moore <= '1';

 when others => found_moore <='0';

end case;

end process;

end Behavioral;

Yêu cầu: mỗi sinh viên đem theo tài liệu là USB vào phòng thi, mở vivado bằng
lệnh trên hệ điều hành Ubuntu như sau:

Source /opt/Xilinx/Vivado/2016.4/settings64.sh

Vivado