超大型積體電路導論

Introduction to Very Large Scale Integrated

Circuits
EL3038

Speed (Delay)
Instructor: 江建學
Date:2024/11/21
Chapter 3

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『注意：請遵守智慧財產權觀念。不得非法影印教科書。』
Speed - Outline
3.1 Introduction

3.2 Transient Response

3.3 RC Delay model

3.4 Linear Delay Model

3.5 Logical Effect of Path

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Speed – Introduction - Definitions
傳播延遲

汙染，弄髒；玷汙

-Rise/fall times are also sometimes called slopes or edge rates.

-Propagation and contamination delay times are also called max-time
and min-time, respectively
- Propagation delay is usually the most relevant value of interest, and is
often simply called delay

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Propagation and Contamination Delay
-Combinational logic is characterized by its propagation delay and contamination delay. The propagation delay tpd is the
maximum time from when an input changes until the output or outputs reach their final value. The contamination delay
tcd is the minimum time from when an input changes until any output starts to change its value.

-When designers speak of calculating the delay of a circuit, they generally are referring to the worst-case value (the
propagation delay), unless it is clear otherwise from the context.
-Figure illustrates a buffer's propagation delay and contamination delay in blue and gray, respectively. The figure shows
that A is initially either HIGH or LOW and changes to the other state at a particular time; we are interested only in the fact
that it changes, not what value it has. In response, Y changes some time later. The arcs indicate that Y may start to
change tcd after A transitions and that Y definitely settles to its new value within tpd.

https://www.sciencedirect.com/topics/computer-science/contamination-
delay 4
Speed – Introduction - Definitions
-The timing analyzer computes the arrival times at each node and checks that the outputs arrive.
鬆弛；懈怠
-The slack is the difference between the required and arrival times.
→Positive slack means that the circuit meets timing.
→Negative slack means that the circuit is not fast enough

*If the outputs are all required at 200 ps, the circuit has 60 ps of slack.
(choose the max. delay as the main delay path)

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Speed – Introduction - Definitions

-There will be a number of critical paths that limit the operating speed of the system and
require attention to timing details

1. The architectural/microarchitectural level

微結構層級間的設計選擇包含管路級數、執行單位數目和記憶體大小
2. The logic level
設計選擇包含函數區塊形式、一個週期裡邏輯閘的級數與輸入輸出數
3.The circuit level
可選擇電晶體大小或其他CMOS邏輯形式調整延遲
4. The layout level
佈局的技巧也可做延遲的優化

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Speed – Transient Response
-The most fundamental way to compute delay (transient response)
1.develop a physical model of the circuit
2.write a differential equation describing the output voltage as a function of input voltage and time,
3.solve the equation.
→The solution of the differential equation is called the transient response,(對t時間作微分)

*DC analysis tells us Vout if Vin is constant

-Input is usually considered to be a step or ramp

>From 0 to VDD or vice versa

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Speed – Transient Response
-Find step response of inverter driving load cap

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Example 4.1

bootstrapping -The propagation delay predicted by the RC model matches

SPICE fairly well

-RC models will be explored further in Section 4.3

-SPICE simulator solves the equations numerically

→Uses more accurate I-V models too!

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Speed – RC Delay Model - Switch-level RC Delay Models

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Speed – RC Delay Model - Switch-level RC Delay Models
-The unit inverters of Figure 4.6(a) are composed from an nMOS transistor of unit size and a pMOS transistor of twice unit
width to achieve equal rise and fall resistance

- Figure 4.6(b) gives an equivalent circuit, showing the first

inverter driving the second inverter’s gate.
→ If the input A rises, the nMOS transistor will be ON and the
pMOS OFF

-Figure 4.6(c) illustrates this case with the switches removed

→The total capacitance on the output Y is 6C.

* The capacitors shorted between two constant supplies are also removed
because they are not charged or discharged

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Speed – Example 4.2
-Sketch a 3-input NAND gate with transistor widths chosen to achieve
effective rise and fall resistance equal to that of a unit inverter (R).

-The three nMOS transistors are in series so the resistance is three times that of a single
transistor.
→each must be three times unit width to compensate.
→each transistor has resistance R/3
→the series combination has resistance R.

-The two pMOS transistors are in parallel.

→In the worst case (with one of the inputs low), only one of the pMOS transistors is ON.
→each must be twice unit width to have resistance R.

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Speed – Example 4.2

-Figure 4.7(b) shows the capacitances.

-Each input presents five units of gate.

→Notice that the capacitors on source diffusions attached to the rails
(VDD/GND) have both terminals shorted together
→so they are irrelevant to circuit operation.

- Figure 4.7(c) redraws the gate with these capacitances deleted and the
remaining capacitances lumped to ground

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Speed – Example 4.2

- Figure 4.7(d) shows the equivalent circuit for the falling output transition.
→The output pulls down through the three series nMOS transistors.

-Figure 4.7(e) shows the equivalent circuit for the rising output transition.
→In the worst case, the upper two inputs are 1 and the bottom one falls to 0.
→The output pulls up through a single pMOS transistor.
→The upper two nMOS transistors are still on, so the diffusion capacitance
between the series nMOS transistors must also be considered.

WHY?

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Speed – Elmore Delay

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Speed – Example 4.4
Estimate tpd for a unit inverter driving m identical unit inverters

-Each load inverter presents 3C units of gate capacitance,

→for a total of 3mC.
Inv_1
-The output node also sees a capacitance of 3C from the drain
diffusions of the driving inverter.
→This capacitance is called parasitic
→The parasitic capacitance is independent of the load that
the inverter is driving.

-The total capacitance is (3 + 3m)C

-The resistance is R

Inv_m

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Speed – Example
-A NAND driving h identical NAND gates What is the worst case
→ Compute the worst rising and falling propagation delay - Estimate rising propagation delay

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Speed – RC Delay Model
-A NAND driving h identical NAND gates What is the worst case
→ Compute the worst rising and falling propagation delay
- Estimate Falling propagation delay

If B turn-on faster than A, Vx=0

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Speed – RC Delay Model

https://slideplayer.com/slide/10652619/ 19
Speed – Linear Delay Model
-The RC delay model showed that delay is a linear function of the fanout of a gate
-The normalized delay of a gate p: internal parasitic delay driving no load

-f is the effort delay or stage effort that depends on the complexity and fanout of the gate.

→g: logic effort–measure relative ability of gate to deliver current

g = 1 for inverter; g=5/3 for 3-input NAND (previous example)

-A gate driving h identical copies of itself is said to have a fanout or electrical effort of h.
→h: electrical effort = Cout / Cin (fanout)

-Cout is the capacitance of the external load being driven

-Cin is the input capacitance of the gate

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Speed – Linear Delay Model

-The y-intercepts indicate the parasitic delay,

→i.e., the delay when the gate drives no load

-The slope of the lines is the logical effort.

-The inverter has a slope of 1 by definition.

-The 3-input NAND has a slope of 5/3.

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Speed – Logical Effort

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Speed – Logical Effort
-Logical effort of a gate is defined as the ratio of the input capacitance of the gate to the
input capacitance of an inverter that can deliver the same output current.
→Equivalently, logical effort indicates how much worse a gate is at producing output
current as compared to an inverter, given that each input of the gate may only present as
much input capacitance as the inverter.
(相比的gate可產生與反向器相同輸出電流時的最差的延遲效果(more input capacitance))

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Speed – Logical Effort

-Which is better in terms of logic effort? NAND or NOR?

→NAND gates are better than NOR gates because the series transistors are nMOS rather than pMOS

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Speed – Parasitic Delay
-The parasitic delay of a gate is the delay of the gate when it drives zero load.
-The inverter has three units of diffusion capacitance on the output, so the parasitic delay is
→the normalized parasitic delay is 1
-Increasing transistor sizes reduces resistance but increases capacitance correspondingly, so
parasitic delay is independent of gate size

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Speed – Parasitic Delay (More refined estimates)
-Figure 4.23 shows a model of an n-input NAND gate in which the upper inputs were all 1 and the
bottom input rises.
-The gate must discharge the diffusion capacitances of all of the internal nodes as well as the output
-The Elmore delay is

Grows more than linearly with # of inputs

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Speed – Parasitic Delay
Example 4.10
-Use the linear delay model to estimate the delay of the fanout-of-4 (FO4) inverter from Example 4.6. Assume the
inverter is constructed in a 65 nm process with τ=3ps

-The logical effort of the inverter is g 1, by definition.

-The electrical effort is 4 because the load is four gates of equal size.
-The parasitic delay of an inverter is pinv=1

The total delay is d gh p 1 × 4 1 5 in normalized terms
→ tpd 15

* As a rough rule of thumb, the FO4 delay for a process (in picoseconds) is 1/3 to 1/2 of
the drawn channel length (in nanometers).
→ For example, a 65 nm process with a 50 nm channel length may have an FO4 delay of 16–25 ps

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Speed – Parasitic Delay
Example 4.11
-A ring oscillator is constructed from an odd number of inverters, as shown in Figure 4.24. Estimate the
frequency of an N-stage ring oscillator.

because a value must propagate twice around the ring to

regain the original polarity.(has a period of 2N stage)

*A 31-stage ring oscillator in a 65 nm process has a frequency of 1/(4 × 31 × 3 ps) = 2.7 GHz.

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