SESSION Ill: SAMPLED-DATA ANALOG CIRCUITS

W A M 3.3: A CMOS ProgrammableSelf-calibrating 13b Eight-Channel Analog Interface Processor

Michael Armstrong, Harlian Ohara, Ho Ngo, Chowdhury Rahim, Anita Grossman

Microlinear Corp.

San Jose, C A
of the input sample to the .4DC, the same samplejhold samples
the reference source selected in software. The reference source
Paul R. Gray can be floating and time varying, and since both the reference
and the signal pass through this sample/hold, the full scale
University of California accuracy is unaffected by the capacitor ratios within it.
Berkeley, CA The conversion technique used is the algorithmic approach,
selected because of its small area and inherent ablllty to carry
out signal preamplification”21s. In this technique the succes-
sive approximation algorithm is carried out bymultiplying the
AN IMPORTANT BARRIER to the realization of higher levels signal by two, comparing with the reference, and subtracting
of integration in general-purpose data acquaition components the reference if the signal is larger. The result is taen recirculated
has been the diversity of applications, with varying requirments for the next bit decision. The three cyelc-per-bit operation of
o n converter resolution, sampling rate, synchronization method, the two amplifier algorithmic loop is illustrated in Figure 2.
reference source, channel dc gain, etc. This paper will describe The three cycles of operation are designated I, 2, and 3 with
a single-chip eight-channel CMOS programmable 13b (12b t sign) corresponding switch closures indicated. In phase I , thc sam-
data acquisition system with conversion time of 25ps in stan- pling m’ode, the input or remainder is loaded on capacitor 2C.
dard 3pm CMOS. It addresses a diverse spectrum of applications In phase 2, the compare phase, Al, is used as a Comparator to
by utilizing a processor-like architecture in which most systems compare the sampled value to VR/2. In phase 3,’the reconstruct
attributes are reconfigurable under the control of an on-board mode, the remainder is reconstructed and sampled on A2.
programmable sequencer. The analog elements of the chip in- The algorithmic technique requires that loop offsets be
clude an analog input multiplexer configurable as eight single- smaller than 0.5 LSB in order to achieve 0.5 LSB integral
ended or four differential channels, a differential-input self- linearity in the conversion. This requires the use of a pre-
calibrated algorithmic A/D converter block implementing the cision offset-nulling approach that not onlyremoves opamp
converter, sample/hold, and programmable-gain amplifier func- offsets, but cancels charge injection offsets as well. This
tions, and a precision bandgap reference using lateral devices offset and charge-injection nulling scheme is illustrated
and containing an auxiliary thermometer output. The operation conceptually in Figure 3. During the auto-zero cycle the
of these.elements is controlled by an on-board programmable four gain-setting capacitors are grounded, and the common-mode
sequencer with internal instructionmemory, data memory, opamp input voltage has been initialized previously with summing
timer, data comparator, and microprocessor bus interface with node grounding switches. The summing node shorting switch S1,
DMA capability. A block diagram of the system is shown in initially on, is turned off, which results in any charge injection
Figure 1. imbalance from it appearing as an offset applied to the input
The input section consists of an input multiplexer followed terminals of the opamp. Next, the feedback loop 1s closed
by a differential sampling amplifer whose common-mode range around the opamp through an auxiliary input stage with a gm
includes both supplies4. Prior to the start of the input sampling of one-tenth that of the main input stage. The AZ switches
operation, the offset of the opamp as well as the charge injec- are then opened, storing a voltage approximately equal to 10
tion offset are stored on the offset cancellation capacitor in a times the combined total of the opamp offsetand the charge
dummy sampling/amplification cycle. Following the transfer injection offset on the offset correction capacitors. Because of
the lower gm of this auxiliary stage, the charge injection mis-
match from the opening of the AZ switches is reduced by a
‘McCharles, R.
and
Hodges,
D.A., “Charge Circuits for factor of 10 when referred t o the input’. This offset correc-
Analog LSI”, IEEE Transactions o n Circuits and Systems, Vol. tion voltage is stored throughout the remainder of the convcr-
CAS 2 5 ; July, 1978. sion and cancels both components of offset. A major advantage
2Li, P.W., Chin, M., Gray.P.R.andCastello,R..“ARatio of this approach is that all offsets are canceled and that the
Independent
Algorithmic
Analog-Digital
Conversion
Tech- cancellation circuitry is not in the signal path and does not
nique”, IEEEJournal o f Solid-StateCircuits, Vol.SC-19, 6;
Dec., 1984. affect the settling time or bandwidth of the amplifier in the
active mode. Typical observed offset voltage is less than 1OOpV.
3Yen,R.C.andGray,P.R., “ A n MOS SwitchedCapacitor
Sampling Differential Instrumentation Amplifier”, IEEE Journal The converter uses two high-speed differential folded cascode
of Solid-State Circuits, Vol. SC-17; Dec., 1982. operational amplifiers. These amplifiers incorporate triple
4Webb, R.W.. Cooper,F.R.andRandlett, R.W., “ A1 2 b caseodes and optimized high-swing tracking bias to achieve
A/D Converter”. ISSCCDIGEST O F T E C H N I C A LP A P E R S , a typical voltage gain of 100,000, a typical voltage swing at
P. 54-55; Feb., 1980. each output towithin 1.2V of the supplies, and a worst-case
’Degrauwe, M., Vittoz, E. and Verbaouwhede, I., “ A Micro- settling time of 400ns to 0.02%with a lOpF load and 6V
power CMOS Instrumentation Amplifier”, I E E E Journal of differential step at the output. A simplified circuit diagram
Solid-state Circuits;June, 1985.
is shown in Figure 4.

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 The second critical source of linearity error stems from the because of capacitor ratio or other errors, then the result of this
fact that algorithmic converters require that the gain in the loop reference voltage conversion is a value less than full scale. Full-
be exactly two with anaccuracy comparable with the desired scale reference conversions at 16b resolution are used as a test
level of linearity. Converter linearity is achieved through a se- in a successive approximation algorithm to set the calibration
parate calibration sequence in which the value of the loop gain is of the loop gain value at precisely 2. To provide noise immu-
adjusted using a programmable capacitor. The trim network nity, each of the steps in the successive approximation process
makes use of the t-network concept to provide the ability to giving the optimum trim,actually consists of seven full con-
control the amplifier gain in steps of one part in 64K while using versions, with a majority vote rule used to define the test out-
moderate capacitor ratios. The trim DAC need not be either come.
linear or monotonic as long as the transfer characteristic has no A function analogous to that provided by a programmable
gaps. This allows the use of a minimum-size unit element capa- gain instrumentation amplifier is provided by recirculating the
citor of 35fF and the implementation of the trim array in a very signal through the 2x loop priorto the start of conversion,
small area. Since the 2x gain is precisely set by the calibration process,
The calibration sequence is initiated under system control this amplifier gain value is precisely controlled. The value of
and utilizes the fact that inan algorithmic converter, when the gain is software selectable to be 1, 2, 4, o r 8.
loop gain is exactly equalto 2, an A/D conversion performed on Various aspects of the performance of the chip are sum-
an input voltage equal to the reference voltage gives a result marized in Table 1. A die photo is shown in Figure 5.
which is exactly equal to fullscale. If the loop gain is too small

-1
CHO_
RESET
w
CLK
SYNC
4NALOG
MUX

PROGRAMMABLE
SEQUENCER

CH7_

J INTIN7
DBR
ALE
TCLK

I** = SAMPLING
PHASE,
FIRST
CYCLE 3** = RECONSTRUCT
PHASE, b=O
I* = SAMPLING
PHASE,
SUBSEQUENT
CYCLES 3* = RECONSTRUCT
PHASE, b=l
1 = 1**+1* 3 = 3**+3*
2 = COMPAREPHASE

FIGURE l-A/D processor chip block diagram. FIGURE 2-Algorithmic A/D converter schematic diagram.

AcHch AZ
9

- OUT-

'.A U X l L L l A R YI N P U TS T A G E
FIGURE 3-Conceptual illustration of offset cancellation
technique.
VDD

COMMON-

FIGURE 4-Simplified schematic diagram of folded caseode FEEDBACK

INPUT
operational amplifier.

[Seepage334 for Figure SITable I . ]

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 FIGURE 5-Die photograph.

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 TABLE 1-Typicalperformance,25C, t 5Vsupplies:a-
ADC; b-inputsample/hold and programmableamplifier output
Nominal value 2.500V
function; c-voltage reference; d-overall chip. Drift, 0-70C k 18ppm
PSR R 85dB
Integral
nonlinearity
after col 0.4LSB @ 12b
Max output current 3m.4
offsetInput voltage 0.3mV
Rout 0.15a
Conversion time (includesgain, SIH)
8b, I x gain 1 8 ~ Thermometer
output
sensitivity SmV/degC
136, I x g a i n 25Y
8b. 8x gain 211-ls (c)
I3b, 8 x gain 28W
Power dissipation,
active 25OmW
Max. Vref value 3.2V
Power
dissipation, power
down 1mW
system (a) (external
accuracy gain vref)0.04%
Input offset voltage O.1mV Die size 255 x 272mil

CMRR (dc) >lO0dB Technology 3pm, 2 poly CMOS

PSRR (dc) 76dB Number of transistors 25,000

(b) (4

FIGURE 5-Chip photomicrograph.

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