USOO8248.

108B2

(12) United States Patent (10) Patent No.: US 8.248,108 B2

Santoro et al. (45) Date of Patent: Aug. 21, 2012
(54) COMPARATOR WITH OFFSET Apisak Worapishet et al.; Speed and Accuracy Enhancement Tech
COMPENSATION, IN PARTICULAR FOR niques for High-Performance Switched-Current Comparators IEEE
ANALOG DIGITAL CONVERTERS Journal of Solid-State Circuits, IEEE Service Center, Piscataway, NJ,
vol. 36, No. 4, Apr. 1, 2001, pp. 687-689 XP01 1061500.
(75) Inventors: Manuel Santoro, Milan (IT); Fabio Shimizu, Y et al. A 30mW 12b 40MS/s Subranging ADC With a
Bottinelli, Malnate (IT) High-Gain Offset-Canceling, Positive-Feedback Amplifier in 90mm
digital CMOS, Solid-State Circuits, 2006 IEEE International Con
(73) Assignee: STMicroelectronics S.r.l., Agrate ference Digest of Technical papers, Feb. 6-9, 2006, Piscataway, NJ,
Brianza (MI) (IT) IEEE Feb. 6, 2006, pp. 802-811 XPO10940464.
Matsuzawa, A. Design Challenges of Analog-to-Digital Converters
(*) Notice: Subject to any disclaimer, the term of this in Nanoscale CMOS, IEICE Transactions on Electronics, Electronics
patent is extended or adjusted under 35 Society, Tokyo, JP vol. E90Cmbi, 4m, Apr. 1, 2007, pp. 779-785,
U.S.C. 154(b) by 4 days. XPOO1541955.

(21) Appl. No.: 12/727,104 (Continued)

(22) Filed: Mar 18, 2010 Primary Examiner — John Poos
(74) Attorney, Agent, or Firm — Wolf, Greenfield & Sacks,
(65) Prior Publication Data P.C.
US 2010/0237907 A1 Sep. 23, 2010 (57) ABSTRACT
(30) Foreign Application Priority Data A comparator formed by first and second stages. The second
stage is formed by a pair of output transistors connected
Mar. 18, 2009 (IT) .............................. TO2OO9AO2O7 between a power-supply line and respective output nodes; a
pair of bias transistors, connected between a respective output
(51) Int. C. node and a current source; a pair of memory elements, con
HO3K 5/22 (2006.01) nected between the control terminals of the output transistors
(52) U.S. Cl. ................... 327/63; 327/65; 327/67; 330/9 and opposite output nodes; and Switches coupled between the
(58) Field of Classification Search .................... 327/63, control terminals of the respective output transistors and the
327/65, 67: 330/9 respective output nodes. In an initial autoZeroing step, the first
See application file for complete search history. stage stores its offset so as to generate an offset-free current
signal. In a Subsequent tracking step, the second stage
(56) References Cited receives the current signal and the memory elements store
control Voltages of the respective output transistors. In a
U.S. PATENT DOCUMENTS Subsequent evaluating step, the first stage is disconnected
6,750,704 B1* 6/2004 Connell et al. .................... 330.9 from the second stage and the memory elements receive the
7,400.279 B2 * 7/2008 Krymski ....................... 341,118 current signal and Switch the first and the second output node
2006,0164.125 A1 7, 2006 Mulder depending on the current signal. In Subsequent comparisons,
OTHER PUBLICATIONS the tracking and evaluating steps follow one another without
performing the autoZeroing step.
Italian Search Report and Written Opinion dated Sep. 25, 2009, from
corresponding Italian Application No. TO20090207. 18 Claims, 9 Drawing Sheets

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 US 8.248.108 B2
Page 2

OTHER PUBLICATIONS Razavi, Betal. Design Techniques for High-Speed, High-Resolution

Comparators, IEEE Journal of Solid-State Circuits. vol. 27.No.
Verma, N, et al. An Ultra Low Energy 12-Bit Rate-Resolution Scal- 12, Dec. 1992, pp. 1916-1926.
able SAR ADC for Wireless Sensor Nodes, IEEE Journal of Solid- Doernberg, Jet al. A 10-bit 5-Msample/s CMOS Two-Step Flash
State Circuits, vol. 42, No. 6, Jun. 2007, pp. 1196-1205. ADC, IEEE Journal of Solid-State Circuits, Apr. 1989, vol. 24 No. 2,
Shima.T et al., Simple and Accurate Comparator Circuit, Circuits pp. 241-249.
and Systems, 2002, MWSCAS-2002, 45' Midwest Symposium, Pub.
Aug. 4-7, 2002, vol. 1, pp. 299-302. * cited by examiner
U.S. Patent Aug. 21, 2012 Sheet 1 of 9 US 8.248,108 B2

VCM VCM VCM VCM

FIG. 1
U.S. Patent Aug. 21, 2012 Sheet 2 of 9 US 8.248,108 B2

CK1

Ck2

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C C1

WOUT WOUTt
VN - o oVN
SW2

SW1
Vbias

F/G, 3
U.S. Patent Aug. 21, 2012 Sheet 3 of 9 US 8.248,108 B2
U.S. Patent Aug. 21, 2012 Sheet 4 of 9 US 8.248,108 B2
U.S. Patent Aug. 21, 2012 Sheet 5 of 9 US 8.248,108 B2

WOA )
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U.S. Patent Aug. 21, 2012 Sheet 6 of 9 US 8.248,108 B2

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U.S. Patent Aug. 21, 2012 Sheet 7 Of 9 US 8.248,108 B2

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U.S. Patent Aug. 21, 2012 Sheet 8 of 9 US 8.248,108 B2

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U.S. Patent Aug. 21, 2012 Sheet 9 of 9 US 8.248,108 B2

SOC

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Logic Unit

VREF

3/4 VREF

1/2 VREF

1/4 VREF

I bit
- 3=0 2 it 1- bit O=1 t
(MSB) bit 2=1 bit 1-0 (LSB)
-L L- -------

FIG 11
 US 8,248,108 B2
1. 2
COMPARATOR WITH OFFSET connected between the gate terminals of two transistors 5 and
COMPENSATION, IN PARTICULAR FOR 6, of the difference in gate-source voltage of two transistors 5,
ANALOG DIGITAL CONVERTERS 6 in the absence of a signal. Thereby, in the Subsequent
comparing step and then in the step latching, the output signal
CROSS REFERENCE TO RELATED is independent of the offset. This solution has a less compli
APPLICATIONS cated structure than the previous one with respect to the
auxiliary circuitry, but requires the inputs to be shorted before
This application claims the priority benefit of Italian patent each comparison as the stored offset is lost after the compari
application number TO2009A000207, filed on Mar. 18, 2009, SO.
entitled “COMPARATOR WITH OFFSET COMPENSA 10
It is an object of the present invention to provide a com
TION, IN PARTICULAR FOR ANALOG DIGITAL CON parator overcoming the drawbacks of the prior art.
VERTERS,” which is hereby incorporated by reference to the
maximum extent allowable by law. SUMMARY OF THE INVENTION
BACKGROUND OF THE INVENTION 15
According to at least one embodiment, the present inven
1. Field of the Invention tion provides a comparator, comprising a first stage and a
The present invention relates to a comparator with offset second stage, the first stage being configured so as to receive
compensation, in particular for analog digital converters a Voltage input signal and generate a current signal, the sec
(ADCs) operating by Successive approximations (ADC ond stage comprising a first and a second output transistor
SAR-Analog Digital Converter Successive Approximation connected between a reference potential line and, respec
Register). tively, a first and a second comparator output node, a pair of
2. Discussion of the Related Art bias devices, connected between a respective comparator out
As is known, precision is an important requirement for put node and an output bias current source, a first memory
comparators; techniques ensuring a reliable correction of the 25 element, connected between a control terminal of the first
existing offset due to the mismatch among physical compo output transistor and the second comparator output node, a
nents forming the converter are therefore required. second memory element, connected between a control termi
Several solutions have been suggested for correction of the nal of the second output transistor and the first comparator
offset. output node, and bias Switches coupled between a control
A first solution, shown in FIG.1 and disclosed in B. Razavi, 30 terminal of a respective output transistor and a respective
B. Wooley “Design Techniques for High-Speed, High-Reso comparator output node.
lution Comparators, IEEE Journal of Solid-State VOL. M7, According to at least one embodiment, the first stage com
N. 12, December 1992, comprises N preamplifier stages 1 prises a first and a second converter output node, the com
upstream of a latch 2 having an offset. The offset of pream parator further comprising a pair of connection Switches
plifiers 1 is detected in an initial autoZeroing step, by shorting 35 interposed between a respective converter output node and a
the inputs of preamplifiers 1 at a preset Voltage and sampling respective comparator output node, the connection Switches
the outputs of preamplifiers 1. Thereby, the offset of latch2 is and the bias Switches being configured so that, in a tracking
reduced, as it is divided by the product of the gains of pream step, the first stage is connected to the second stage and the
plifiers 1 (1/(G1* ... Gi ... *GN), Gi representing the gain first and second memory elements store a control Voltage of
of a generic preamplifier 1. Preamplifier stages 1 are gener 40 the respective output transistor and, in a evaluating step, the
ally low-gain (~2-3) in order to have a good band/consump first stage is disconnected from the second stage and the
tion ratio. Accordingly, in order to Sufficiently reduce the memory elements receive said current signal and Switch said
offset of latch 2, a certain number of preamplifier stages needs first and second output nodes according to said current signal.
to be provided, thereby the overall comparison time is rather According to at least one embodiment, the first and the
long and depends on the desired level of reduction of the 45 second memory elements are capacitors.
offset. Furthermore, the circuit has a considerable bulk and a According to at least one embodiment, the first stage com
high power consumption. prises a first and a second input transistors and a first and a
Another solution, shown in FIG. 2 and disclosed in N. second load transistors interposed between the reference
Verma, A. Chandrakasan “An Ultra Low Energy 12-bit Rate potential line and an input bias current Source, said first and
Resolution Scalable SARADC for Wireless Sensor Nodes', 50 second input transistors being connected to said first and
IEEE Journal of Solid-State VOL. 42, N. 6, June 2007, uses a second load transistors at respective converter output nodes.
latched comparator with a single offset cancellation in the According to at least one embodiment, the comparator
autoZeroing step at the beginning of conversion, thus elimi further comprises a third and a fourth memory element inter
nating the need to perform the resampling of the offset after posed between the control terminal of the first and, respec
each comparison. Namely, transistors 3 and 4, operating as 55 tively, of the second load transistor and the reference potential
current sources, are biased so that input transistors 1, 2 have line.
the same source voltages (VS1=VS2) when receiving identi According to at least one embodiment, the first stage fur
cal input signals Vy. This solution requires a rather compli ther comprises, an input circuit connected to said input tran
cated auxiliary circuitry for managing the different control sistors and configured so as to Supply a reference signal in an
steps, with a Subsequent impact on the occupied area. Fur 60 autoZeroing step and said input signal in a comparing step, a
thermore, the presence of local feedbacks leads to problems first and a second autoZero Switch interposed between a con
in the stability of the circuit in critical conditions. trol terminal of a respective load transistor and a respective
A further solution, shown in FIG. 3 and disclosed in T. converter output node and configured so as to receive an
Shima, K. Miyoshi "Simple and Accurate Comparator Cir autoZero signal so that, in the autoZeroing step, the load
cuit', IEEE Circuits and Systems VOL. 1, August 2002, uses 65 transistors are transdiode-connected and the third and fourth
a latched comparator with offset cancellation at each com memory elements store a signal correlated to an offset of the
parison. This circuit is based on the storing, on capacitor C first stage and, in the comparing step, the first and the second
 US 8,248,108 B2
3 4
autoZero Switches are open and the first stage Supplies the while the tracking and evaluating steps are performed in a
current signal to the converter output nodes. sequence one after another, for each comparison operation of
According to at least one embodiment, the input circuit the series.
comprises a first Switch interposed between a first comparator In comparator 100, a first stage 10 substantially forms a
input and a control terminal of the first input transistor, a 5 Voltage/current converter which, during the autoZeroing step,
second Switch interposed between a second comparator input stores an offset-compensated bias condition thereof, so that
and a control terminal of the second input transistor, a third during the Subsequent tracking and evaluating steps, it may
switch interposed between the control terminal of the first generate, on its outputs 13 and 14, current signals +i and -i,
input transistor and a common mode Voltage and a fourth dependent on input signals IN1 and IN2 received on its inputs
switch interposed between the control terminal of the second 10 11 and 12, but independent of the offset of first stage 10.
input transistor and the common mode Voltage, the first and A second stage 20 forms a latched comparator, which is
the second Switch being configured so as to Switch on in held in a reset condition during the autoZeroing step, con
nected to first stage 10 during the tracking step, so as to
counterphase with respect to the third and fourth switches. receive current signals 11 and 12 on its inputs 21 and 22 and
According to at least one embodiment, the comparator is 15 store an offset-compensated bias condition thereof, and is
included in an ADC SAR. disconnected from first stage 10 during the evaluating step, so
According to at least one embodiment, the present inven as to Switch and generate, on comparison outputs 23 and 24.
tion provides a method of comparing a Voltage signal Sup output signals O1, O2 only dependent on input signals IN1
plied to a comparator comprising a first stage receiving an and IN2.
input signal and a second stage outputting an output signal, In detail, first stage 10 comprises a pair of input transistors
including a tracking step and an evaluating step, the tracking M1, M2, herein of the NMOS type, having gate terminals
step comprising generating a current signal related to the connectable respectively to input 11 and input 12 through
input signal by the first stage, connecting a pair of output respective switches S1 and S2. Furthermore, the gate termi
transistors of the second stage between a reference potential nals of input transistors M1, M2 are connectable to a common
line and respective comparator output nodes, Supplying the 25 mode DC voltage VCM through respective switches S3 and
current signal to the pair of output transistors through respec S4. First terminals (herein the source terminals) of input
tive comparator output nodes, connecting control terminals of transistors M1, M2 are connected together and to a first cur
the output transistors to respective comparator output nodes, rent source 19 supplying a first bias current IB1. Second
storing control Voltages existing between each control termi terminals (herein drain terminals) of input transistors M1, M2
nal of the output transistors and an opposite output node, and 30 are connected to a respective output 13, 14 of the first stage
the evaluating step comprising reciprocally disconnecting the and to first terminals (herein drain terminals) of a pair of load
first stage and the second stage, disconnecting the control transistors M3, M4, herein of the PMOS type. Second termi
terminals of the output transistors from the respective output nals (herein source terminals) of load transistors M3, M4 are
nodes, and detecting the output signal on the comparator connected to a supply voltage VDD. Capacitors C1 and C2
output nodes.
35 are connected between drain and gate terminals of a respec
tive load transistor M3, M4; switches S5 and S6 are connected
BRIEF DESCRIPTION OF THE DRAWINGS between the gate and source terminals of a respective load
transistor M3, M4.
The outputs 13, 14 of the first stage are connectable to
For a better understanding of the present invention, a pre 40 inputs 21 and 22 of second stage 20 through respective
ferred embodiment thereof will now be disclosed by mere switches S7 and S8. Inputs 21 and 22 of second stage 20 (also
way of non-limitative example and with reference to the forming outputs of comparator 100) are connected to first
accompanying drawings, wherein: terminals (herein drain terminals) of a pair of bias transistors
FIG. 1 is a circuit diagram of a first known solution; M5, M6, herein of the NMOS type. Second terminals (herein
FIG. 2 is a circuit diagram of a second known solution; 45 source terminals) of bias transistors M5, M6 are connected
FIG. 3 is a circuit diagram of a third known solution; together and to a second current source 29 Supplying a second
FIG. 4 is a circuit diagram of an embodiment of the present bias current IB2. Inputs 21 and 22 of second stage 20 are also
comparator, connected to first terminals (herein drain terminals) of a pair
FIG. 5 shows the plot of the control signals of the com of output transistors M7, M8, herein of the PMOS type.
parator of FIG. 4; 50 Second terminals (herein source terminals) of output transis
FIGS. 6-8 show equivalent circuit diagrams of the com tors M7, M8 are connected to a supply voltage VDD. Capaci
parator of FIG. 4, in three different operative steps; tors C3 and C4 are connected between the drain terminal of a
FIG. 9 shows a simulation referring to the comparator of respective output transistor M7, M8 and the gate terminal of
FIG. 4; the other output transistor M8, M7; switches S9 and S10 are
FIG. 10 is block diagram of an ADCSAR converter using 55 connected between the gate and drain terminals of a respec
the comparator of FIG. 4; and tive output transistor M7, M8.
FIG.11 shows the output signal of the converter of FIG. 10. Switches S1-S10 receive control signals resulting from
combinations of two synchronism signals AZ and R (shown
DETAILED DESCRIPTION in FIG. 5), so as to obtain a sequence of autoZeroing step AZ.
60 tracking step T and evaluating step E. For instance, Switches
FIG. 4 shows a comparator 100 comprising two stages 10, S3-S6 receive autoZero signal AZ., switches S1, S2 receive
20 which are cascade connected and controlled by two syn inverted autoZero signal AZ; switches S7 and S8 receive reset
chronization signals (autoZero signal AZ and reset signal R) signal Rand switches S9 and S10 receive a control signal CK,
So as to operate according to three steps, including a autoZ which is the combination of autoZero signal AZ and reset
eroing step, a tracking step and an evaluating step (unbalanc 65 signal R and is such as to maintain them closed during the
ing and latching). The autoZeroing step may be performed autoZeroing and tracking steps and open during the evaluating
once at the beginning of a series of comparison operations, step.
 US 8,248,108 B2
5 6
The operation of comparator 100 of FIG. 4 will now be Thereafter, comparator 100 goes back to the tracking step.
disclosed with reference to FIGS. 6-8, showing the equivalent The first stage therefore generates a new value of signal
circuit of comparator 100 respectively in the autoZeroing, current it flowing towards/from second stage 20, analo
tracking and evaluating steps. gously to what disclosed above. A Subsequent evaluating step
AutoZeroing Step therefore leads to the generation of a new output.
In this step, switches S1, S2, S7, S8 are open and switches Resampling the offset of the whole comparator 100 by
S3, S4, S5, S6, S9, S10 are closed. Accordingly, the gate shorting the inputs of the common mode is not required after
terminals of input transistors M1, M2 of first stage 10 are each single comparison operation (tracking and evaluating)
connected to common mode DC voltage VCM; outputs 13 with the shown circuit. Indeed, the overall offset of compara
and 14 of first stage 10 are disconnected from second stage 10
tor 100 depends on the sum of the offset contributions of the
20; load transistors M3 and M4 are in a transdiode configu first and second stages. The offset of first stage 10 is stored
ration and second stage 20 is in a reset state. during the initial autoZeroing step and maintained for the
In this configuration, shown in FIG. 6, load transistors M3 whole duration of the subsequent N comparisons. The infor
and M4 are respectively biased with the current set by input
transistor M1, M2 connected thereto, equal to IB+ioff1 and 15 mation on the offset of second stage 20, although lost at each
IB-ioffl. During this step, capacitors C1 and C2 store volt comparison, is recovered during the Subsequent tracking step,
ages VGS of load transistors M3 and M4 corresponding to without requiring additional steps.
these currents. Thereby, a series of comparisons may be performed by
Second stage 20 is maintained in a reset state, with a alternating the tracking and evaluating steps, as shown in FIG.
disabled positive feedback, due to switches S9 and S10 clos 9, relating to the simulation of a transient wherein input 11 of
ing. In this condition, capacitors C3 and C4 are equivalent to comparator 100 receives a ramp signal IN1, while input 12 is
a single capacitance Ceq C3+C4 connected between the gate maintained at a constant Voltage, for instance the common
terminals of output transistors M7 and M8. mode voltage (IN2=1.650 V). As may be noted, the autoZero
Tracking Step ing step is performed only initially and reset signal R deter
At the beginning of this step, switches S3 and S4 are 25 mines alternating of the tracking and evaluating steps (and
opened and switches S1 and S2 are closed. Furthermore, more precisely, the tracking step occurs when reset signal Ris
switches S5 and S6 are opened and switches S7 and S8 are high and the evaluating step occurs when signal R is low).
closed, connecting first stage 10 to second stage 20 through a The comparator disclosed herein has several advantages.
low impedance path; switches S9 and S10 remain closed, In particular, the circuit is very simple, comprises few
maintaining output transistors M7, M8 in a transdiode con 30 auxiliary components, so that its implementation requires a
figuration. Comparator 100 is therefore in the configuration rather limited area.
shown in FIG. 7. The cancellation of the offset also requires only two control
Thereby, input signals IN1 and IN2 are applied to input signals and only one additional step (autoZeroing step).
transistors M1, M2 which respectively conduct currents Indeed, the tracking step requires no additional times with
IB+ioffl-i, and IB-ioffl+i Since capacitors C1 and C2 35 respect to other kinds of comparators, which in any case
hold the gate-source voltage of load transistors M3, M4 con comprise a resetting step, corresponding to the tracking step
stant, the latter do not modify the current flowing there in the present comparator.
through and the signal currents -i, and +i flow through the The solution shown is also compatible with the use of
low impedance path between first and second stage 10, 20. low-gain preamplification stages upstream of the comparator,
Accordingly, signal current -i, and +i flows in output 40 as the autoZeroing step is performed only once, as explained
transistors M7, M8, as well as bias current IB2+ioff2 due to above.
second generator 29. The currents of output transistors M7. Furthermore, the circuit allows a reduction in the input
M8 are therefore equal to IB2+ioff2+i and IB2-ioff2-i. noise during the comparison due to Switching of the outputs,
respectively. the so-called “kick-back'. Indeed, during switching of the
In this step, capacitors C3 and C4 in parallel to one another 45 outputs, second stage 20 is electrically disconnected from
store the Voltage existing between outputs 21 and 22 of com first stage 10, by virtue of the opening of switches S7 and S8.
parator 100, dependent on offset currents itioff2 of second Comparator 100 may be used for providing an analog
stage 20. digital converter ADC SAR, as shown in FIGS. 10 and 11.
Evaluating Step Namely, digital analog converter DAC samples input signal
At the beginning of this step, switches S7, S8, S9 and S10 50 IN on its input capacitances; furthermore it also receives a
are opened, while switches S1-S6 remain in the previous level of reference voltage V and the output of the SAR
condition, as shown in FIG. 8, relating to the time at which control logic unit providing, at each comparison, an output
switches S7 and S8 are opened. In this condition, second stage bit. The DAC converter therefore subtracts input signal IN
20 is disconnected from first stage 10. Immediately after from a reference signal corresponding to the bits generated by
switching switches S7-S10, signal current i, of first stage 10 55 the SAR control logic unit (V, in FIG. 11). Initially, the
flows towards parasitic capacitances associated to nodes 13 output bit is set to 1 and the DAC converter subtracts input
and 14, while the currents flowing through output transistors signal IN from V/2. The result of the Subtraction is com
M7, M8 remain unaltered with respect to the previous step, as pared in comparator 100 with common mode Voltage V
capacitors C3 and C4 hold the Voltages constant on their gate and the output signal of comparator 100 is supplied to the
terminals. As bias transistors M5 and M6 receive the common 60 SAR control logic unit which generates the most significant
mode DC voltage VCM on the gate terminals thereof and bit (in the example of FIG. 11, MSB-bit3=0). Accordingly, in
therefore currents IB2+ioff2 and IB2-ioff2 continue to the Subsequent comparison cycle V, is equal to V/4 and
respectively pass therethrough, signal currenti starts to flow the subsequent bit generated by the SAR control logic unit is
in capacitors C3 and C4, modifying the Voltage drop across equal to “1” (in FIG. 11, bit2). The comparison cycles are
them and triggering a positive feedback that allows the 65 repeated several times, on the basis of the desired discretiza
Switching of outputs 21, 22. This Switching develops accord tion level. In FIG. 10, signal SOC is the conversion activation
ing to a direction exclusively depending on signal current i. signal and signal EOC is the conversion end signal.
 US 8,248,108 B2
7 8
The use of comparator 100 of FIG. 4 in ADC SAR con first stage is disconnected from the second stage and the
verter 200 of FIG. 10 is especially advantageous, as the entire memory elements receive said current signal and Switch said
operation of conversion requires several Subsequent compar first and second output nodes according to said current signal.
ing steps, without the need to resample the offset. Namely, in 3. The comparator according to claim 1, wherein the first
this case, the autoZeroing step may be performed only before 5 and the second memory elements are capacitors.
each conversion operation and the Subsequent comparing 4. The comparator according to claim 1, wherein the first
steps for the generation in a sequence of output bits include stage comprises first and second input transistors and first and
only one sequence of tracking and evaluating steps. Further second load transistors interposed between the reference
more, during the tracking step, the DAC converter develops potential line and an input bias current Source, said first and
its output state, so that the tracking step requires no additional 10 second input transistors being connected to said first and
times in the overall process. second load transistors at respective converter output nodes.
Comparator 100 may also be used in various application 5. The comparator according to claim 4, further comprising
fields, such as for instance the automotive, the consumer a third and a fourth memory element interposed between the
electronics or the sigma-delta converter field. control terminal of the first and, respectively, of the second
It is finally apparent that modifications and variants can be 15 load transistor and the reference potential line.
made to the comparator disclosed and illustrated herein with 6. The comparator according to claim 5, wherein the first
out departing from the scope of protection of the present stage further comprises:
invention, as defined in the appended claims. an input circuit connected to said input transistors and
For instance, switches S9 and S10 connected to output configured so as to supply a reference signal in an autoZ
transistors M7 and M8 could be directly controlled by the eroing step and said input signal in a comparing step:
reset signal and therefore be opened during the autoZeroing a first and a second autoZero Switch interposed between a
step, as second stage 20 is in any case decoupled from first control terminal of a respective load transistor and a
stage 10. respective converter output node and configured so as to
Moreover, the components can be replaced by other receive an autoZero signal so that, in the autoZeroing
equivalent elements, for example bipolar transistors and/or of 25 step, the load transistors are transdiode-connected and
different type. the third and fourth memory elements store a signal
Having thus described at least one illustrative embodiment correlated to an offset of the first stage and, in the com
of the invention, various alterations, modifications, and paring step, the first and the second autoZero Switches
improvements will readily occur to those skilled in the art. are open and the first stage Supplies the current signal to
Such alterations, modifications, and improvements are 30 the converter output nodes.
intended to be within the spirit and scope of the invention. 7. The comparator according to claim 6, wherein the input
Accordingly, the foregoing description is by way of example circuit comprises a first switch interposed between a first
only and is not intended as limiting. The invention is limited comparator input and a control terminal of the first input
only as defined in the following claims and the equivalents transistor, a second Switch interposed between a second com
thereto. 35 parator input and a control terminal of the second input tran
What is claimed is: sistor; a third switch interposed between the control terminal
1. A comparator, comprising a first stage and a second of the first input transistor and a common mode Voltage and a
stage, the first stage being configured so as to receive a Voltage fourth switch interposed between the control terminal of the
input signal and generate a current signal, second input transistor and the common mode Voltage, the
the second stage comprising: 40 first and the second Switch being configured so as to Switch on
a first and a second output transistor connected between a in counterphase with respect to the third and fourth switches.
reference potential line and, respectively, a first and a 8. An ADC SAR converter, comprising the comparator
second comparator output node: according to claim 1.
a pair of bias devices, connected between a respective 9. A method of comparing a Voltage signal Supplied to a
comparator output node and an output bias current 45 comparator comprising a first stage receiving an input signal
Source: and a second stage outputting an output signal, the method
a first memory element, connected between a control ter including a tracking step and an evaluating step, wherein the
minal of the first output transistor and the second com tracking step comprises:
parator output node: generating current signals related to the input signal by the
a second memory element, connected between a control 50 first stage;
terminal of the second output transistor and the first Supplying the current signals to a pair of output transistors
comparator output node; and of the second stage at respective comparator output
bias switches coupled between a control terminal of a nodes, wherein the pair of output transistors are con
respective output transistor and a respective comparator nected between a reference potential line and the respec
output node, wherein 55 tive comparator output nodes;
there is no additional memory element connected between connecting control terminals of the pair of output transis
the control terminal of the first output transistor and the tors to the respective comparator output nodes; and
control terminal of the second output transistor. storing control Voltages existing between each control ter
2. The comparator according to claim 1, wherein the first minal of the pair of output transistors and an opposite
stage comprises a first and a second converter output node, the 60 comparator output node;
comparator further comprising a pair of connection Switches and wherein the evaluating step comprises:
interposed between a respective converter output node and a disconnecting current flow between the first stage and the
respective comparator output node, the connection Switches Second stage;
and the bias Switches being configured so that, in a tracking disconnecting the control terminals of the output transis
step, the first stage is connected to the second stage and the 65 tors from the respective comparator output nodes; and
first and second memory elements store a control Voltage of detecting the output signals on the comparator output
the respective output transistor and, in a evaluating step, the nodes.
 US 8,248,108 B2
9 10
10. The method according to claim 9, further comprising an a first load transistor configured in a first branch of the
autoZeroing step including acts of: second stage, and having its mainterminals connected
disconnecting current flow between the first stage and the between a first potential and a first input node of the at
Second stage; least one input node;
providing a reference signal to a pair of input transistors in a first load transistor Switch configured to couple or
the first stage, the pair of input transistors connected decouple a control terminal of the first load transistor
between respective converter output nodes and a first to the first input node:
current Source: a second load transistor configured in a second branch of
connecting control terminals of a pair of load transistors in the second stage that is parallel to the first branch, and
the first stage to respective converter output nodes; and 10 having its main terminals connected between the first
storing bias Voltages at the control terminals of the pair of potential and a second input node of the at least one
load transistors. input node;
11. The method according to claim 10, wherein the step of a second load transistor Switch configured to couple or
storing bias Voltages further comprises disconnecting each decouple a control terminal of the second load tran
control terminal of the pair of load transistors from the respec
15 sistor to the second input node.
tive converter output nodes. 16. The comparator of claim 15, further comprising:
12. The method according to claim 10, wherein the track a first biasing transistor having its main terminals con
ing step further comprises: nected between the first input node and a current source;
and
Supplying the input signal to control terminals of the input a second biasing transistor having its main terminals con
transistors; and nected between the second input node and the current
maintaining the bias Voltages on the control terminals of Source, wherein
the load transistors.
13. The method according to claim 12, further comprising, the control terminals of the first and second biasing tran
following the autoZeroing step, repeating the tracking step sistors are configured to be coupled to a constant Voltage
25 SOUC.
and the evaluating step several times in a sequence. 17. The comparator of claim 15, further comprising:
14. The method according to claim 10, wherein the refer a first capacitive element connected between a first control
ence signal is applied to each control terminal of the pair of terminal of the first load transistor and the second input
input transistors. node; and
15. A comparator comprising: 30 a second capacitive element connected between a second
a first stage configured to convert an input signal to at least control terminal of the second load transistor and the
one current signal; second input node.
a second stage configured to convert the at least one current 18. The comparator of claim 17, wherein there is no addi
signal into at least one comparator output signal; and tional capacitive element coupling the first control terminal of
at least one coupling Switch for connecting or disconnect 35 the first load transistor to the second control terminal of the
ing at least one signal path configured to carry the at least second load transistor.
one current signal to at least one input node of the second
stage, wherein the second stage comprises: k k k k k