The ARM Architecture

T H E A R C H I T E C T U R E F O R T TMH E D I G I T A L W O R L D
1
Agenda
• Introduction to ARM Ltd
Programmers Model
Instruction Set
ARM Ltd
• Founded in November 1990
• Spun out of Acorn Computers

• Designs the ARM range of RISC processor cores

• Licenses ARM core designs to semiconductor
partners who fabricate and sell to their
customers.
• ARM does not fabricate silicon itself

• Also develop technologies to assist with the

design-in of the ARM architecture
• Software tools, boards, debug hardware,
application software, bus architectures,
peripherals etc
• ARM’s business model centres around the principle
of partnership. At the centre of this are ARM’s
semiconductor partners who design, manufacture
and market ARM-compliant products.
• Having so many partner companies producing silicon
executing the same instruction set is a very important
part of ARM’s strength in the market place.
• However each of the semiconductor partners bring
their own unique strengths to the partnership - each
having their own technologies, applications
knowledge, product focus, culture, geography, and
key customers.
• In addition to partnering with semiconductor
companies, also partner with a large number of
other third parties to ensure that operating systems,
EDA and software development tools, application
software and design services are available for doing
ARM based designs.
“ATAP” stands for ARM Technology Access Program.
Creates a network of independent design service
companies and equips them to deliver ARM-powered
designs. Members get access to ARM technology,
expertise and support. Members sometimes referred to
as “Approved Design Centers”.
Agenda
Introduction to ARM Ltd
• Programmers Model
Instruction Sets
ARM's Flagship Cortex-M Class Processor
The ARM Cortex-M3 processor offers superior efficiency and
flexibility and is specifically developed for response and power-
sensitive applications.

Cortex-M3 differs from previous generations of ARM processors by

defining a number of key peripherals as part of the core:
–interrupt controller
–system timer
–debug and trace hardware (including external interfaces)
Low Power
• 32-bit Cortex-M3 designed for low power operation
• longer battery life, especially critical in portable products
including wireless networking applications
Greater performance efficiency: more work to be done
without increasing the frequency or power requirements
–Implements the new Thumb-2 instruction set architecture
•70% more efficient per MHz than an ARM7TDMI-S
processor executing Thumb instructions
•35% more efficient than the ARM7TDMI-S processor
executing ARM instructions for Dhrystone benchmark

• Small core footprint with integrated power mode support

High Performance
• Cortex-M3 delivering 1.25 DMIPS/MHz
• Separate data and instruction bus
• High code density and performance with Thumb-2 instruction set
• Excellent clock per instruction ratio
• Nested Vectored Interrupt Controller (NVIC) for outstanding interrupt handling
. The NVIC supports up to 240 interrupt vectors with 16 priority levels, which
allows for efficient handling of real-time events and reduces latency.
• Superior math capability
Thumb-2 Instruction Set Architecture (ISA)
Cortex-M3 supports 16- and 32-bit instructions available in the Thumb-2
instruction set. Both can be mixed without extra complexity and without
reducing the Cortex-M3 performance. Hardware divide instructions and a
number of multiply instructions give users high data-crunching throughput.
3-stage Pipeline Core Based on Harvard Architecture
The ARM Cortex-M3 3-stage pipeline includes instruction fetch, instruction
decode and instruction execution. Cortex-M3 also has separate buses for
instructions and data.
Overview of ARM Cortex M3
• The ARM Cortex M3 is a 32-bit microcontroller architecture that is
designed to provide high-performance and low-power embedded
solutions. It is based on the ARMv7-M architecture, which is designed for
microcontroller applications that require a balance of performance,
power efficiency, and ease of use
• It includes a high-performance 32-bit RISC core, a comprehensive set of
peripheral interfaces, and a flexible memory architecture.
• Harvard architecture with separate instruction and data buses. This
reduces bottlenecks common to shared data and instruction buses. This
allows for simultaneous access to both instruction and data memory,
which can improve performance and reduce power consumption.
• It includes a 3-stage pipeline that enables the core to execute
instructions in a single clock cycle.
• The Cortex-M3 supports up to 128KB of flash memory and 32KB of RAM, and
it supports a variety of peripherals, including ADCs, DACs, UARTs, timers, and
more
• M3 includes a Memory Protection Unit (MPU), which allows for memory
protection and isolation. The MPU can be used to define regions of
memory with different access permissions and can help to prevent
unauthorized access or modification of critical data.
• The SCB is another key feature of the Cortex M3 architecture, which
provides system-level control and configuration. The SCB includes registers
for controlling clock and power management, as well as system exceptions
and fault handling.
• supports low power modes, which can be used to reduce power
consumption in battery-powered applications. The Cortex M3 can enter a
sleep mode or a low-power mode when the system is not actively
processing data, which can help to extend battery life.
Data Sizes and Instruction Sets
• The ARM is a 32-bit architecture.

• When used in relation to the ARM:

• Byte means 8 bits
• Halfword means 16 bits (two bytes)
• Word means 32 bits (four bytes)

• Most ARM’s implement two instruction sets

• 32-bit ARM Instruction Set
• 16-bit Thumb Instruction Set
Programmer’s model
Operation modes and states
The Cortex-M3 and Cortex-M4 processors have two operation states and two modes.
In addition, the processors can have privileged and unprivileged access levels.
The privileged access level can access all resources in the processor, while unprivileged access
level means some memory regions are inaccessible, and a few operations cannot be used

Operation states and modes

Operation states
• Debug state: When the processor is halted (e.g., by the debugger, or after
hitting a breakpoint), it enters debug state and stops executing instructions.
• Thumb state: If the processor is running program code (Thumb
instructions), it is in the Thumb state.

Operation modes
• Handler mode: When executing an exception handler such as an Interrupt
Service Routine (ISR). When in handler mode, the processor always has
privileged access level.
• Thread mode: When executing normal application code, the processor can
be either in privileged access level or unprivileged access level. This is
controlled by a special register called “CONTROL.”
• Software can switch the processor in privileged Thread mode to
unprivileged Thread mode. However, it cannot switch itself back from
unprivileged to privileged.
• If this is needed, the processor has to use the exception mechanism to
handle the switch.
• The separation of privileged and unprivileged access levels allows system
designers to develop robust embedded systems by providing a mechanism
to safeguard memory accesses to critical regions and by providing a basic
security model.
• Thread mode and Handler mode have very similar programmer’s models.
• Thread mode can switch to using a separate shadowed Stack Pointer (SP).
This allows the stack memory for application tasks to be separated from
the stack used by the OS kernel, thus allowing better system reliability.
By default, the Cortex-M processors start in privileged Thread mode and in
Thumb state.
• The debug state is used for debugging operations only. This state is entered
by a halt request from the debugger, or by debug events generated from
debug components in the processor.
• This state allows the debugger to access or change the processor register
values. The system memory, including peripherals inside and outside the
processor, can be accessed by the debugger in either Thumb state or debug
state
Registers
• The Cortex-M3 and Cortex-M4 processors have a number of registers inside
the processor core to perform data processing and control.
• Most of these registers are grouped in a unit called the register bank. Each
data processing instruction specifies the operation required, the source
register(s), and the destination register(s) if applicable.
 Exceptions and Interrupts

28-12-2017 ARM - 36 22
Next 3 Slides provide a Quick
Summary of the above aspects
• The register bank in the Cortex-M3 and Cortex-M4 processors has 16 registers.
• Thirteen of them are general purpose 32-bit registers, and the other three have special
uses
• Registers R0 to R12 are general purpose registers. The first eight (R0 - R7) are also called
low registers. Due to the limited available space in the instruction set, many 16-bit
instructions can only access the low registers.
• The high registers (R8 - R12) can be used with 32-bit instructions, and a few with 16-bit
instructions, like MOV (move).
• The initial values of R0 to R12 are undefined.
• R13 is the Stack Pointer. It is used for accessing the stack memory via PUSH and POP
operations. Physically there are two different Stack Pointers: the Main Stack Pointer is
the default Stack Pointer. It is selected after reset, or when the processor is in Handler
Mode.
• The other Stack Pointer is called the Process Stack Pointer, The PSP, can only be used in
Thread Mode. The selection of Stack Pointer is determined by a special register called
CONTROL
• Both MSP and PSP are 32-bit, but the lowest two bits of the Stack Pointers (either MSP or
PSP) are always zero, and writes to these two bits are ignored.
• Only one stack pointer is active at a time. In a high-reliability operating system, we could activate
the PSP for user software and the MSP for operating system software. This way the user program
could crash without disturbing the operating system.
• In ARM Cortex-M processors, PUSH and POP are always 32-bit, and the addresses of the
transfers in stack operations must be aligned to 32-bit word boundaries.
• R14 is also called the Link Register (LR) and is used for holding the return address when
calling a function or subroutine. At the end of the function or subroutine, the program
control can return to the calling program and resume by loading the value of LR into the
Program Counter (PC). When a function or subroutine call is made, the value of LR is
updated automatically. If a function needs to call another function or subroutine, it needs
to save the value of LR in the stack first. Otherwise, the current value in LR will be lost
when the function call is made.
• R15 is the Program Counter (PC). It is readable and writeable: a read returns the current
instruction address plus 4 (this is due to the pipeline nature of the design, and
compatibility requirement with the ARM7TDMI processor). Writing to PC (e.g., using data
transfer/processing instructions) causes a branch operation.
The Cortex-M4 processor has an optional floating point unit. This provides
additional registers for floating point data processing, as well as a Floating
Point Status and Control Register (FPSCR)

CONTROL register
The CONTROL register defines:
• The selection of stack pointer (Main Stack Point/Process Stack Pointer)
• Access level in Thread mode (Privileged/Unprivileged)
In addition, for Cortex-M4 processor with a floating point unit, one bit of the
CONTROL register indicates if the current context (currently executed code)
uses the floating point unit or not.
The CONTROL register can only be modified in the privileged access level and
can be read in both privileged and unprivileged access levels
ARM-M3
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ARM-M3
ARM-M3
ARM-M3
ARM-M3
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ARM-M3
ARM-M3
ARM-M3
ARM-M3
Examples (Slides 52 to 67)
DATA PROCESSING INSTRUCTIONS
DATA PROCESSING INSTRUCTIONS
DATA PROCESSING INSTRUCTIONS

Summary
DATA PROCESSING INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
CONTROL FLOW INSTRUCTIONS
CONTROL FLOW INSTRUCTIONS
CONTROL FLOW INSTRUCTIONS
CONTROL FLOW INSTRUCTIONS
CONTROL FLOW INSTRUCTIONS
CONTROL FLOW INSTRUCTIONS
Memory system
Memory system features
The Cortex-M3 and Cortex-M4 processors have the following memory system features:
• 4GB linear address space e With 32-bit addressing, the ARM processors can access up
to 4GB of memory space. While many embedded systems do not need more than 1MB
of memory, the 32-bit addressing capability ensures future upgrade and expansion
possibilities. The Cortex-M3 and Cortex-M4 processors provide 32-bit buses using a
generic bus protocol called AHB LITE. The bus allows connections to 32/16/8-bit
memory devices with suitable memory interface controllers.
• Architecturally defined memory map - The 4GB memory space is divided into a
number of regions for various predefined memory and peripheral uses. This allows the
processor design to be optimized for performance. For example, the Cortex-M3 and
Cortex-M4 processors have multiple bus interfaces to allow simultaneous access from
the CODE region for program code and data operations to SRAM or peripheral regions.
• Support for little endian and big endian memory systems - The Cortex-M4 and Cortex-
M4 processors can work with either little endian or big endian memory systems. In
practice, a microcontroller product is normally designed with just one endian
configuration.
Bit band accesses (optional) -When the bit-band feature is included
(determined by microcontroller/System-on-Chip vendors), two 1MB regions in
the memory map are bit addressable via two bit-band regions. This allows
atomic access to individual bits in SRAM or peripheral address space.
• Write buffer - When a write transfer to a bufferable memory region will take
multiple cycles, the transfer can be buffered by the internal write buffer in the
Cortex-M3 or Cortex-M4 processor so that the processor can continue to
execute the next instruction, if possible. This allows higher program execution
speed.
• Memory Protection Unit (Optional) - The MPU is a programmable unit which
defines access permissions for various memory regions. The MPU in the
Cortex- M3 and Cortex-M4 processor supports eight programmable regions,
and can be used with an embedded OS to provide a robust system.
● Unaligned transfer support - All processors supporting ARMv7-M
architecture (including Cortex-M3 and Cortex-M4 processors) support
unaligned data transfers.
Memory map
The 4GB address space of the Cortex-M processors is partitioned into a number of memory
regions
The partitioning is based on typical usages so that different areas are designed to be used
primarily for:
• Program code accesses (e.g., CODE region)
• Data accesses (e.g., SRAM region)
• Peripherals (e.g., Peripheral region)
• Processor’s internal control and debug components (e.g., Private Peripheral Bus)
● The architecture also allows high flexibility to allow memory regions to be used for
other purposes. For example, programs can be executed from the CODE as well as the
SRAM region, and a microcontroller can also integrate SRAM blocks in CODE region
● The memory map arrangement is consistent between all of the Cortex-M processors.
● For example, the PPB address space hosts the registers for the Nested Vectored
Interrupt Controller (NVIC), processor’s configuration registers, as well as registers for
debug components. This is the same across all Cortex-M devices. This makes it easier to
port software from one Cortex-M device to another, and allows better software
reusability. It also makes it easier for tool vendors, as the debug control for the Cortex-
Code 0x00000000 to 0x1FFFFFFF
A 512MB memory space primarily for program code, including the default vector table that is a part of the
program memory. This region also allow data accesses.
SRAM 0x20000000 to 0x3FFFFFFF The SRAM region is located in the next 512MB of memory space. It is
primarily for connecting SRAM, mostly on-chip SRAM, but there is no limitation of exact memory type. The first
1MB of the SRAM region is bit addressable if the optional bit-band feature is included. You can also execute
program code from this region.
Peripherals 0x40000000 to 0x5FFFFFFF The Peripheral memory region also has the size of 512MB, and is use
mostly for on-chip peripherals. Similar to SRAM region, the first 1MB of the peripheral region is bit addressable if
the optional bit-band feature is included.
RAM 0x60000000 to 0x9FFFFFFF The RAM region contains two slots of 512MB memory space (total 1GB) for
other RAM such as off-chip memories. The RAM region can be used for program code as well as data.
Devices 0xA0000000 to 0xDFFFFFFF The Device region contains two slots of 512MB memory space (total
1GB) for other peripherals such as off-chip peripherals.
System 0xE0000000 to 0xFFFFFFFF The System region contains several parts:
Internal Private Peripheral Bus (PPB), 0xE0040000 to 0xE00FFFFF: The internal Private Peripheral Bus
(PPB) is used to access system components such as the NVIC, SysTick, MPU, as well as debug components
inside the Cortex-M3/M4 processors. In most cases this memory space can only be accessed by program code
running in privileged state.
External Private Peripheral Bus (PPB), 0xE0040000 to 0xE00FFFFF An addition PPB region is available for
additional optional debug components and so allow silicon vendors to add their own debug or vendorspecific
components. This memory space can only be accessed by program code running in privileged state. Note that
the base address of debug components on this bus can potentially be changed by silicon designers.
Vendor-specific area, 0xE0100000 to 0xFFFFFFFF The remaining memory space is reserved for vendor-
The Cortex-M3 Memory Map
The Memory Map
The Cortex-M3 has a predefined memory map. This allows the built-in
peripherals, such as the interrupt controller and the debug components,
to be accessed by simple memory access instructions.
The predefined memory map also allows the Cortex-M3 processor to be
highly optimized for speed and ease of integration in system-on-a-chip
(SoC) designs.
Overall, the 4 GB memory space can be divided into ranges as shown in
Figure .
The Cortex-M3 design has an internal bus infrastructure optimized for this
memory usage. In addition, the design allows these regions to be used
differently.
For example, data memory can still be put into the CODE region, and
program code can be executed from an external Random Access Memory
(RAM) region
Multiple bus interface for different memory regions
 Connecting the processor to memory and peripherals

● The Cortex-M processors provide generic bus interfaces based on AMBA

(Advanced Microcontroller Bus Architecture). The AMBA specification supports
several bus protocols. I
● n the Cortex-M3 and Cortex-M4 processors, the AHB (AMBA High-performance
Bus) Lite protocol is used for the main bus interfaces, and the APB protocol is
used for the Private Peripheral Bus (PPB), which is mainly used for debug
components.
● Additional bus segments based on APB can be added onto the system bus by
using additional bus bridge components. In order to provide better performance,
the CODE memory region has separated the bus interfaces from the system bus
● In a simple microcontroller design, typically the program memory is connected to
the I-CODE and D-CODE bus, and the SRAM and peripherals are connected to
the system bus
● Each bus to be operated at different speeds for best power optimization
● Peripheral interfaces are usually based on the APB protocol.
● For high performance peripherals, AHB Lite could be used instead for higher
bandwidth and operation speed.
● Private Peripheral Bus (PPB) is not used for normal peripherals. This is because:
• PPB is privileged access only
● • Only 32-bit accesses are allowed
● • PPB write accesses need more clock cycles as there is no write buffer
(Strongly Ordered device accesses;
● • Peripherals in PPB cannot make use of the bit-band feature
● In addition, there are other restrictions on PPB usage: • Little endian only, even if
the processor is configured to be big endian.
● • It is accessible by the processor and debugger, but no other bus master (e.g., in
a multiprocessor environment).
● Two bus interfaces (I-CODE and D-CODE) are provided for the accesses to
program memory
 BUS INTERFACES ON THE CORTEX-M3
The I-Code Bus: The I-Code bus is a 32-bit bus based on the AHB-Lite bus protocol for
instruction fetches in memory regions from 0x00000000 to 0x1FFFFFFF. Instruction fetches
are performed in word size, even for 16-bit Thumb instructions. Therefore, during
execution, the CPU core could fetch up to two Thumb instructions at a time.
The D-Code Bus: The D-Code bus is a 32-bit bus based on the AHB-Lite bus protocol; it is
used for data access in memory regions from 0x00000000 to 0x1FFFFFFF. Although the
Cortex-M3 processor supports unaligned transfers, you won‘t get any unaligned transfer on
this bus, because the bus interface on the processor core converts the unaligned transfers
into aligned transfers for you. Therefore, devices (such as memory) that attach to this bus
need only support AHB-Lite (AMBA 2.0) aligned transfers.
The System Bus : The system bus is a 32-bit bus based on the AHB-Lite bus protocol; it is
used for instruction fetch and data access in memory regions from 0x20000000 to
0xDFFFFFFF and 0xE0100000 to 0xFFFFFFFF. Similar to the D-Code bus, all the transfers on
the system bus are aligned.
Power control
The LPC17xx support a variety of power control features.
• There are four special modes of processor power reduction: Sleep mode, Deep-
sleep mode, Power-down mode, and Deep power-down mode.
• The CPU clock rate may also be controlled as needed by changing clock sources,
reconfiguring PLL values, and/or altering the CPU clock divider value. This allows
a trade-off of power versus processing speed based on application
requirements.
• In addition, Peripheral Power Control allows shutting down the clocks to
individual on-chip peripherals, allowing fine tuning of power consumption by
eliminating all dynamic power use in any peripherals that are not required for
the application.
• Each of the peripherals has its own clock divider which provides even better
NESTED VECTORED INTERRUPT CONTROLLER AND INTERRUPT CONTROL:
• the Nested Vectored Interrupt Controller (NVIC)is an integrated part of the
Cortex -M3 processor. It is closely linked to the Cortex-M3 CPU core logic.
• Its control registers are accessible as memory-mapped devices.
• Besides control registers and control logic for interrupt processing, the NVIC
unit also contains control registers for the SYSTICK Timer, and debugging
controls.
• The NVIC supports 1–240 external interrupt inputs (commonly known as
interrupt request [IRQs]). The exact number of supported interrupts is
determined by the chip manufacturers when they develop their Cortex-M3
chips.
• In addition, the NVIC also has a Non-maskable Interrupt (NMI) input. The
actual function of the NMI is also decided by the chip manufacturer.
• Most of the interrupt control/status registers are accessible only in privileged
mode, except the Software Trigger Interrupt register (STIR), which can be set
INTERRUPT LATENCY:
• The term interrupt latency refers to the delay from the start of the
interrupt request to the start of interrupt handler execution.
• In the Cortex-M3 processor, if the memory system has zero latency, and
provided that the bus system design allows vector fetch and stacking to
happen at the same time, the interrupt latency can be as low as 12 cycles.
• This includes stacking the registers, vector fetch, and fetching instructions
for the interrupt handler.
• For tail-chaining interrupts, since there is no need to carry out stacking
operations, the latency of switching from one exception handler to
another exception handler can be as low as six cycles.
• When the processor is executing a multicycle instruction, such as divide,
the instruction could be abandoned and restarted after the interrupt
handler completes.
Stack memory
● The Cortex-M processors need stack memory to operate and have stack
pointers (R13).
● Stack is a kind of memory usage mechanism that allows a portion of
memory to be used as Last-In-First-Out data storage buffer. ARM
processors use the main system memory for stack memory operations, and
have the PUSH instruction to store data in stack and the POP instruction to
retrieve data from stack.
● The current selected stack pointer is automatically adjusted for each PUSH
and POP operation.
● Stack can be used for: • Temporary storage of original data when a function
being executed needs to use registers (in the register bank) for data
processing. The values can be restored at the end of the function so the
program that called the function will not lose its data. • Passing of
information to functions or subroutines. • For storing local variables. • To
hold processor status and register values in the case of exceptions such as
an interrupt.
● The Cortex-M processors use a stack memory model called “full-descending
stack.”
● When the processor is started, the SP is set to the end of the memory space
reserved for stack memory.
● For each PUSH operation, the processor first decrements the SP, then stores
the value in the memory location pointed by SP.
● During operations, the SP points to the memory location where the last data was
pushed to the stack
● In a POP operation, the value of the memory location pointed by SP is read, and
then the value of SP is incremented automatically.
● The most common uses for PUSH and POP instructions are to save contents of
register banks when a function/subroutine call is made
● Physically there are two stack pointers in the Cortex-M processors.
● They are the:
• Main Stack Pointer (MSP) - This is the default stack pointer used after
reset, and is used for all exception handlers.
• Process Stack Pointer (PSP) - This is an alternate stack point that can
only be used in Thread mode. It is usually used for application tasks in
embedded systems running an embedded OS.
● The selection between MSP and PSP can be controlled by the value of
SPSEL in bit 1 of the CONTROL register. If this bit is 0, Thread mode uses
MSP for the stack operation. Otherwise, Thread mode uses the PSP.
● During exception return from Handler mode to Thread mode, the selection
can be controlled by the value of EXC_RETURN (exception return) value. In
that case the value of SPSEL will be updated by the processor hardware
accordingly
Exceptions and interrupts
What are exceptions?
● Exceptions are events that cause changes to program flow. When one
happens, the processor suspends the current executing task and executes a
part of the program called the exception handler. After the execution of the
exception handler is completed, the processor then resumes normal program
execution.
● In the ARM architecture, interrupts are one type of exception. Interrupts are
usually generated from peripheral or external inputs, and in some cases they
can be triggered by software.
● The exception handlers for interrupts are also referred to as Interrupt Service
Routines (ISR). In Cortex-M processors, there are a number of exception
sources: Exceptions are processed by the NVIC.
● The NVIC block suspends the calculation processing that is running
on the main core, and controls switching to prioritized processing. It
supports the system exception and interrupt occurrence.
● The NVIC can handle a number of Interrupt Requests (IRQs) and a Non-Maskable
Interrupt (NMI) request. Usually IRQs are generated by on-chip peripherals or from
external interrupt inputs though I/O ports.
● The NMI could be used by a watchdog timer or brownout detector (a voltage
monitoring unit that warns the processor when the supply voltage drops below a
certain level).
● Inside the processor there is also a timer called SysTick, which can generate a
periodic timer interrupt request, which can be used by embedded OSs for timekeeping
● The processor itself is also a source of exception events. These could be fault events
that indicate system error conditions, or exceptions generated by software to support
embedded OS operations
● Exception numbers 1 to 15 are classified as system exceptions, and exceptions 16
and above are for interrupts. The design of the NVIC in the Cortex-M3 and Cortex-M4
processors can support up to 240 interrupt inputs

Various exception sources

Exception Types
● The Cortex -M3 provides a feature-packed exception architecture that
supports a number of system exceptions and external interrupts.
● Exceptions are numbered 1–15 for system exceptions and 16 and above for
external interrupt inputs.
● Most of the exceptions have programmable priority, and a few have fixed
priority.
● Cortex-M3 chips can have different numbers of external interrupt inputs
(from 1 to 240) and different numbers of priority levels.

● The value of the current running exception is indicated by the special register
Interrupt Program Status register (IPSR), or from the Nested Vectored
Interrupt Controllers (NVICs) Interrupt Control State register (the
VECTACTIVE field)
● When an enabled exception occurs but cannot be carried out immediately (for
instance, if a higher-priority interrupt service routine is running or if the interrupt
mask register is set), it will be pended (except for some fault exceptions1 ).
● This means that a register (pending status) will hold the exception request
until the exception can be carried out.
● This is different from traditional ARM processors.
● Previously, the devices that generate interrupts, such as interrupt request
(IRQ)/fast interrupt request (FIQ), must hold the request until they are served.
 Definitions of Priority

● In the Cortex-M3, whether and when an exception can be carried out can be
affected by the priority of the exception.
● A higher-priority (smaller number in priority level) exception can preempt a
lower priority (larger number in priority level) exception; this is the nested
exception / interrupt scenario.
● Some of the exceptions (reset, NMI, and hard fault) have fixed priority levels.
They are negative numbers to indicate that they are of higher priority than
other exceptions.
● Other exceptions have programmable priority levels.
● The Cortex-M3 supports three fixed highest-priority levels and up to 256
levels of programmable priority (a maximum of 128 levels of preemption)
● If the priority level configuration registers are 8 bits wide, why there are only
128 preemption levels?
● This is because the 8-bit register is further divided into two parts: preempt
priority and subpriority.
● Using a configuration register in the NVIC called Priority Group (a part of the
Application Interrupt and Reset Control register in the NVIC,), the priority-
level configuration registers for each exception with programmable priority
levels is divided into two halves.
● The upper half (left bits) is the preempt priority, and the lower half (right bits)
is the subpriority
● The preempt priority level defines whether an interrupt can take place when
the processor is already running another interrupt handler.
● The subpriority level value is used only when two exceptions with the same
preempt priority level occurred at the same time. In this case, the exception
with higher subpriority (lower value) will be handled first.
Nested vectored interrupt controller (NVIC)
The NVIC is a part of the Cortex-M processor.
It is programmable and its registers are located in the System Control Space (SCS) of
the memory map .
The NVIC handles the exceptions and interrupt configurations, prioritization, and
interrupt masking.
The NVIC has the following features:
• Flexible exception and interrupt management
• Nested exception/interrupt support
• Vectored exception/interrupt entry
• Interrupt masking
Flexible exception and interrupt management
● Each interrupt can be enabled or disabled and can have its pending status set or
cleared by software.
● The NVIC can handle various types of interrupt sources:
• Pulsed interrupt request - the interrupt request is at least one clock cycle long.
When the NVIC receives a pulse at its interrupt input, the pending status is set and
held until the interrupt gets serviced.
• Level triggered interrupt request the interrupt source holds the request high until
the interrupt is serviced.
● The signal level at the NVIC input is active high.
● However, the actual external interrupt input on the microcontroller could be
designed differently and is converted to an active high signal level by on-chip
logic.
● Nested exception/interrupt support- Each exception has a priority level.
● Some exceptions, such as interrupts, have programmable priority levels and
some others have a fixed priority level.
● When an exception occurs, the NVIC will compare the priority level of this
exception to the current level. If the new exception has a higher priority, the
current running task will be suspended.
● Some of the registers will be stored on the stack memory, and the processor will
start executing the exception handler of the new exception. This process is
called “preemption.” When the higher priority exception handler is complete, it is
terminated with an exception return operation and the processor automatically
restores the registers from stack and resumes the task that was running
previously. This mechanism allows nesting of exception services without any
Vectored exception/interrupt entry
● When an exception occurs, the processor will need to locate the starting point of
the corresponding exception handler.
● Traditionally, in ARM processors such as the ARM7TDMI, software handles this
step. The Cortex-M processors automatically locate the starting point of the
exception handler from a vector table in the memory.
● As a result, the delays from the start of the exception to the execution of the
exception handlers are reduced.
● Interrupt masking
● The NVIC in the Cortex-M3 and Cortex-M4 processors provide several interrupt
masking registers such as the PRIMASK special register.
● Using the PRIMASK register you can disable all exceptions, excluding HardFault
and NMI.
● This masking is useful for operations that should not be interrupted, like time
critical control tasks or real-time multimedia codecs.
Cortex-M3 Processor Applications

• Low-cost microcontrollers: The Cortex-M3 processor is ideally suited for low-cost

microcontrollers, which are commonly used in consumer products, from toys to electrical
appliances. Its lower power, high performance, and ease-of-use advantages enable
embedded developers to migrate to 32-bit systems and develop products with the ARM
architecture.
• Automotive: Another ideal application for the Cortex-M3 processor is in the automotive
industry. The Cortex-M3 processor has very high-performance efficiency and low interrupt
latency, allowing it to be used in real-time systems. The Cortex-M3 processor supports up
to 240 external vectored interrupts, with a built-in interrupt controller with nested
interrupt supports and an optional MPU, making it ideal for highly integrated and cost-
sensitive automotive applications.
• Data communications: The processor’s low power and high efficiency, coupled with
instructions in Thumb-2 for bit-field manipulation, make the Cortex-M3 ideal for many
communications applications, such as Bluetooth and ZigBee.
• Industrial control: In industrial control applications, simplicity, fast response, and
reliability are key factors. Again, the Cortex-M3 processor’s interrupt feature, low
interrupt latency, and enhanced fault-handling features make it a strong candidate in
this area.
• Consumer products: In many consumer products, a high-performance microprocessor
(or several of them) is used. The Cortex-M3 processor, being a small processor, is highly
efficient and low in power and supports an MPU enabling complex software to execute
while providing robust memory protection.
Instruction Set Development
Two different instruction sets are supported on the ARM processor: the
ARM instructions that are 32 bits and Thumb instructions that are 16 bits.
During program execution, the processor can be dynamically switched
between the ARM state and the Thumb state to use either one of the
instruction sets.
The Thumb instruction set provides only a subset of the ARM instructions,
but it can provide higher code density. It is useful for products with tight
memory requirements.
The Thumb-2 Technology and Instruction Set Architecture
The Thumb-2 technology extended the Thumb Instruction Set Architecture
(ISA) into a highly efficient and powerful instruction set that delivers
significant benefits in terms of ease of use, code size, and performance
• The extended instruction set in Thumb-2 is a superset of the previous 16-bit Thumb
instruction set, with additional 16-bit instructions alongside 32-bit instructions.
• It allows more complex operations to be carried out in the Thumb state, thus allowing
higher efficiency by reducing the number of states switching between ARM state and
Thumb state.
• Focused on small memory system devices such as microcontrollers and reducing the size of
the processor, the Cortex-M3 supports only the Thumb-2 instruction set. Instead of using
ARM instructions for some operations, as in traditional ARM processors, it uses the Thumb-
2 instruction set for all operations.
• The Cortex-M3 processor is not backward compatible with traditional
ARM processors.
• With support for both 16-bit and 32-bit instructions in the Thumb-2
instruction set, there is no need to switch the processor between Thumb
state (16-bit instructions) and ARM state (32-bit instructions). For
example, in ARM7 or ARM9 family processors, you might need to switch
to ARM state if you want to carry out complex calculations or a large
number of conditional operations and good performance is needed,
whereas in the Cortex-M3 processor, you can mix 32-bit instructions with
16-bit instructions without switching state, getting high code density and
high performance with no extra complexity.
• The Thumb-2 instruction set is a very important feature of the ARMv7
architecture. Compared with the instructions supported on ARM7 family
processors (ARMv4T architecture), the Cortex-M3 processor instruction
set has a large number of new features.
• For the first time, hardware divide instruction is available on an ARM
processor, and a number of multiply instructions are also available on
the Cortex-M3 processor to improve data-crunching performance.
• The Cortex-M3 processor also supports unaligned data accesses, a
feature previously available only in high-end processors
The Bus Interface
There are several bus interfaces on the Cortex-M3 processor.
They allow the Cortex-M3 to carry instruction fetches and data accesses at
the same time.
The main bus interfaces are as follows:
• Code memory buses
• System bus
• Private peripheral bus
The code memory region access is carried out on the code memory buses,
which physically consist of two buses, one called I-Code and other called D-
Code. These are optimized for instruction fetches for best instruction
execution speed.
The system bus is used to access memory and peripherals. This provides
access to the Static Random Access Memory (SRAM), peripherals, external
RAM, external devices, and part of the system level memory regions.
• The private peripheral bus provides access to a part of the system-level
memory dedicated to private peripherals, such as debugging
components.
The MPU (Memory Protection Unit)
• The Cortex-M3 has an optional MPU.
• This unit allows access rules to be set up for privileged access and user
program access.
• When an access rule is violated, a fault exception is generated, and the
fault exception handler will be able to analyze the problem and correct
it, if possible.
• The MPU can be used in various ways. In common scenarios, the OS
can set up the MPU to protect data use by the OS kernel and other
privileged processes to be protected from untrusted user programs.
• The MPU can also be used to make memory regions read-only, to prevent
accidental erasing of data or to isolate memory regions between different
tasks in a multitasking system.
• Overall, it can help make embedded systems more robust and reliable.
 LPC17xx
•LPC17xx (of NXP) is an ARM Cortex-M3 based microcontroller
•The Cortex-M3 is also the basis for microcontrollers from other
manufacturers including TI, ST, Toshiba, Atmel, etc.
•LPC1768 operates at up to a 100 MHz CPU frequency
•Sophisticated clock system
•Peripherals include:
–up to 512 kB of flash memory, up to 64 kB of data memory
–Ethernet MAC
–a USB interface that can be configured as either Host, Device, or OTG
–8 channel general purpose DMA controller
–4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface
–3 I2C interfaces, 2-input plus 2-output I2S interface
–8 channel 12-bit ADC, 10-bit DAC, motor control PWM
–Quadrature Encoder interface, 4 general purpose timers,
–6-output general purpose PWM
–ultra-low power RTC with separate battery supply
–up to 70 general purpose I/O pins
LPC1768
LPC1768
•LPC1768 microcontrollers are based on the Cortex-M3 processor with a set of
peripherals distributed across three buses – Advanced High-performance Bus
(AHB) and its two Advanced Peripheral Bus (APB) sub-buses APB1 and APB2.
•These peripherals:
–are controlled by the CM3 core with load and store instructions that access memory mapped
registers
–can “interrupt” the core to request attention through peripheral specific interrupt requests
routed through the NVIC
•Data transfers between peripherals and memory can be automated using
DMA
•Labs will cover among others:
–basic peripheral configuration (e.g., lab1 illustrates GPIO General Purpose I/O peripherals)
–how interrupts can be used to build effective software
–how to use DMA to improve performance and allow processing to proceed in parallel with
data transfer
Peripherals are “memory-mapped”
–core interacts with the peripheral hardware by reading and writing peripheral “registers” using
load and store instructions
•The various peripheral registers are documented in the user and reference manuals
–documentation include bit-level definitions of the various registers and info on how interpret
those bits
–actual physical addresses are also found in the reference manuals
•Examples of base addresses for several peripherals
0x40010000 UART1
0x40020000 SPI
0x40028000 GPIO interrupts
0x40034000 ADC
…
•No real need for a programmer to look up all these values as they are defined in the library file
lpc17xx.h as:
LPC_UART1_BASE
LPC_SPI_BASE
LPC_GPIOINT_BASE
LPC_ADC_BASE
Typically, each peripheral has:
•control registers to configure the peripheral
•status registers to determine the current peripheral status
•data registers to read data from and write data to the peripheral

In addition to providing the addresses of the peripherals, lpc17xx.h also

provides C language level structures that can be used to access each
peripheral.
•For example, the SPI and GPIO ports are defined by the following
register structures:
typedef struct
{
__IO uint32_t SPCR;
__I uint32_t SPSR;
__IO uint32_t SPDR;
__IO uint32_t SPCCR;
uint32_t RESERVED0[3];
__IO uint32_t SPINT;
} LPC_SPI_TypeDef;
 Memory
•On-chip flash memory system
–Up to 512 kB of on-chip flash memory
–Flash memory accelerator maximizes performance for use with the two
fast AHB-Lite buses
–Can be used for both code and data storage
•On-chip Static RAM
–Up to 64 kB of on-chip static RAM memory
–Up to 32 kB of SRAM, accessible by the CPU and all three DMA controllers
are on a higher-speed bus
–Devices with more than 32 kB SRAM have two additional 16 kB SRAM
blocks