Science viSion inStitute

electronicS
PreviouS YearS QueStionS
cSir-net/JrF,
net/JrF, Gate, JeSt

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ASSIGNMENT – 1

DIGITAL ELECTRONICS

Q-1. A sign of frequency 10 KHz is being digitized by an A/D converter. A possible sampling time

which can be used is: NET June 2011

(a) 100 µs (b) 40 µs (c) 60 µs (d) 200 µs

Q-2. Consider the digital circuit shown below in which the input C is always high (I).
The truth table for the circuit can be written
A
as
B Z
A B Z
0 0
0 1
C 1 0
(high) 1 1

The entries in the Z column (vertically) are NET June 2011

(a) 1010 (b) 0100 (c) 1111 (d) 1011

Q-3. A counter consists of four fip--flops connected as shown in the figure. NET Dec. 2011

J Q J Q J Q J Q
CLK
   
K Q K Q K Q K Q

If the counter is initialized as A0 A1 A2 A3 = 0110, the state after the next clock pulse is

(a) 1000 (b) 0001 (c) 0011 (d) 1100

Q-4. The output 0, of the given circui

circuit in cases I and II, where NET June 2012

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Case I : A, B = 1; C, D = 0; E, F = 1 and G = 0

Case II : A, B = 0; C, D = 0; E, F = 0 and G = 1 are respectively

A
B

C
D Q
E
F
G

(a) 1, 0 (b) 0, 1 (c) 0, 0 (d) 1, 1

Q-5. The logic circuit shown in the figure below.

HIGH

Implement the Boolean expression

(a) . (b) . (c) (d)

Q-6. Four digital outputs V, P, T and H monitor the speed v, tyre pressure p, temperature t and relative

humidity h of a car. These outputs switch from 0 to 1 when the values of the parameters exceed

85 km/hr, 2 bar, 400C and 50%, respectively. A ligic circuit that is used to switch ON a lamp at

the output E is shown below. NET June 2013

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P
E

Which
ich of the following conditions will switch the lamp ON?

(a) v < 85km/hr, p < 2bar, t > 400C, h > 50%

(b) v < 85km/hr, p < 2bar, t > 400C, h < 50%

(c) v > 85km/hr, p < 2bar, t > 400C, h < 50%

(d) v < 85km/hr, p < 2bar, t < 400C, h > 50%

Q-7. If the analog input to an 8-bit

bit successive approximation ADC is increased from 1.0 V to 2.0 V

then the conversion time will NET June 2013

(a) remain unchanged (b) double

(c) decrease to half its original value (d) increase four times

Q-8. If one of the inputs of a J-K

K flip flop is high and the other is low, then

(a) Oscillate between low and high in race

race-around condition

(b) Toggle and the circuit acts like a T flip flop

(c) Are opposite to the inputs

(d) Follow the inputs and the circuit acts like an R

R-S flip flop

Q-9. A 4-variable
variable switching function is given by ∑ 5,7,8,10,13,15 0,1
1,2 , where d is the

do-not-care-condition.
condition. The minimized form of in sum of products (SOP) form is :

NET Dec. 2013

(a) ̅ ̅ (b) ̅ ̅ (c) ̅ ̅ (d)

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Q-10. For the logic circuit shown in the figure below NET

June 2014

B
x
C

A simplified equivalent circuit is

A
A
(a) B x 
(b) B x
C
C

A A

(c)  x (d)  x
B B

C C

Q-11. For the logic circuit given below, the decimal count sequence and the

modulus
lus of the circuit corresponding to A B C D are NET

June 2015
1

J Flip D
3 bit ring Flop
Clock counter
K
A B C

MSB LSB

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(a) 8 → 4 → 2 → 1 → 9 → 5 (mod 6) (b) 8 → 4 → 2 → 9 → 5 → 3 (mod 6)

(c) 2 → 5 → 9 → 1 → 3 (mod 5) (d) 8 → 5 → 1 → 3 → 7 (mod 5)

Q-12. Which of the following circuits behaves as a controlled inverter? NET

June 2015

(a) Input
Output
Control

Input

(b)
Output

Control

Input

(c)
Output

Control

Input

(d)
Output
Control

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Q-13. If the parameters y and x are related by y = log(x), then the circuit that can

be used to product output voltage V 0 verying linearly with x is

(a) y (b) y
V0 V0

(c) y (d) y
V0 V0

Q-14. The state diagram corresponding to the following circuit is NET

Dec. 2015

x D A

y
>
Flip Flop

00,01,10 00,11
11 00 01,10 01,10

1. 0 1 3. 0 1

01,10,11 00,11

01,11 00,01,10
01,10 00,10 11 11

2. 0 1 4. 0 1

01,11 00,01,10

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Q-15. The state diagram that detects three or more consecutive 1’s in a serial bit

stream is

NET June 2016

0 0 0
Reset 1 Reset 1
S 0/0 S1/0 S0/0 S1/0

0 1
(1) 1 1 (3) 1 1

S 2/1 S2/0 S3/1 S2/0

0 0

0 0

1 0 0
Reset Reset
S 0/0 S1/0 S0/0 S1/0
0 1

0 0 0 0
(2) 1 (2)

S 3/1 S2/0 S3/1 S2/0

1 1

0 1

Q-16. In the schematic figure given below, assume that the propagation delay of

each logic gate is NET

June 2016

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+5V

The propagation delay of the circuit will be maximum when the logic inputs A and B make the

transition

1. (0, 1) → (1, 1) 2. (1, 1) → (0, 1)

3. (0, 0) → (1, 1) 4. (0, 0) → (0, 1)

Q-17. Which of the following circuits implements the Boolean function

, ,

∑ 1,2,4,6 ? NET Dec. 2016

I0 I0
I1 41 I1 41
MUX MUX
(1) I2 (2) I2
I3 S S0 I3 S S0
1 1

A B A B

C I0 0 I0
(3) (4)
I1 41 I1 41
1 MUX F MUX F
I2 I2
I3 S S0 C I3 S S0
1 1

A B A B

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Q-18. In the figure below, X and Y are one bit inputs. The circuit which

corresponds to a one bit comparator is

NET June 2017

X
X<Y
Y

(1) X=Y

X>Y

X
X<Y

(2) X=Y

X>Y
Y

X
X<Y

(3) X=Y

X>Y
Y

X
X=Y

Y
(4) X>Y

X>Y
Y

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Q-19. A 2 × 4 decoder with an enable input can function as a NET

June 2017
1. 4 × 1 multiplexer

2. 1 × 4 demultiplexer

3. 4 × 2 encoder

4. 4 × 2 priority encoder

Q-20. The full scale voltage of an nn-bit Digital-to-Analog

Analog Converter is V. The

resolution that can be achieved in it is NET Dec. 2017

(1) / 2 1 (2) / 2 1 (3) /2 (3) /

Q-21. The circuit below comprises of D

D-flit.
flit. The output is taken from Q3, Q2, Q1

a as shown in the figure. NET

Dec. 2017

LSQ Q0 Q1 Q2 MSQ Q3

D Q D Q D Q D Q

Q
CLR CLR CLR CLR
CLK
RST

The binary number given by the sstring Q3Q2Q1Q0 charge for every clock pulse that is applied to

the CLK input. If the output is initialized at 0000, then the corresponding sequence of decimal

numbers that repeats itself, is

1) 3, 2, 1, 0

2) 1, 3, 7, 14, 12, 8

3) 1, 3, 7, 15, 12, 14, 0

4) 1, 3, 7, 15, 14, 12, 8, 0

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Q-22. RAM and ROM are

GATE 2000
(a) Charge coupled devices use in computers

(b) Computer memories

(c) Logic gates

(d) Binary counters used in computers

Q-23. Draw the electrical circuits for each of the following ****************

source (battery), a detector (lamp), and switch (es).

GATE 2000
(a) AND (b) OR (c) NOT

(d) NAND (e) NOR

Q-24. Which of the following options is true for a two input XOR gate?

GATE 2002

Input Output

A B
(a) 0 1 1

(b) 1 0 0

(c) 0 0 1

(d) 1 1 1

Q-25. Which one of the set of values given below does NOT stisfy the Boolean

relation R = PQ (where Q denotes Not Q)? GATE 2003

(a) P = 1, Q = 1, R = 0 (b) P = 1, Q = 1, R = 1

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(c) P = 0, Q = 0, R = 0 (d) P = 0, Q = 1, R = 0

Q-26. Which of the given relation between the Boolean variables P and Q is NOT

correct?
ect? (In the notation used here, P’ denotes NOT P and Q’ denotes NOT Q)

GATE 2003

(a) PQ + PQ’ = P (b) (PQ)’+ P’ + Q’

(c) PQ’ + (P’ + Q)’ (d) PQ’ + Q = P

Q-27. A half-adder
adder is a digital circuit with

GATE 2004

(a) three inputs and one output (b) three inputs and two outputs

(c) two inputs and one output (d) two inputs and two outputs

Q-28. The Boolean expression ̅ ̅ ̅ reduces

to

(a) ̅ (b) GATE 2004

(c) ̅ (d) ̅

Q-29. The Boolean expression : . can be realized using

minimum number of GATE 2004

(a) 1 AND Gate (b) 2 AND Gate (c) 1 OR Gate (d) 2 OR Gate

Q-30. In the given digital logic circuit. A and B form the input. The output Y is

GATE 2006

A
B

(a) ̅ (b) (c) ⊕ (c)

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Q-31. The largest analog output voltage from a 66-bit

bit digital to analog converter

(DAC) which produces 1.0V output for a digital input of 010100, is

GATE 2006
(a) 1.6 V (b) 2.9 V (c) 3.15 V (d) 5.0 V

Q-32. A ripple counter designed with JK flip

flip-flops
lops provided with CLEAR (CL)

input is shown in the figure. In order that this circuit function as a MOD
MOD-12
12 counter, the NAND

gate input (X1 and X2) should be GATE 2006

D Q C Q B Q A Q

CL K CL K CL K CL K

X1
X2

(a) A and C (b) A and D (c) B and D (d) C and D

Q-33. Identity the function F generated by the logic network shown

GATE 2007

Z
Y

(a) (b)

(c) (d)

Q-34. In the circuit shown, the ports Q1 and Q2 are in the state Q1 = 1, Q2 = 0.

The circuit is now subjected to two complete clock pulses. The state of these ports now becomes

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I J Q I J Q

CLK CLK
I K Q I K Q

(a) 1, 0 (b) 0, 0 GATE 2007

(c) 1, 1 (d) 0, 0

Q-35. The registers Q D, QC, QB and QA shown in the figure are initially in the

state 1010 respectively. An input sequence SI = 0101 is applied. After two clock pulses, the state

of the shift registers (in the same sequence Q D, QC, QB, QA) is GATE 2007

CLK SI 0101
QD QC QB Q A

(a) 1001 (b) 0100 (c) 0110 (d) 1010

Q-36. The simplest logic gate circuit corresponding to the Boolean expression,

is

P
(a) Y (b) Y
Q

P
(c) Y (d) Y
Q

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Q-37. An analog voltage V is converted into 22-bit

bit binary number. The minimum

number of comparators required and their reference voltage are GATE 2008

(a) 3, , , (b) 3, , ,

(c) 4, , , , (d) 4, , , ,

Q-38. The following circuit (where R L >> R) performs the operation of

GATE 2008

R
V1
V0
R
V1 R1
V(1)

(a) OR gate for a negative logic system (b) NAND gate for a negative logic system

(c) AND gate for a positive logic system (d) AND gate for negative logic system

Q-39. In the T type master

master-slave
slave JK flip flop is shown along with the clock and

input waveforms. The Qn output ooff flip flop was zero initially. Identify the correct output

waveform. GATE 2008

Input
Clk J Q J Q
Clk
K Q K Q
Input

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(a) (b)

(c) (d)

Statement for Linked Answer Questions

The Karnaugh map of a logic circuit is shown below:

R R
PQ 1 1
PQ 1
PQ
PQ 1 1

Q-40. The minimized logic expression for the above map is’

(a) (b) ∙ (c) (d) ∙

Q-41. The corresponding logic implementation using gates is given as:

GATE 2009
P P
(a) R Y
(b) R Y
Q Q

P P
(c) Q (d) Q
Y Y
R R

Q-42. The voltage resolution of a 12-bit

bit digital to analog converter (DAC),

whose uoutput varies from -10

10 V to +10 V is, approximately GATE 2010

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(a) 1 mV (b) 5 mV (c) 20 mV (d) 100 mV

Q-43. For any set of inputs A and B, the following circuits give the same output

Q, except one.. Which one is it?

GATE 2010

Q-44. The following Boolean expression

GATE 2010

∙ ∙ ̅∙ ̅∙ ∙ ̅∙ ̅∙ ∙ ̅∙ ̅∙ ∙ ∙ ̅∙ ∙ ∙

∙ ∙ ̅∙

Can be simplified to

(a) ̅ ∙ ∙ ∙ (b) ̅ ∙ ∙ ̅ ∙

(c) ∙ ∙ ̅ ̅ (d) ∙ ∙ ̅∙

Q-45. What should be the clock frequency of a 6-bit

6 A/D

converter so that its maximum conversion (a) 1 MHz (b) 2 MHz

GATE 2010

(c) 0.5 MHz (d) 4 MHz

Q-46. The minimum number of flip

flip-flops
flops required to construct a mod-75
mod counter

is_______

Q-47. In order to measure a maximum of 1V with a resolution of 1mV using a n-

n

bit A/D converter, working under the principle of ladder network, the minimum value of n is___

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Q-48. Which one of the following DOES NOT represent an exclusive OR

operation for inputs A and B?

GATE 2015

(a) (b) (c) ̅ (d)

Q-49. For the digital circuit given below, the output X is

GATE 2016

X
B
C

(a) ̅ ∙ (b) ̅ ∙ ∙ (c) ̅ ∙ (d) ∙

Q-50. The best resolution that a 7 bit A/D converter with 5V full scale can

achieve is ___ mV. (up to two decimal places).

GATE 2017
Q-51. The minimum number of NAND gates required to construct and OR gate

is:

(a) 2 (b) 4 (c) 5 (d) 3 GATE 2017

Q-52. The digital electronic circuit shown below (left side) has some problem and

iss not performing as intended. The voltage at each pin as a function of time is shown in the

adjacent figures.

TIFR 2012

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The problem in the about cirquit may be that

(a) the Pin 8 is clamped to +5 (b) the input inverter is shorted

(c) the Pin 6 is shorted

rted to ground (d) OR gate is used instead of AND gate

Q-53. Consider the circuit shown below TIFR

2012

A
Y
B

The minimum number of NAND gates required to design this circuit is

(a) 6 (b) 5 (c) 4 (d) 3

Q-54. The circuit below uses only NAND gates. Find the final output TIFR

2013

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(a) A XOR B (b) A OR B (c) A AND B (d) A NOR B

Q-55. A control circuit needs to be designed to save on power consumption an

air-conditioning
conditioning unit A in a windowless room with a single door. The room is the following

devices: TIFR 2014

1. A temperature sensor T, which is enabled (T = 1) whenever the temperature falls below a pre-
pre

set value;

2. A humidity sensor H which is enabled (H = 1) whenever the humidity fall following with a

certain pre-set value;

3. A sensor D on the door,, which is triggered (D = 1) whenever the door opens.

Which of the following logical circuits will turn the air

air-conditioning
conditioning unit of whenever the

door is opened or when both temperature and humidity are below set values?

Q-56. A building has three overhead water tanks, each fitted with a sensor (S1, S2,

S3) which goes to 0 when the water level in the tank falls below a set value and remains 1

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otherwise. A common pump is used to raise water from an underground storage tank to these

overhead tanks. Of the following

owing circuits, which one will turn on (P = 1) the pump only when at

least two of the tanks have water level below the set value? TIFR 2015

Q-57. To measure the voltage in the range 0 5 with a precision of 5 mV, the

minimum number of bits required in a digit

digital voltmeter is TIFR 2015

(a) 12 (b) 9 (c) 11 (d) 10

Q-58. In a digital circuit for three input signals (A, B and C) the final output (Y)

should be such that for inputs TIFR

2016

0 0 0
0 0 1
0 1 0
The output (Y) should be low and for all other cases it should be high. Which of the following

digital circuit will give such output?

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Q-59. The output (Y) of the following circuit will be TIFR

2017

(a) ̅ (b) (c) ̅ (d) ̅ ̅

Q-60. For exact calculation and minimum complexity, two four-digit

four binary

number can be added with TIFR

2017
(a) 3 full adders and 1 half-adder
adder (b) 2 full adders and 2 half-adders
adders

(c) 1 full adder and 3 half-adders

adders (d) 4 full adders

Q-61. The ratio of maximum to minimum resistance that can be obtained with

1 resistors is JEST 2012

(a) N (b) (c) 1 (d) ∞

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Q-62. Which of the following circuits will act like a 44-input

input NAND gate? JEST

2014

Q-63. The reference voltage of an analog to digital converter is 1V. The smallest

voltage step that the converter can record using a 12

12-bit converter is, JEST

2015
(a) 0.24V (b) 0.24
0.24mV (d) 0.24µV (d) 0.24 nV

Q-64. For the logic circuit shown in figure 5, the required input condition (A, B,

C) to make the output (X) = 1 is, JEST

2015

(a) 1,0,1 (b) 0,0,1 (c) 1,1,1 (d) 0,1,1

Q-65. What is Y for the circuit shown below? JEST

2017

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(a) (b)

(c) ̅ (c)

Q-66. Which of the following logic gates can be used as a controlled inverter?

HYD 2010
(A) AND gate

(B) OR gate

(C) INVERTER gate

(D) XOR gate

Q-67. Binary equivalent of (8.2)10 is HYD

2010

(A) 1 0 0 1 . 0 0 1 1

(B) 1 0 0 0 . 0 0 1 1

(C) 1 0 0 1 . 0 1 1 0

(D) 0 1 1 1 . 0 1 1 0

Q-68. Synchronous counters eliminate the delay problems encountered with

asynchronous counters because the HYD

2012

(A) Input clock pulses are applied only to the first and last stage
stages.

(B) Input clock pulses are applied only to the last stage.

(C) Input clock pulses are not used to activate any of the counter stages.

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(D) Input clock pulses are applied simultaneously to each stage.

Q-69. When a MOD 5 counter is cascaded with MOD 3 counter, the overall

MOD number is equal to HYD

2012

(a) 15 (b) 8 (c) 2 (d) log(15)

Q-70. If a 4-bit
bit Analog to Digital converter (ADC) has a reference of 5 volts, its

resolution is

(a) 0.3125 V (b) 3.125 V (c) 0.78125 V (d) -3.125 V HYD 2012

Q-71. The number of input combinations and the number of ones in the truth

table for the expression ̅ ̅ are respectively;

(a) 1,3 (b) 2,6 (c) 8,3 (d) 8,5

Q-72. The minimum number of gates required to implement the Boolean

expression 1 after simplification is HYD

2013
(a) 1 (b) 2 (c) 4 (d) 5

Q-73. The minimum number of logic gates that are required to implement the

following logic function , , ∑ 0,2,4 with don’t care condition , , ∑ 3,6 is

(a) 5 (b) 3 (c) 2 (d) 1 HYD 2014

Q-74. The equivalent circuit of the logic circuit given below is HYD

2015

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Q-75. The timing diagrams for a two input OR gate are given below. HYD

2015

The timing diagram corresponding to the output, F is

(a) (b)

(c) (d)

Q-76. The binary number 1011 0110 is equivalent to the decimal number HYD

2016

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(a) 180 (b) 64 (c) 182 (d) 132

Q-77. The dual of the Boolean function is HYD

2016

(a) ̅ ̅ ̅ ̅ (b)

(c) ̅ ̅ ̅ ̅ (d) ̅ ̅ ̅ ̅

Q-78. The state of a flip flop goes from

rom “1” to “0” after applying a clock

pulse (that is 1 and 1 0 . Which of the following is the correct and complete

input combination? HYD 2016

(a) 0 and 1 (d) 0 and

(c) and 1 (d) 1 and 1

Q-79. The Boolean algebra exp

expression reduce to IISC

2011

(a) A + BC (b) A + B (c) AC + (d) A + C

Q-80. If A, B and C are three Boolean variables, the function can be

realized using which of the following sets of four standard logic gates? IISC

2012
(a) Two NAND gates and two OR gates

(b) Two NOR gates and two AND gates

(c) Two NAND gates and two NOR gates

(d) Two AND gates and two OR gates

Q-81. The total number of 1’s in a 15 bit shift register is to be counted by

clocking into a counter which is present to 0. The counter must ha

have
ve which one of the following:

(a) 4 – bits (b) 5 – bits (c) 16 – bits (d) 5 – bits DU 2013

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Q-82. The number of comparator circuits required to build a three-bit

three

simultaneous A/D converter is DU

2013
(a) 7 (b) 8 (c) 15 (d) 16

Q-83. For a flip

flip-flop formed from 2 NAND
D gates as shown in figure, the

unusable state corresponds to

(a) X = 0, Y = 0 (b) Y = 1, Y = 0 (c) X = 0, Y = 1 (d) X = 1, Y = 1

Q-84. The minimal product of sums functions described by K-Map,

K shown in

figure is

AB
C
00 01 11 10
C1 1 1 x 0
C0 0 0 x 0

(a) ’ ’ (b) ’ ’ (c) (d) ’

Q-85. The digital circuit shown in figure acts as a

X D Q

CLK >

(a) JK flip-flop (b) clocked RS flip-flop

(c) T flip-flop (d) ring counter

Data for linked Q.87 and Q.88

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The 4, variable function f is given in terms of min terms as , , ,

∑ 2,3,8,10,12,14,15 . If by use of K
K-Map,
Map, function is minimised in sum of product forms, then

SOP is

Q-86. (a) (b) ̅ (c) ̅ (d)

Q-87. Above minimi

minimised
sed SOP, can be implemented by how many minimum

number of 2 inputs NAND gate

(a) 6 (b) 7 (c) 8 (d) 9

Q-88. If 2’s compliment representation of a 16

16-bit
bit number (one-sign
(one bit and 15

magnitude bits) is FFFF, then its magnitude in decimal representation is

(a) 0 (b) 1 (c) 32767 (d) 65535

Q-89. The initial state of MOD

MOD-16,
16, down counter is 0110. What state will be it be

after 37 clock pulses?

(a) Indeterminate (b) 0110 (c) 0101 (d) 0001

Q-90. How many min

min-term
term (excluding redundant) does the minimal switching

function , , , , , originally have

(a) 16 (b) 20 (c) 24 (d) 32

Q-91. Any combinational circuit can be built using

(1) NAND (2) NOR (3) EX-OR (4) MUX

(a) 1, 2 (b) 1,2,3 (c) 1,2,4 (d) 1,2,3,4

Q-92. A, MOD
MOD-11 ripple counter consists of 4 flip-flops
flops and a combinational
combination

circuit-then
then economical combinational CKT, will be

(a) 4 input AND gate (b) 4 input NAND gate

(c) 3 input OR gate (d) 3 input NOR gate

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Q-93. Above circuit represent a

>D Q D Q

>

>
>

(a) MOD-2 counter (b) MOD-3 counter

(c) MOD-4 counter (d) MOD-4, ring counter

Q-94. In a dual slope ADC, if reference voltage is 100 mV and the first

integration period is set as 50 m sec. for an input voltage of 120 mV,, what is the second

integration (de-integration)
integration) period?

(a) 50 m sec (b) 60 m sec (c) 100 m sec (d) 100 m sec

Q-95. In circuit, shown in figure, when inputs A = B = 0, then possible logic state

of C & D are

(a) C = 0, D = 1 or C = 1, D = 0 (b) C = 1, D = 1 or C = 0, D = 0

(c) C = 1, D = 0 (d) C = 0, D = 1

Q-96. Above given combinational circuit is equivalent to:

(a) NOR (b) OR (c) EX-OR (d) EX-NOR

NOR
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Q-97. The combinational circuit is equivalent to:

1 D3
41
1 D2
MUX Q
1 D1
C D0

A B

(a) ̅ (b) (c) A⨁B⨁C (d)

Q-98. The Boolean expression , , 0,5 is not to be realized using only

two 2 input gates, what are these gates.

(a) AND & OR (b) NAND & OR (c) AND & XOR (d) OR & XOR

Q-99. The Boolean function ̅ is equal to which one of the

following expression

(a) (b) ̅

(c) ̅ (d) ̅

Q-100. If output of a 22-level AND-OR

OR network is F. What is the output when all

gates are replaced by NOR gates.

(a) F (b) (c) FD (d)

Q-101. The total number of 1’s in a 15

15-bit
bit shift register is to be counted by

clocking into a counter, which is pr

present
esent to O. The counter must have which one of the following.

(a) 4-bit (b) 5-bit

bit (c) 6-bit (d) 16-bit

Q-102. A number is expressed in binary 2’s complement as 1011. Its decimal

equivalent value is

(a) −19 (b) +19 (c) −13 (d) +13

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Q-103. The output voltage of a 55-bit DAC, binary ladder, which has a digital input

of 11010 (assume O = 0V and 1 = +10

+10V) is:

(a) 3.4375 volt (b) 6.0 volt (c) 8.125 volt (d) 9.6875 volt

Q-104. The circuit show can be used as

(a) NOR gate (b) OR gate (c) NAND gate (d) AND gate

Q-105. The circuit show in fi

figure below acts as a

(a) NOR gate (b) NAND gate (c) AND gate (d) XOR gate

Q-106. If the output of the logic circuit shown in the figure is 1, the input could be

A
B
Out
C
D

(a) A = 1, B = 1, C = 1, D = 0 (b) A = 1, B = 1, C = 0, D = 0

(c) A = 1, B = 0, C = 1, D = 1 (d) A = 0, B = 1, C = 1, D = 1

Q-107. Which of the following logic families has the highest speed?
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(a) DTL (b) TTL (c) CMOS (d) ECL

Q-108. The pulses shown as A and B are fed into the input of the gate shown

below

A
1 2 3 C
B
B

The output at C has the wave form

(a) (b) (c) (d)

1 2 3 1 2 3 1 2 3 1 2 3

Q-109. A J-K
K flip
flip-flop
flop with J = 1 and K = 1 has a 10 kHz clock input. The Q

output is

(a) A 10 kHz square wave (b) a 5 kHz square wave

(c) Always low (d) always HIGH

Q-110. The binary number 1101 0100 0110 1111 can be written in hexadecimal as

(a) D467 (b) D46F (c) E46F (d) C46F

Q-111. Consider the logic gate arrangement shown in the figure below

The arrangements is equivalent to the gate

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(a) (b) (c) (d)

Q-112. The circuit shown in the figure functions as

+V cC

A B

(a) An OR gate (b) an AND gate (c) a NOR gate (d) a NAND gate

Q-113. Consider the circuit shown below

A
Y
A

The minimum number of NAND gate required to design this circuit is

(a) 6 (b) 5 (c) 4 (d) 3

Q-114. For the logic circuit shown in figure 4, the required input condition

, , to make the output 1 is,

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A
UI
B
XOR
U3 X
AND

U2
C
XNOR

(a) 1,0,1 (b) 0,0,1 (c) 1,1,1 (d) 0,1,1

Q-115. A time varying signal Vin is fed to an op-amp

amp circuit with output signal V0

as shown in the figure below. NET

June 2011

The circuit implements a

(a) High pass filter with cutofff frequency 16 Hz.

(b) High pass filter with cutofff frequency 100 Hz.

(c) Low pass filter with cutofff frequency 16 Hz.

(d) Low pass filter with cutofff frequency 100 Hz.

Q-116. In the operational amplifier circuit below, the voltage at point A is

NET Dec. 2011

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(a) 1.0 V (b) 0.5 V (c) 0 V (d) -5.0 V

Q-117. In the op
op-amp
amp circuit shown in the figure below, the input voltage V is 1V.

The value of the output V0 is NET

June 2012

(a) −0.33 V (b) −0.50 V (c) −1.00 V (d) −0.25 V

Q-118. In the op
op-amp circuit shown in the figure, Vi is a sinusoidal input signal of

frequency 10 Hz and V0 is the output signal. NET Dec. 2012

The magnetic of the gain and the phase shift, respectively, are close to the values

(a) 5√2 (b) 5√2

2 (c) 10 and zero (d) 10 and

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Q-119. Band-pass
pass and band
band-reject
reject filters can be implemented by combining a low

pass and in series and in parallel, rrespectively. If the cut-off

off frequencies of the low pass and are

ω. and ω .
, respectively, the condition required to implement the band-pass
band filters are

respectively.

(a) (b)

(c) (d)

Q-120. lock-in amplifier has the form V t

The input to a lock V sin ω θ where

, , are amplitude, frequency and phase of the input signal respectively. This signal is

multiplied reference signal of the same frequency , amplitude Vr and phase . If the multiplied

signal fed to a low pass filter of cut

cut-off frequency , then the finall output signal is

(a) V V cos θ θ (b) V V cos θ θ cos ωt θ

(b) V V sin θ θ (d) V V cos θ θ cos ωt θ

Q-121. Consider the op

op-amp circuit shown in the figure. NET

Dec. 2013

If the input is a sinusoidal wave 5 sin 1000 , then the amplitude of the output V0 is

(d) 5√2
√
(a) (b) 5 (c)

Q-122. An op-amp
amp based voltage follower NET

June 2014
(a) Is useful for converting a low impedance source into a high impedance source

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(b) Is useful for converting a low impedance source into a low impedance source

(c) Has infinitely high closed loop output impedance

(d) Has infinitely high closed loop gain

Q-123. The inner shield of a triaxial conductor is driven by an (ideal) op-amp

op

follower circuit as shown. The effective capacitance between the signal carrying conduction and

ground is NET June 2014

(a) unaffected (b) doubled (c) halved (d) made zero

Q-124. Consider the amplifier circuit comprising of the two op-amps

op A1 and A2 as

shown in the figure. If the input ac signal source has an impedance of 50kΩ, which of the

following statement is true? NET

Dec. 2014

(1) A1 is required in the circuit because the source impedance is much greater than r

(2) A1 is required in the circuit because the source impedance is much less than R

(3) A1 can be eliminated from the circuit without affecting the over
overall gain

(4) A1 is required in the circuit if the output has to follow the phase of the input signal

Q-125. Consider a Low Pass (LP) and High Pass (HP) filter with cut-off
cut

frequencies fLP and fHP respectively, connected in series or in parallel configurations as shown in

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the Figure A and B below.

NET Dec. 2014

HP LP
Input Output
(A)
fHP fLP

HP

fHP
Input Output
(B)

LP

fLP

Which of the following statements in correct?

(1) For fHP < fLP, A acts as a Band Pass filter and B acts as a Band Reject filter

(2) For fHP < fLP, A stop the signal from passing through and B passes the signal without filtering

(3) For fHP < fLP, A acts as a Band Pass filter and B passes the signal without filtering

(4) For fHP < fLP, A passes the signal without filtering and B acts as a Band Reject filter

Q-126. In the circuit given below, the thermistor has a resistance 3 kΩ at 250 C. Its

resistance 150Ω per 0C upon heating. The output voltage of the circuit at 30 0C is

(a) −3.75 V (b) −2.25 V (c) 2.25 V (d) 3.75 V

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Q-127. For the circuit and the input sinusoidal waveform shown in the figures

below, which is the correct waveform at the output? NET

June 2015

(The time scales in all the plots are the same)

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Q-128. In the circuit given below, the thermistor has a resistance 3kΩ 0C upon

heating. The output voltage of the circuit at 30 0 C is NET

June 2015

(a) −3.75 V (b) −2.25 V (c) 2.25 V (d) 3.75 V

Q-129. A sinusoidal signal of peak ot peak amplitude 1V and unknown time

period is input to the following circuit for 5 seconds duration. If the counter measures a value

(3E8)H in hexadecimal then the time period of the input signal is NET Dec. 2015

(a) 2.5 ms (b) 4 ms (c) 10 ms (d) 5 ms

Q-130. If the parameters y and x are related by y = log(x), then the circuit that can

be used to produce an output voltage V0 varying linearly with x is NET Dec. 2015

(1) (2)
y  y 
+ V0 + V0

(3) (4)
y  V0
y  V0
+ +

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Q-131. Given the input voltage Vi, which of following waveforms correctly

represents output voltage V0 in the circuit shown below NET

June 2016

Q-132. In the circuit below, the input voltage Vi is 2 V, Vcc = 16 V, R2 = 2 kΩ and

RL = 10 kΩ.

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The value of R1 required to deliver 10 mW of power across RL is NET Dec. 2016

(a) 12 kΩ (b) 4 kΩ (c) 8 kΩ (d) 14 kΩ

Q-133. Two sinusoidal signals are sent to an analog multiplier off scale factor 1

V−1 followed by a low pass filter (LPF). NET Dec. 2016

V 1 = 5 cos (100t)

LPF
Multiplier fc =5 hz
Vout

V 2 = 20 cos (100t + /3)

If the roll-off
off frequency of the LPF is fc = 5 Hz, the output voltage Vout is

(a) 5 V (b) 25 V (c) 100 V (d) 50 V

Q-134. In the following operational amplifier circuit 10 , 200

and 100 . NET June 2017

RF

CF

R1 C1
Vin Vout

The magnitude of the gain at a input signal frequency of 16 kHz is

(a) 67 (b) 0.15 (c) 0.3 (d) 3.5

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Q-135. The gain of the circuit given below is . NET

June 2017

R V
Vin 
+ Vout
V+ b a

The modification in the circuit required to introduce a dc feedback is to add a resistor

(a) Between a and b

(b) Between positive terminal of the op

op-amp and ground

(c) In series with C

(d) Parallel to C

Q-136. The feedback ratio of an amplifier, which on application of a negative

feedback, changes the voltage gain from −0.250 to −100 is GATE 2002

(a) -0.250 (b) -0.025

0.025 (c) -0.060 (d) -0.006

Q-137. A bistable multivibrator with a saturation voltage 5 is shown in the

diagram. The positive and negative threshold at the inversting terminal for which the

multivibrator will switch to the other state are

GATE 2002

2M


+ O

2M
0.01 F
200K

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(a) 5/11 (b) 10

10/11 (c) 5 (d) 11

Data for Q. No. 139 to 140

R

V1 + V0
C

Q-138. For high frequencies → ∞ the input impedance is

GATE 2003

(a) 0 (b) 1R (c) / 1 (d) ∞

Q-139. For low frequencies → ∞ the input impedance is

GATE 2003

(a) 1/

(b) The voltage at the inverting and non

non-inverting terminals of the op-amp
amp are nearly

(c) The voltage at the non-inverting

inverting terminal of the op
op-amp
amp and the current in the resistor

attached to i are /2 out of page

(d) The current in the two resistor are in phase

Q-140. The inverting input terminal of an operational amplifier (op-amp)

(op is

shorted with the output terminal apart from being ground. A voltage signal is applied to the

non-inverting
inverting input terminal of the op
op-amp.
amp. Under the configuration, the op-amp
op functions as

GATE 2004
(a) an open loop inverter (b) a voltage to current converter

(c) a voltage follower (d) an oscillator

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Q-141. Figure shows a practical integrator with 30 Ω,

Ω 20 Ω and

0.1 . If a step (dc) voltage of +3 V is applied as input for 0 4 (t is in seconds), the

output voltage is GATE 2004

RF

RS CF

+ V0
+
+3V ROM

(a) a ramp function of −6 V (b) a step function of −12 V

(c) a ramp function of −15 V (b) a ramp function of −4 V

Q-142. The output V0 of the ideal opamp circuit shown in the figure is

GATE 2005

5K 

1K 
+2 
V0
+1 +
1K
1K

(a) −7 V (b) −5 V (c) 5 V (d) 7 V

Q-143. The circuit shown in the figure can be used as a

GATE 2005

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Vin C Vout

(a) a high filter or a differentiator (b) high pas filter or an integrator

(c) low pas filter or a differentiator (d) low pas filter or an integrator

Q-144. The low pass active filter shown in the figure has a cut-off
cut frequency of 2

kHz and a pass band gain of 1.5. The values of the resistors are

GATE 2006


15K

R1
Vout

Vin R2
0.047F

(a) R1 = 10 kΩ ; R2 = 1.3 Ω (b) R1 = 30 kΩ ; R2 = 1.3 Ω

(c) R1 = 10 kΩ ; R2 = 1. Ω (d) R1 = 30 kΩ ; R2 = 1.7 Ω

Q-145. The circuit shown is based on ideal operational amplifiers. It

(a) subtractor (b) buffer amplifier (c) adder (d) divider

Statement for Linked Answer Questions 147 and 148:

The following circuit contains three operational amplifiers and resistors

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R R

3R R
Va 
3R +  V 01
Vb +
3R 3R
Vc

R
R 
Va + V02
R
Vb
R
Vc
R

Q-146. The output voltage at the end of second operational amplifier V 01 is

GATE 2008

(a) 3 (b)

(c) (d)

Q-147. The output V02 (at the end of third op amp) of the above circuit is

GATE 2008

(a) 2 (b) 3

(c) (d) Zero

Q-148. The common Mode Rejection Ratio (CMRR) of a differential amplifier

using an operational amplifier is 100 dB. The output voltage for a differential input of 200 V is

2 V. The common mode gain is GATE 2009

(a) 10 (b) 0.1 (c) 30 dB (d) 10 dB

Q-149. In the of th
thee following circuits, negative feedback does not operate for a

negative input. Which one is it? The opamps are running from 15 supplies.

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 
(a) + (b) +

 
(c) + (d) +

Q-150. Consider a conducting loop of radius a and total loop resistance R placed in

a region
gion with a magnetic field B thereby enclosing a flux . The loop is connected to an

electronic circuit as shown, the capacitor being initially uncharged.

C
  
   
  
   
 B 
   Vout
   +
  
  
  
  

If the loop is pulled out of the region of the magnetic field at a constant speed u, the final output

voltage Vout is independent of

+10 V

Vin  Vout
-10 V

Which of the following correctly represents the output V out corresponding to the input Vin?

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+5V +5V
+2V +2V
Vin Vin
2V 2V
5V 5V
(a) (b)
+10V +10V

Vout Vout

10V 10V

+5V +5V
+2V +2V
Vin Vin
2V 2V
5V 5V
(c) (d)
+10V +10V

Vout Vout

10V 10V

Q-151. In the following circuit, for the output voltage to /2 the

ratio / is

R
+V
R
V1 
V2 + V0
R1
-V 
R2

(a) 1/2 (b) 1 (c) 2 (d) 3

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Q-152. Consider the following OP

OP-AMP circuit.

GATE 2012

+10V
Vin +
4K
+5V 
1K -10V

Which one of the following

ing correctly represents the output Vout corresponding to the input Vin?

+5V +5V
Vin V in
+1V +1V
0V t 0V t
(a) (b)

+10V +10V
V out Vout
t t
10V 10V

+5V +5V
Vin Vin

0V t 0V t
(c) (d)

+10V +10V
V out Vout
t t
10V 10V

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Statement for Linked Answer Questions 154 and 155: Consider the following circuit

1K
V(in) 
V(out)
1 Mf 
2

Q-153. For this circuit the frequency above which the gain will decrease by 20 dB

per decade is

(a) 15.9 kHz (b) 1.2 kHz GATE 2013

(c) 5.6 kHz (d) 22.5 kHz

Q-154. At 1:2 kHz the closed loop gain is

GATE 2013
(a) 1 (b) 1.5 (c) 3 (d) 0.5

Q-155. A low pas filter is formed by a resistance R and a capacitance C. At the

cut-off angular frequency the voltage gain and the phase of the output voltage relative to

the input voltage respectively, are GATE 2014

(a) 0.71 and 450 (b) 0.71 and −450

(c) 0.5 and −900 (d) 0.5 and 900

Q-156. The input given to be an ideal OP

OP-AMP
AMP integrator circuit is

GATE 2014

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V0

t
t0

The correct output of the integrator circuit is

V V
(a) (b)
V0 V0

t t
t0 t0

V V
(c) (d)
V0 V0

t t
t0 t0

Q-157. Consider the circuit shown in the figure, where RC = 1. For an

a input signal

Vi shown below, choose the correct V 0 from the options:

R
Vi
Vt 
V0
 l

1 2 3

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V0 V0
1 1

(a) t (b) t
1 2 3 1 2 3

1 1

V0 V0
0.1 1

(c) t (d) t
1 2 3 1 2 3

1

Q-158. In the given circuit, if the open loop gain A = 105, the feedback

configuration and the closed loop gain Af are GATE 2015

V1 +
V0


9 K
1 K RL

(a) series-shunt, Af = 9 (b) series-shunt, Af = 10

(c) series-shunt, Af = 10 (b) shunt-shunt, Af = 10

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Q-159. Consider an ideal operational amplifier as shown in the figure below with

R1 = 5kΩ, R2 = 1kΩ, RL = 100kΩ. For an applied input voltage V = 10 mV, the current passing

through R2 is ________ μA. (up to two decimal places). GATE 2017


R1
V

RL
R2

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Q-160. The following circuit is fed with an input sine wave of frequency
frequenc 50 Hz.

TIFR 2017
10 pF

10 K

10 K
Vin 
Vout
+

Which of the following graphs (solid line is input and dashed line is output) best represents the

correct situation?

(a) (b)

(c) (d)

Q-161. Consider the following circuit:

R

C
V in 
Vout
+

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If the waveform given below is fed in at V in,

Vin
+Vp

Vp

Then the waveform at the output Vout will be

Vout Vout

(a) (b)

Vout Vout

(c) (d)

Q-162. An input of 1.0 V DC is given to the ideal Op

Op-amp
amp circuit depicted
depict below.

What will be the output voltage

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L=1m
L=1m
C=1
C=1F
R=90k
R=90k
R=10K

Op Amp
+ Vout
Vin

(a) 10.0 V (b) 1.0 V (c) 0 V (d) −9.0 V

Q-163. In the following circuit, the resistance R 2 is doubled. It follows that the

current through R2 TIFR 2014

Vin +


R2
R1

(a) remains the same (b) is halved

(c) is doubled (d) is quadrupled

Q-164. In the circuit shown below, the op

op-amp
amp is powered by a bipolar supply of

10 .

+
Vout

V = 5 sin(2t)


5k

Which one of the following graphs represents V out correctly?

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10 10
(a) 5 (b) 5
Vout 0 Vout 0
5 5
10 10
0 1 2 3 4 5 0 1 2 3 4 5
t t

10 10
(c) 5 (d) 5
Vout 0 Vout 0
5 5
10 10
0 1 2 3 4 5 0 1 2 3 4 5
t t

Q-165. In the generalized operational amplifier circuit shown on the right, the op

amp. has a very high input impedance 50 and an open gain of 1000 for the frequency

range under consideration. Assuming that the op. amp. Draws negligible current, the voltage ratio

is approximately

500 k
5 k
+

V1 V2
Z

(a) −190 (b) −190 (c) −90 (d) 80

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