Internal Use Only

North/Latin America http://aic.lgservice.com

Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com

LED TV
SERVICE MANUAL
CHASSIS : LA46B

MODEL : 42LB5800 42LB5800-UG

CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

P/NO : MFL68026204 (1402-REV00) Printed in Korea

 CONTENTS

CONTENTS . ............................................................................................. 2

PRODUCT SAFETY ................................................................................. 3

SPECIFICATION........................................................................................ 4

ADJUSTMENT INSTRUCTION................................................................. 9

BLOCK DIAGRAM................................................................................... 18

EXPLODED VIEW .................................................................................. 19

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

Copyright © LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
 SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1 W), keep the resistor 10 mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed

metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Copyright © LG Electronics. Inc. All rights reserved. -3- LGE Internal Use Only
Only for training and service purposes
 SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service 2. After removing an electrical assembly equipped with ES
manual and its supplements and addenda, read and follow the devices, place the assembly on a conductive surface such as
SAFETY PRECAUTIONS on page 3 of this publication. aluminum foil, to prevent electrostatic charge buildup or expo-
NOTE: If unforeseen circumstances create conflict between the sure of the assembly.
following servicing precautions and any of the safety precautions 3. Use only a grounded-tip soldering iron to solder or unsolder ES
on page 3 of this publication, always follow the safety precautions. devices.
Remember: Safety First. 4. Use only an anti-static type solder removal device. Some solder
removal devices not classified as “anti-static” can generate
General Servicing Precautions electrical charges sufficient to damage ES devices.
1. Always unplug the receiver AC power cord from the AC power 5. Do not use freon-propelled chemicals. These can generate
source before; electrical charges sufficient to damage ES devices.
a. Removing or reinstalling any component, circuit board mod- 6. Do not remove a replacement ES device from its protective
ule or any other receiver assembly. package until immediately before you are ready to install it.
b. Disconnecting or reconnecting any receiver electrical plug or (Most replacement ES devices are packaged with leads electri-
other electrical connection. cally shorted together by conductive foam, aluminum foil or
c. Connecting a test substitute in parallel with an electrolytic comparable conductive material).
capacitor in the receiver. 7. Immediately before removing the protective material from the
CAUTION: A wrong part substitution or incorrect polarity leads of a replacement ES device, touch the protective material
installation of electrolytic capacitors may result in an explo- to the chassis or circuit assembly into which the device will be
sion hazard. installed.
2. Test high voltage only by measuring it with an appropriate CAUTION: Be sure no power is applied to the chassis or circuit,
high voltage meter or other voltage measuring device (DVM, and observe all other safety precautions.
FETVOM, etc) equipped with a suitable high voltage probe. 8. Minimize bodily motions when handling unpackaged replace-
Do not test high voltage by "drawing an arc". ment ES devices. (Otherwise harmless motion such as the
3. Do not spray chemicals on or near this receiver or any of its brushing together of your clothes fabric or the lifting of your
assemblies. foot from a carpeted floor can generate static electricity suf-
4. Unless specified otherwise in this service manual, clean ficient to damage an ES device.)
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable General Soldering Guidelines
non-abrasive applicator; 10 % (by volume) Acetone and 90 % 1. Use a grounded-tip, low-wattage soldering iron and appropriate
(by volume) isopropyl alcohol (90 % - 99 % strength) tip size and shape that will maintain tip temperature within the
CAUTION: This is a flammable mixture. range or 500 °F to 600 °F.
Unless specified otherwise in this service manual, lubrication of 2. Use an appropriate gauge of RMA resin-core solder composed
contacts in not required. of 60 parts tin/40 parts lead.
5. Do not defeat any plug/socket B+ voltage interlocks with which 3. Keep the soldering iron tip clean and well tinned.
receivers covered by this service manual might be equipped. 4. Thoroughly clean the surfaces to be soldered. Use a mall wire-
6. Do not apply AC power to this instrument and/or any of its bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
electrical assemblies unless all solid-state device heat sinks are Do not use freon-propelled spray-on cleaners.
correctly installed. 5. Use the following unsoldering technique
7. Always connect the test receiver ground lead to the receiver a. Allow the soldering iron tip to reach normal temperature.
chassis ground before connecting the test receiver positive (500 °F to 600 °F)
lead. b. Heat the component lead until the solder melts.
Always remove the test receiver ground lead last. c. Quickly draw the melted solder with an anti-static, suction-
8. Use with this receiver only the test fixtures specified in this type solder removal device or with solder braid.
service manual. CAUTION: Work quickly to avoid overheating the circuit
CAUTION: Do not connect the test fixture ground strap to any board printed foil.
heat sink in this receiver. 6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
Electrostatically Sensitive (ES) Devices (500 °F to 600 °F)
Some semiconductor (solid-state) devices can be damaged eas- b. First, hold the soldering iron tip and solder the strand against
ily by static electricity. Such components commonly are called the component lead until the solder melts.
Electrostatically Sensitive (ES) Devices. Examples of typical ES c. Quickly move the soldering iron tip to the junction of the
devices are integrated circuits and some field-effect transistors component lead and the printed circuit foil, and hold it there
and semiconductor “chip” components. The following techniques only until the solder flows onto and around both the compo-
should be used to help reduce the incidence of component dam- nent lead and the foil.
age caused by static by static electricity. CAUTION: Work quickly to avoid overheating the circuit
1. Immediately before handling any semiconductor component or board printed foil.
semiconductor-equipped assembly, drain off any electrostatic d. Closely inspect the solder area and remove any excess or
charge on your body by touching a known earth ground. Alter- splashed solder with a small wire-bristle brush.
natively, obtain and wear a commercially available discharging
wrist strap device, which should be removed to prevent poten-
tial shock reasons prior to applying power to the unit under test.

Copyright © LG Electronics. Inc. All rights reserved. -4- LGE Internal Use Only
Only for training and service purposes
IC Remove/Replacement 3. Solder the connections.
Some chassis circuit boards have slotted holes (oblong) through CAUTION: Maintain original spacing between the replaced
which the IC leads are inserted and then bent flat against the cir- component and adjacent components and the circuit board to
cuit foil. When holes are the slotted type, the following technique prevent excessive component temperatures.
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique Circuit Board Foil Repair
as outlined in paragraphs 5 and 6 above. Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
Removal board causing the foil to separate from or "lift-off" the board. The
1. Desolder and straighten each IC lead in one operation by following guidelines and procedures should be followed whenever
gently prying up on the lead with the soldering iron tip as the this condition is encountered.
solder melts.
2. Draw away the melted solder with an anti-static suction-type At IC Connections
solder removal device (or with solder braid) before removing To repair a defective copper pattern at IC connections use the
the IC. following procedure to install a jumper wire on the copper pattern
Replacement side of the circuit board. (Use this technique only on IC connec-
1. Carefully insert the replacement IC in the circuit board. tions).
2. Carefully bend each IC lead against the circuit foil pad and
solder it. 1. Carefully remove the damaged copper pattern with a sharp
3. Clean the soldered areas with a small wire-bristle brush. knife. (Remove only as much copper as absolutely necessary).
(It is not necessary to reapply acrylic coating to the areas). 2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
"Small-Signal" Discrete Transistor 3. Bend a small "U" in one end of a small gauge jumper wire and
Removal/Replacement carefully crimp it around the IC pin. Solder the IC connection.
1. Remove the defective transistor by clipping its leads as close 4. Route the jumper wire along the path of the out-away copper
as possible to the component body. pattern and let it overlap the previously scraped end of the
2. Bend into a "U" shape the end of each of three leads remaining good copper pattern. Solder the overlapped area and clip off
on the circuit board. any excess jumper wire.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding At Other Connections
leads extending from the circuit board and crimp the "U" with Use the following technique to repair the defective copper pattern
long nose pliers to insure metal to metal contact then solder at connections other than IC Pins. This technique involves the
each connection. installation of a jumper wire on the component side of the circuit
board.
Power Output, Transistor Device
Removal/Replacement 1. Remove the defective copper pattern with a sharp knife.
1. Heat and remove all solder from around the transistor leads. Remove at least 1/4 inch of copper, to ensure that a hazardous
2. Remove the heat sink mounting screw (if so equipped). condition will not exist if the jumper wire opens.
3. Carefully remove the transistor from the heat sink of the circuit 2. Trace along the copper pattern from both sides of the pattern
board. break and locate the nearest component that is directly con-
4. Insert new transistor in the circuit board. nected to the affected copper pattern.
5. Solder each transistor lead, and clip off excess lead. 3. Connect insulated 20-gauge jumper wire from the lead of the
6. Replace heat sink. nearest component on one side of the pattern break to the lead
of the nearest component on the other side.
Diode Removal/Replacement Carefully crimp and solder the connections.
1. Remove defective diode by clipping its leads as close as pos- CAUTION: Be sure the insulated jumper wire is dressed so the
sible to diode body. it does not touch components or sharp edges.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and if
necessary, apply additional solder.

Fuse and Conventional Resistor

Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.

Copyright © LG Electronics. Inc. All rights reserved. -5- LGE Internal Use Only
Only for training and service purposes
 SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.

1. Application range
1.1. This spec sheet is applied all of the 32”, 39”, 42”, 47”, 50”,
55”, 60, 65” LED TV with LA46B chassis.
1.2. Not included spec and each product spec in this spec
sheet apply correspondingly to the following each country
standard and requirement of Buyer

2. Test condition
Each part is tested as below without special notice.

1) Temperature : 20 ºC ± 5 ºC
2) Relative Humidity: 65 % ± 10 %
3) Power Voltage
Market Input voltage Frequency Remark
USA 110~240V 50/60Hz Standard Voltage of each
product is marked by
models

4) Specification and performance of each parts are followed

each drawing and specification by part number in
accordance with BOM
5) The receiver must be operated for about 20 minutes prior to
the adjustment

3. Test method
1) Performance: LGE TV test method followed
2) Demanded other specification
- Safety : UL, CSA, IEC specification
- EMC: FCC, ICES, IEC specification
- Wireless : WirelessHD Specification (Option)

Copyright © LG Electronics. Inc. All rights reserved. -6- LGE Internal Use Only
Only for training and service purposes
4. General Specification
No Item Specification Remark
1 Market 1) North America
2 Television System NTSC-M, ATSC, 64 & 256 QAM
3 Input Voltage AC 100 ~ 240V 50/60Hz
4 Available Channel 1) VHF : 02~13
2) UHF : 14~69
3) DTV : 02-69
4) CATV : 01~135
5) CADTV : 01~135
5 Aspect Ratio 16:9
6 Tuning System FS
7 LCD Module LC550DUE-FGA3 LGD 55LB5800-UA
T500HVF05.0 AUO 50LB5800-UA
LC550DUE-FGA4 LGD 55LB6100-UG
LC500DUE-FGA4 LGD 50LB5800-UG, 50LB6100-UG
LC470DUE-FGA4 LGD 47LB5800-UG, 47LB6100-UG
LC420DUE-FGA4 LGD 42LB5800-UG
LC650DUF-FGA1 LGD 65LB6190-UD
HC600DUF-VHHS2 Sharp 60LB6100-UG
T550HVF04.2 AUO 55LB6100-UG/55LB5800-UG
NC500DUN-VXBP2 INX 50LB6100-UG/50LB5800-UG
T420HVF07.0 AUO 42LB5800-UG
NC390DUN-VXBP2 INX 39LB5800-UG
LC320DUE-FGA4 LGD 32LB5800-UG
NC320DXN-VSBP2 Sharp 32LB580B-UG
LC320DXE-FGA4 LGD 32LB580B-UG
8 Operating Environment 1) Temp : 0 ~ 40 deg
2) Humidity : ~ 80 %
9 Storage Environment 1) Temp : -20 ~ 60 deg
2) Humidity : ~ 85 %

Copyright © LG Electronics. Inc. All rights reserved. -7- LGE Internal Use Only
Only for training and service purposes
5. Supported video resolutions
5.1. Component 2D input(Y, CB/PB, CR/PR)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed
1. 720*480 15.73 60 13.5135 SDTV ,DVD 480I
2. 720*480 15.73 59.94 13.5 SDTV ,DVD 480I
3. 720*480 31.50 60 27.027 SDTV 480P
4. 720*480 31.47 59.94 27.0 SDTV 480P
5. 1280*720 45.00 60.00 74.25 HDTV 720P
6. 1280*720 44.96 59.94 74.176 HDTV 720P
7. 1920*1080 33.75 60.00 74.25 HDTV 1080I
8. 1920*1080 33.72 59.94 74.176 HDTV 1080I
9. 1920*1080 26.97 23.976 74.176 HDTV 1080P
10. 1920*1080 27.00 24.00 74.25 HDTV 1080P
11. 1920*1080 33.71 29.97 74.176 HDTV 1080P
12. 1920*1080 33.75 30.00 74.25 HDTV 1080P
13. 1920*1080 67.432 59.94 148.352 HDTV 1080P
14. 1920*1080 67.50 60 148.50 HDTV 1080P

5.2. HDMI Input (PC/DTV)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed
PC DDC
1 640*350 31.468 70.09 25.17 EGA X
2 720*400 31.469 70.08 28.32 DOS O
3 640*480 31.469 59.94 25.17 VESA(VGA) O
4 800*600 37.879 60.31 40.00 VESA(SVGA) O
5 1024*768 48.363 60.00 65.00 VESA(XGA) O
6 1152*864 54.348 60.053 80.002 VESA O
7 1360*768 47.712 60.015 85.50 VESA (WXGA) X
8 1280*1024 63.981 60.020 108.00 VESA (SXGA) O
9 1920*1080 67.5 60 148.5 HDTV 1080P O
DTV
1 720*480 31.50 60 27.027 SDTV 480P
2 720*480 31.469 59.94 27.00 SDTV 480P
3 1280*720 45.00 60.00 74.25 HDTV 720P
4 1280*720 44.96 59.94 74.176 HDTV 720P
5 1920*1080 33.75 60.00 74.25 HDTV 1080I
6 1920*1080 33.72 59.94 74.176 HDTV 1080I
7 1920*1080 67.500 60 148.50 HDTV 1080P
8 1920*1080 67.43 59.94 148.352 HDTV 1080P
9 1920*1080 27.000 24.000 74.25 HDTV 1080P
10 1920*1080 26.97 23.97 74.176 HDTV 1080P
11 1920*1080 33.75 30.000 74.25 HDTV 1080P
12 1920*1080 33.716 29.976 74.176 HDTV 1080P

Copyright © LG Electronics. Inc. All rights reserved. -8- LGE Internal Use Only
Only for training and service purposes
 ADJUSTMENT INSTRUCTION
1. Application 4. MAIN PCBA Adjustments
This spec. sheet applies to LA46B Chassis applied LED TV all 4.1. ADC Calibration
models manufactured in TV factory - A n ADC calibration is not necessary because MAIN SoC
(LGExxxx) is already calibrated from IC Maker

2. Specification 4.2. M AC Address, ESN Key and Widevine

(1) Because this is not a hot chassis, it is not necessary to use
an isolation transformer. However, the use of isolation Key, DTCP Key, HDCP1.4, HDCP2.0
transformer will help protect test instrument. download
(2) Adjustment must be done in the correct order. 4.2.1. Equipment & Condition
(3) The adjustment must be performed in the circumstance of 1) Play file: keydownload.exe
25 ±5 ºC of temperature and 65±10% of relative humidity if
there is no specific designation 4.2.2. Communication Port connection
(4) The input voltage of the receiver must keep 100~240V, 1) Key Write: Com 1,2,3,4 and 115200 (Baudrate)
50/60Hz 2) Barcode: Com 1,2,3,4 and 9600 (Baudrate)
(5) At first Worker must turn on the SET by using Power Only
key.
(6) The receiver must be operated for about 5 minutes prior to
4.2.3. Download process
1) Select the download items.
the adjustment when module is in the circumstance of over
2) Mode check: Online Only
15 ºC
3) Check the test process
In case of keeping module is in the circumstance of 0°C, it
- U S, Canada models: DETECT -> MAC_WRITE ->
should be placed in the circumstance of above 15°C for 2
WIDEVINE_WRITE
hours
4) Play : START
In case of keeping module is in the circumstance of below
5) Check of result: Ready, Test, OK or NG
-20°C, it should be placed in the circumstance of above
6) Printer out (MAC Address Label)
15°C for 3 hours.

※ Caution 4.2.4. Communication Port connection

When still image is displayed for a period of 20 minutes or 1) Connect: PCBA Jig -> RS-232C Port == PC -> RS-232C
longer (especially where W/B scale is strong. Port
Digital pattern 13ch and/or Cross hatch pattern 09ch), there
can some afterimage in the black level area

3. Adjustment items
3.1. Final assembly adjustment
(1) White Balance adjustment
(2) RS-232C functionality check
(3) Factory Option setting per destination
(4) Shipment mode setting (In-Stop) 4.2.5. Download
(5) GND and HI-POT test 1) US, Canada models (14Y LED TV + MAC + Widevine +
ESN Key + DTCP Key + HDCP1.4 and HDCP2.0)
3.2. Appendix
(1) Tool option menu, USB Download (S/W Update, Option
and Service only)
(2) Manual adjustment for ADC calibration and White balance.
(3) Shipment conditions, Channel pre-set

4.2.6. Inspection
- In INSTART menu, check these keys.

Copyright © LG Electronics. Inc. All rights reserved. -9- LGE Internal Use Only
Only for training and service purposes
4.3. LAN port Inspection (Ping Test) 4.4.3. EDID DATA
4.3.1. Equipment setting 4.4.3.1. . 2D_8bit_PCM(US) _ xvYCC : off (HD)
1) Play the LAN Port Test PROGRAM. HDMI EDID 2D_8bit_PCM(US)_xvYCC : off (HD)
2) Input IP set up for an inspection to Test Program.
- IP number: 12.12.2.2

4.3.2. LAN PORT inspection (PING TEST)

1) Play the LAN Port Test Program.
2) Connect each other LAN Port Jack.
3) Play Test (F9) button and confirm OK Message.
4) Remove LAN CABLE
▪Reference
- HDMI1 ~ HDMI3
- In the data of EDID, bellows may be different by S/W or Input
mode.

ⓐ Product ID
HEX EDID Table DDC Function
0001 0100 Analog
0001 0100 Digital

ⓑ Serial No: Controlled on production line.

ⓒ Month, Year: Controlled on production line:
ex) Monthly : ‘01’ -> ‘01’
Year : ‘2014’ -> ‘18’
ⓓ Model Name(Hex): LGTV
Chassis MODEL NAME(HEX)
LA46B 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20

ⓔ Checksum(LG TV): Changeable by total EDID data.

ⓔ1 ⓔ2 ⓔ3
4.4. EDID Download HDMI1 A5 0C X
4.4.1 Overview HDMI2 A5 FC X
▪ I t is a VESA regulation. A PC or a MNT will display an
optimal resolution through information sharing without any HDMI3 A5 EC X
necessity of user input. It is a realization of “Plug and Play”.
ⓕ Vendor Specific(HDMI)
4.4.2 Equipment
INPUT MODEL NAME(HEX)
▪ Since embedded EDID data is used, EDID download JIG,
HDMI cable and D-sub cable are not need. HDMI1 67 03 0C 00 10 00 80 1E
▪ Adjust remocon
HDMI2 67 03 0C 00 20 00 80 1E
HDMI3 67 03 0C 00 30 00 80 1E

Copyright © LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
Only for training and service purposes
4.4.3.2. 2D_8bit_PCM(US) _ xvYCC : off 4.4.3.3. 2D_10bit_PCM(US) _ xvYCC : off
HDMI EDID 2D_8bit_PCM(US)_xvYCC : off HDMI EDID 2D_10bit_PCM(US)_xvYCC : off

▪Reference ▪Reference
- HDMI1 ~ HDMI3 - HDMI1 ~ HDMI3
- In the data of EDID, bellows may be different by S/W or Input - In the data of EDID, bellows may be different by S/W or Input
mode. mode.

ⓐ Product ID ⓐ Product ID
HEX EDID Table DDC Function HEX EDID Table DDC Function
0001 0100 Analog 0001 0100 Analog
0001 0100 Digital 0001 0100 Digital

ⓑ Serial No: Controlled on production line. ⓑ Serial No: Controlled on production line.
ⓒ Month, Year: Controlled on production line: ⓒ Month, Year: Controlled on production line:
ex) Monthly : ‘01’ -> ‘01’ ex) Monthly : ‘01’ -> ‘01’
Year : ‘2014’ -> ‘18’ Year : ‘2014’ -> ‘18’
ⓓ Model Name(Hex): LGTV ⓓ Model Name(Hex): LGTV
Chassis MODEL NAME(HEX) Chassis MODEL NAME(HEX)
LA46B 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 LA46B 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20

ⓔ Checksum(LG TV): Changeable by total EDID data. ⓔ Checksum(LG TV): Changeable by total EDID data.
ⓔ1 ⓔ2 ⓔ3 ⓔ1 ⓔ2 ⓔ3
HDMI1 E7 1C X HDMI1 E7 02 X
HDMI2 E7 0C X HDMI2 E7 F2 X
HDMI3 E7 FC X HDMI3 E7 E2 X

ⓕ Vendor Specific(HDMI) ⓕ Vendor Specific(HDMI)

INPUT MODEL NAME(HEX) INPUT MODEL NAME(HEX)
HDMI1 67 03 0C 00 10 00 80 1E HDMI1 67 03 0C 00 10 00 B8 2D
HDMI2 67 03 0C 00 20 00 80 1E HDMI2 67 03 0C 00 20 00 B8 2D
HDMI3 67 03 0C 00 30 00 80 1E HDMI3 67 03 0C 00 30 00 B8 2D

Copyright © LG Electronics. Inc. All rights reserved. - 11 - LGE Internal Use Only
Only for training and service purposes
5. Final Assembly Adjustment 5.1.4. Adjustment Command (Protocol)
(1) RS-232C Command used during auto-adj.
5.1. White Balance Adjustment
RS-232C COMMAND
5.1.1. Overview Explanation
5.1.1.1. W/B adj. Objective & How-it-works CMD DATA ID
(1) Objective: To reduce each Panel’s W/B deviation Wb 00 00 Begin White Balance adj.
(2) How-it-works: When R/G/B gain in the OSD is at 192, it
means the panel is at its Full Dynamic Range. In order to Wb 00 ff End White Balance adj.
prevent saturation of Full Dynamic range and data, one of (internal pattern disappears )
R/G/B is fixed at 192, and the other two is lowered to find
the desired value. (2) Adjustment Map
(3) Adj. condition: normal temperature Adj. item Command Data Range
- Surrounding Temperature: 25±5 °C (lower caseASCII) (Hex.)
- Warm-up time: About 5 Min CMD1 CMD2 MIN MAX
- Surrounding Humidity: 20% ~ 80%
- Before White balance adjustment, Keep power on status, Cool R Gain j g 00 C0
don’t power off G Gain j h 00 C0

B Gain j i 00 C0
5.1.1.2. Adj. condition and cautionary items
(1) Lighting condition in surrounding area surrounding lighting Medium R Gain j a 00 C0
should be lower 10 lux. Try to isolate adj. area into dark G Gain j b 00 C0
surrounding.
B Gain j c 00 C0
(2) Probe location: Color Analyzer (CA-210) probe should be
within 10cm and perpendicular of the module surface Warm R Gain j d 00 C0
(80°~ 100°) G Gain j e 00 C0
(3) Aging time
B Gain j f 00 C0
- A fter Aging Start, Keep the Power ON status during 5
Minutes.
- In case of LCD, Back-light on should be checked using no 5.1.5. Adjustment method
signal or Full-white pattern. 5.1.5.1. Auto WB calibration
(1) Set TV in ADJ mode using P-ONLY key (or POWER ON
5.1.2. Equipment key)
(1) Color Analyzer: CA-210 (NCG: CH 9 / WCG: CH12 / LED: (2) Place optical probe on the center of the display
CH14) - It need to check probe condition of zero calibration before
(2) A dj. Computer (During auto adj., RS-232C protocol is adjustment.
needed) (3) Connect RS-232C Cable
(3) Adjust Remocon (4) Select mode in ADJ Program and begin a adjustment.
(4) V ideo Signal Generator MSPG-925F 720p/204-Gray (5) When WB adjustment is completed with OK message,
(Model: 217, Pattern: 49) check adjustment status of pre-set mode (Cool, Medium,
※ Color Analyzer Matrix should be calibrated using CS-1000 Warm)
(6) Remove probe and RS-232C cable.
▪ W/B Adj. must begin as start command “wb 00 00” , and
5.1.3. Equipment connection finish as end command “wb 00 ff”, and Adj. offset if need

Copyright © LG Electronics. Inc. All rights reserved. - 12 - LGE Internal Use Only
Only for training and service purposes
5.1.5.2. Manual adjustment 5.1.7. Reference (White balance table)
(1) Set TV in Adj. mode using POWER ON ▪ S tandard color coordinate and temperature using
(2) Z  ero Calibrate the probe of Color Analyzer, then place it on CA-210(CH-14) – by aging time
the center of LCD module within 10cm of the surface.. (1) Normal line in Korea (From January to February) LGD
(3) P  ress ADJ key -> EZ adjust using adj. R/C à 9. White- (LB5xxx, LB6xxx, LB7xxx, LB8xxx).
Balance then press the cursor to the right (KEY►). When
Cool Medium Warm
KEY(►) is pressed 206 Gray internal pattern will be Aging time
displayed. X Y X Y X Y
(Min)
(4) Adjust Cool modes 271 270 286 289 313 329
(i) F ix the one of R/G/B gain to 192 (default data) and
1 0-2 286 295 301 314 328 354
decrease the others.
(If G gain is adjusted over 172 and R and B gain less than 2 3-5 284 290 299 309 326 349
192 , Adjust is O.K.) 3 6-9 282 287 297 306 324 346
(ii) If G gain is less than 172,
Increase G gain by up to 172, and then increase R gain and 4 10-19 279 283 294 302 321 342
G gain same amount of increasing G gain. 5 20-35 276 278 291 297 318 337
(iii) If R gain or B gain is over 255, 6 36-49 274 275 289 294 316 334
R eadjust G gain less than 172, Conform to R gain is 255 or
B gain is 255 7 50-79 273 272 288 291 315 331
(5) Adjust two modes (Medium / Warm) Fix the one of R/G/B 8 80-119 272 271 287 290 314 330
gain to 192 (default data) and decrease the others. 9 Over 120 271 270 286 289 313 329
(6) Adj. is completed, Exit adjust mode using “EXIT” key on
Remote controller. ▪ S tandard color coordinate and temperature using
▪ If internal pattern is not available, use RF input. In EZ Adj. CA-210(CH-14) – by aging time
menu. 6.White Balance, you can select one of 2 Test-pattern: (2) Normal line (From March to December) : LGD
ON, OFF. Default is inner (ON). By selecting OFF, you can (LB5xxx, LB6xxx, LB7xxx, LB8xxx)
adjust using RF signal in 206 Gray pattern.
Cool Medium Warm
Aging time
5.1.6. Reference (White Balance Adj. coordinate and (Min)
X Y X Y X Y
color temperature) 271 270 286 289 313 329
▪ Luminance: 204 Gray, 80IRE
1 0-2 282 289 297 308 324 348
▪ Standard color coordinate and temperature using CS-1000
(over 26 inch) 2 3-5 281 287 296 306 323 346
Coordinate 3 6-9 279 284 294 303 321 343
Mode Temp △uv
X Y 4 10-19 277 280 292 299 319 339
Cool 0.271 0.270 13,000K 0.0000 5 20-35 275 277 290 296 317 336
Medium 0.286 0.289 9,300K 0.0000 6 36-49 274 274 289 293 316 333
Warm 0.313 0.329 6,500K 0.0000 7 50-79 273 272 288 291 315 331
8 80-119 272 271 287 290 314 330
▪ S tandard color coordinate and temperature using
9 Over 120 271 270 286 289 313 329
CA-210(CH 18) – ALEF
Coordinate ▪ S tandard color coordinate and temperature using
Mode Temp △uv
X Y CA-210(CH 14)
O/S Module (AUO, INX, Sharp, CSOT, BOE)
Cool 0.271±0.002 0.270±0.002 13,000K 0.0000
cool med warm
Medium 0.286±0.002 0.289±0.002 9,300K 0.0000
x y x y x y
Warm 0.313±0.002 0.329±0.002 6,500K 0.0000
spec 271 270 286 289 313 329
▪ S tandard color coordinate and temperature using target 278 280 293 299 320 339
CA-210(CH-14)
Coordinate
Mode Temp △uv
X Y
Cool 0.271±0.002 0.270±0.002 13,000K 0.0000
Medium 0.286±0.002 0.289±0.002 9,300K 0.0000
Warm 0.313±0.002 0.329±0.002 6,500K 0.0000

Copyright © LG Electronics. Inc. All rights reserved. - 13 - LGE Internal Use Only
Only for training and service purposes
5.2. Tool Option setting & Inspection per 5.3. Magic Motion remote controller Check
countries 5.3.1. Test equipment
▪ R F-remote controller for check, IR-KEY-CODE remote
5.2.1. Overview controller.
(1) Tool option selection is only done for models in Non-USA ▪ Check AA battery before test. A recommendation is that a
North America due to rating tester change battery every lots.
(2) Applied model: LA46B Chassis applied to CANADA and
MEXICO
5.3.2. Test
(1) Make pairing with TV set by pressing “Start key(Wheel
5.2.2. Country Group selection key)” on RCU.
(1) Press ADJ key on the Adj. R/C, and then select Country (2) Check a cursor on screen by pressing ‘Wheel key” of RCU
Group Menu (3) Stop paring with TV set by pressing “Back+ Home” key of
(2) Depending on destination, select US, then on the lower RCU
Country option, select US, CA, MX.
Selection is done using +, - KEY 5.3.3. Applied models
Chassis Model Name Magic RF receiver
5.2.3. Tool Option inspection
▪ Press Adj. key on the Adj. R/C, then select Tool option LA46B 32LB580B-UG Dongle

Model Tool 1 Tool 2 Tool 3 Tool 4 Tool 5 Tool 6 Tool 7 32/39/42/47/50/55LB5800-

UG
32LB580B-UG(Sharp) 6769 13329 33152 64070 4566 1353 41771
47/50/55/60LB6100-UG
32LB580B-UG(LGD) 625 13329 33152 64070 4310 1354 41771
32LB5800-UG 625 13329 33152 64070 4310 1353 41771 ※ Dongle Model : A n USB dongle-type receiver will be
39LB5800-UG 14963 13329 33152 64070 4566 1353 41771 supplied in form of accessory. So this
pairing test is not necessary for these
42LB5800-UG(LGD) 628 13329 33152 64070 4310 1433 41771 models
42LB5800-UG(AUO) 4724 13329 33152 64070 4310 1353 41771
47LB5800-UG 629 13329 33152 64070 4310 1353 41771 5.4. Wi-Fi MAC Address Check
50LB5800-UG(AUO) 4726 13329 33152 64070 4310 1353 41771 5.4.1. Using RS232 Command
50LB5800-UG(INX) 14966 13329 33152 64070 4310 1353 41771 Command Set ACK
55LB5800-UG(LGD) 631 13329 33152 64070 4310 1402 41771 Transmission [A][l][][Set ID][][20][Cr] [O][K][x] or [N][G]
55LB5800-UA(AUO) 4727 13329 33152 64070 4310 1353 41771
5.4.2. Check the menu on in-start
47LB6100-UG 677 13329 33152 64070 12502 1353 41771
50LB6100-UG(LGD) 678 13329 33152 64070 12502 1353 41771
50LB6100-UG(AUO) 4774 13329 33152 64070 12502 1353 41771
50LB6100-UG(INX) 15014 13329 33152 64070 12502 1353 41771
55LB6100-UG(LGD) 679 13329 33152 64070 12502 1402 41771
55LB6100-UG(AUO) 4775 13329 33152 64070 12502 1353 41771
60LB6100-UG 39592 13329 33152 64070 12502 1353 41771
65LB6190-UD 34467 13329 33152 64070 12502 1353 41771

※ Tool option can be reconstructed by Software

Copyright © LG Electronics. Inc. All rights reserved. - 14 - LGE Internal Use Only
Only for training and service purposes
5.5. HDMI ARC Function Inspection 5.6. HDMI MHL Function Inspection
5.5.1. Test equipment 5.6.1. Test method
- Optic Receiver Speaker (1) Insert the HDMI Cable to the HDMI MHL port from the
- MSHG-600 (SW: 1220 ↑) master equipment, HDMI3
- HDMI Cable (for 1.4 version) (2) Check the Green LED of Tester, and TV Display

5.5.2. Test method

(1) Insert the HDMI Cable to the HDMI ARC port from the
master equipment (HDMI1)

5.7. EYE-Q Green Function Inspection

Step 1) Turn on the TV..
Step 2) P ress 'EYE button' on the adjustment remote-
controller.
(2) Check the sound from the TV Set Step 3) Cover 'Eye Q sensor' on the front of set with your
hands, hold it for 6 seconds.
Step 4) Check "the Sensor Data" on the screen, make certain
that Data is below 10. If Data isn’t below 10 in 6
seconds, Eye Q sensor would be bad. You should
change Eye Q sensor.
Step 5) Uncover your hands from Eye Q sensor, hold it for 6
seconds.
Step 6) Check "Back Light(xxx)" on the screen, check data
increase . You should change Eye Q sensor

(3) Check the Sound from the Speaker or using AV & Optic
TEST program (It’s connected to MSHG-600)

* Remark: Inspect in Power Only Mode and check SW version

in a master equipment

5.8. Ship-out mode check (In-stop)

▪ After final inspection, press In-Stop key of the Adj. R/C and
check that the unit goes to Stand-by mode

Copyright © LG Electronics. Inc. All rights reserved. - 15 - LGE Internal Use Only
Only for training and service purposes
6. AUDIO output check 8. USB S/W Download
6.1. Audio input condition (optional, Service only)
(1) RF input: Mono, 1KHz sine wave signal, 100% Modulation (1) Put the USB Stick to the USB socket
(2) CVBS, Component: 1KHz sine wave signal (0.4Vrms) (2) Automatically detecting update file in USB Stick
(3) RGB PC: 1KHz sine wave signal (0.7Vrms) - If your downloaded program version in USB Stick is lower
than that of TV set, it didn’t work. Otherwise USB data is
6.2. Specification automatically detected.
(3) Show the message “Copying files from memory”
No Item Min Typ Max Unit Remark
1 Audio 9.0 10.0 12.0 W (1) Measurement
practical 8.5 8.9 9.9 Vrms condition
max Output, -E Q/AVL/Clear
L/R Voice: Off
(Distor- (2) Speaker (8Ω
tion=10% Impedance)
max Output)

(4) Updating is staring.

7. GND and HI-POT Test
7.1. GND & HI-POT auto-check preparation
(1) Check the POWER CABLE and SIGNAL CABE insertion
condition

7.2. GND & HI-POT auto-check

(1) Pallet moves in the station. (POWER CORD / AV CORD is
tightly inserted)
(2) Connect the AV JACK Tester.
(3) Controller (GWS103-4) on. (5) Updating Completed, The TV will restart automatically
(4) GND Test (Auto) (6) If your TV is turned on, check your updated version and
- If Test is failed, Buzzer operates. Tool option.
- If Test is passed, execute next process (Hi-pot test). * If downloading version is more high than your TV have, TV
(Remove A/V CORD from A/V JACK BOX) can lost all channel data. In this case, you have to channel
(5) HI-POT test (Auto) recover. If all channel data is cleared, you didn’t have a DTV/
- If Test is failed, Buzzer operates. ATV test on production line.
- If Test is passed, GOOD Lamp on and move to next process
automatically. * After downloading, TOOL OPTION setting is needed again.
(1) Push "IN-START" key in service remote controller.
7.3. Checkpoint (2) Select "Tool Option 1" and Push “OK” button.
(1) Test voltage (3) Punch in the number. (Each model has their number.)
- GND: 1.5KV/min at 100mA
- SIGNAL: 3KV/min at 100mA
(2) TEST time: 1 second
(3) TEST POINT
- GND Test = POWER CORD GND and SIGNAL CABLE GND.
- Hi-pot Test = POWER CORD GND and LIVE & NEUTRAL.
(4) LEAKAGE CURRENT: At 0.5mArms

Copyright © LG Electronics. Inc. All rights reserved. - 16 - LGE Internal Use Only
Only for training and service purposes
9. Optional adjustments
9.1. Manual White balance Adjustment
9.1.1. Adj. condition and cautionary items
(1) Lighting condition in surrounding area surrounding lighting
should be lower 10 lux. Try to isolate adj. area into dark
surrounding.
(2) Probe location: Color Analyzer (CA-210) probe should be
within 10cm and perpendicular of the module surface
(80°~ 100°)
(3) Aging time
i) After Aging Start, Keep the Power ON status during 5
Minutes.
ii) In case of LCD, Back-light on should be checked using no
signal or Full-white pattern.

9.1.2. Equipment
(1) Color Analyzer: CA-210 (NCG: CH 9 / WCG: CH12 / LED:
CH14)
(2) A dj. Computer (During auto adj., RS-232C protocol is
needed)
(3) Adjust Remocon
(4) V ideo Signal Generator MSPG-925F 720p/216-Gray
(Model: 217, Pattern: 78)

9.1.3. Adjustment
(1) Set TV in Adj. mode using POWER ON
(2) Zero Calibrate the probe of Color Analyzer, then place it on
the center of LCD module within 10cm of the surface.
(3) Press ADJ key -> EZ adjust using adj. R/C -> 6. White-
Balance then press the cursor to the right (KEY►). When
KEY(►) is pressed 216 Gray internal pattern will be
displayed.
(4) One of R Gain / G Gain / B Gain should be fixed at 192,
and the rest will be lowered to meet the desired value.
(5) Adj. is performed in COOL, MEDIUM, WARM 3 modes of
color temperature.

▪ If internal pattern is not available, use RF input. In EZ Adj.

menu 6.White Balance, you can select one of 2 Test-pattern:
ON, OFF. Default is inner(ON). By selecting OFF, you can
adjust using RF signal in 216 Gray pattern.

Copyright © LG Electronics. Inc. All rights reserved. - 17 - LGE Internal Use Only
Only for training and service purposes
Copyright ©
X_TAL DDR3 1600 X 16
27MHz (512MB X 2EA)
CI Slot
T/C/S2 Without ATV
800MHz
P_TS 800MHz DDR3 1600 X 16
Air/ P_TS
A B (256MB X 1EA)
Cable TUNER
R IF (+/-) T/C Demod

Only for training and service purposes

E (T/C/A)
Tuner : I2C 6 Analog Demod SYSTEM EEPROM
A P_TS I2C 5
P_TS (256Kb)
R
(H) USB1 OCP HDCP EEPROM
S (HDD) 2.5A I2C 1 (16Kb)
I USB
D USB2 OCP
USB3
DVB-S : I2C 4 E 1A eMMC
(4GB)

LG Electronics. Inc. All rights reserved.

LNB
51P
MHL 1A HDMI1 LVDS 41P
SIL1392 MHL 사용시 S HDMI
MHL : I2C 4 I HDMI2 MUX EPI 50P PM LEVEL
D I2C 2 50P IC SHIFTER
HDMI3 MTK A2
E I2S Out Audio AMP
I2C 1 (NTP7513)

- 18 -
H/P AMP
TI
AV/COMP CVBS/YPbPr I2C 1 LOCAL DIMMING

R UART BLUTOOTH
E
A IR IR / NFC
BLOCK DIAGRAM

R OPTIC SPDIF OUT

KEY KEY SUB
ASSY
LAN ETHERNET WIFI
USB_WIFI
LVDS Diagram LOGO LIGHT

Sub Micom
I2C 3 (RENESAS
R5F1000G)

X_TAL
32.768KHz

LGE Internal Use Only

 EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
400

420
410

900
310
521

540

121
530
LV1

820

120

Set + Stand
A10
A2
200

Copyright © LG Electronics. Inc. All rights reserved. - 19 - LGE Internal Use Only
Only for training and service purposes
 IC105
LGE2122[A2_M13]
+1.2V_MTK_CORE

L11 R15
VCCK_1 DVSS_24
N12 T15
+1.2V_MTK_CORE VCCK_2 DVSS_25
P12 U15
+3.3V_NORMAL VDD3V3 +1.2V_MTK_CORE 5600mA VCCK_3 DVSS_26
OPT OPT AG5 V15
60mA VCCK_4 DVSS_27
L501 OPT AH5 W15
BLM18PG121SN1D C527 C535 VCCK_5 DVSS_28
C513 AJ5 Y15
0.1uF 0.1uF VCCK_6 DVSS_29
C514 C517 C523 C520 C532 10uF AK5 AA15
C503 C505 C507 C508 VCCK_7 DVSS_30
10uF 10uF 0.1uF 0.1uF 0.1uF AL5 AB15
10uF 10uF 0.1uF 2.2uF VCCK_8 DVSS_31
AM5 T18
VCCK_9 DVSS_32
AN5 R16
VCCK_10 DVSS_33
AK6 T16
VCCK_11 DVSS_34
AL6 U16
VCCK_12 DVSS_35
AM6 V16
VCCK_13 DVSS_36
AN6 W16
VCCK_14 DVSS_37
M11 Y16
VCCK_15 DVSS_38
N11 AA16
VCCK_16 DVSS_39
P11 AB16
VCCK_17 DVSS_40
R11 R17
VCCK_18 DVSS_41
M12 T17
VCCK_19 DVSS_42
R12 U17
VCCK_20 DVSS_43
L13 V17
VCCK_21 DVSS_44
L14 Y17
+3.5V_ST_WAKE VCCK_22 DVSS_45
VDD3V3 L15 N16
AVDD_33SB VCCK_23 DVSS_46
L17 V18
VCCK_24 DVSS_47
L18 Y18
OPT VCCK_25 DVSS_48
L19 P16
L503 VCCK_26 DVSS_49
BLM18PG121SN1D T11 V19
VCCK_27 DVSS_50
U11 Y19
VCCK_28 DVSS_51
V11 W17
VCCK_29 DVSS_52
OPT W11 AA17
+1.2V_MTK_CORE +1.2V_MTK_AVDD VCCK_30 DVSS_53
L502 Y11 AB17
BLM18PG121SN1D VCCK_31 DVSS_54
L504 AA11 N19
BLM18PG121SN1D VCCK_32 DVSS_55
AB11 AC14
OPT VCCK_33 DVSS_56
AC11 C13
C504 C506 C518 VCCK_34 DVSS_57
R23 K24
0.1uF 0.1uF 10uF VCCK_35 DVSS_58
L12 K25
VCCK_36 DVSS_59
W12 L24
VCCK_37 DVSS_60
V23 M17
VCCK_38 DVSS_61
Y12 M18
VCCK_39 DVSS_62
AF6 M19
VCCK_40 DVSS_63
AG6 P17
VCCK_41 DVSS_64
AH6 P19
VCCK_42 DVSS_65
AJ6 N18
VCCK_43 DVSS_66
AE7 U20
VCCK_44 DVSS_67
POWER_ON/OFF1 AF7 V20
VCCK_45 DVSS_68
AVDD_33SB TP500 AG7 W20
VCCK_46 DVSS_69
IC500 AD8 Y20
+3.5V_ST +3.5V_ST_WAKE VCCK_47 DVSS_70
+3.5V_ST_WAKE AP2121N-3.3TRE1 AE8 AA20
VCCK_48 DVSS_71
AF8 R19
VCCK_49 DVSS_72
VIN 3 2 VOUT AE9 T19
VCCK_50 DVSS_73
Q501 AC10 M20
1 VCCK_51 DVSS_74
PMV48XP AD10 N20
GND VCCK_52 DVSS_75
S

AD11 U21
C512 VCCK_53 DVSS_76
C510 1uF AE10 V21
0.1uF VCCK_54 DVSS_77
10V AF9 W21
G 16V VCCK_55 DVSS_78
AG8 Y21
C502
R502

VCCK_56 DVSS_79
10K

C501 0.1uF AH7 AA21

4.7uF VCCK_57 DVSS_80
ZD500

16V AJ7 P20

5V

10V VCCK_58 DVSS_81

OPT AK7 R20
OPT

VCCK_59 DVSS_82
AL7 T20
+3.3V_NORMAL VCCK_60 DVSS_83
3.3V_EMMC LAN_JACK_POWER AM7 U22
VCCK_61 DVSS_84
AN7 V22
VCCK_62 DVSS_85
L16 W22
VCCK_63 DVSS_86
TP501 V12 Y22
L505 VCCK_64 DVSS_87
BLM18PG121SN1D U12 AA22
1.8K
R501

VCCK_65 DVSS_88
T12 N21
VCCK_66 DVSS_89
AD13 P21
VCCK_67 DVSS_90
C531 AD17 R21
0.1uF VCCK_68 DVSS_91
C AD14 T21
R500 16V VDD3V3 VCCK_69 DVSS_92
10K B Q500 AB12 M22
WOL_CTL VCCK_70 DVSS_93
MMBT3904(NXP) AA12 N22
VCCK_71 DVSS_94
AC12 P22
C500 E VCCK_72 DVSS_95
4.7uF R22
DVSS_96
10V T22
OPT DVSS_97
T9 M21
VCC3IO_C DVSS_98
Y10 AC17
VCC3IO_B_1 DVSS_99
AA10 AA19
VCC3IO_B_2 DVSS_100
D22 M13
VCC3IO_A_1 DVSS_101
E22 M14
VCC3IO_A_2 DVSS_102
M15
DVSS_103
AA13
DVSS_104
AC18 AB13
DVSS_1 DVSS_105
AB21 AA14
DVSS_2 DVSS_106
AB14 AB19
DVSS_3 DVSS_107
N13 D6
DVSS_4 DVSS_108
P13 W19
DVSS_5 DVSS_109
R13 U19
DVSS_6 DVSS_110
T13 N17
DVSS_7 DVSS_111
DECAP FOR SOC (HIDDEN - UCC) DECAP FOR SOC Rework (BOTTOM) U13 L3
DVSS_8 DVSS_112
V13 AB18
DVSS_9 DVSS_113
W13 AA18
DVSS_10 DVSS_114
Y13 W18
DVSS_11 DVSS_115
P18 U18
DVSS_12 DVSS_116
N14 D16
DVSS_13 DVSS_117
P14 AC13
+1.2V_MTK_CORE VDD3V3 DVSS_14 DVSS_118
R14 M16
DVSS_15 DVSS_119
T14 AC20
DVSS_16 DVSS_120
U14 AC22
TP502

DVSS_17 DVSS_121
V14 AD20
TP503

DVSS_18 DVSS_122
W14 Y23
DVSS_19 DVSS_123
Y14 AA23
DVSS_20 DVSS_124
R18 AB23
DVSS_21 DVSS_125
N15 V24
DVSS_22 DVSS_126
P15 W23
DVSS_23 DVSS_127

+1.5V_DDR

OPT
+1.5V_DDR OPT
C539 C541
0.1uF 0.1uF
16V

C509 C511
0.1uF 0.1uF

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS MID_MAIN_3 2011.12.09
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 10
 DDR_512MB_SS
DDR_512MB_SS

IC701 IC703
+1.5V_DDR
K4B4G1646B-HCK0 K4B4G1646B-HCK0
A_RVREF2
ARA[0-14] +1.5V_DDR
A_RVREF4
A_RVREF1 ARA[0-14] +1.5V_DDR
C713 ARA[0] N3 M8
R706 M8 N3 ARA[0]
1K 0.1uF A0 VREFCA A_RVREF2
VREFCA A0 ARA[1] ARA[1] P7 C735
1% P7 R720
ARA[2] P3 A1 A_RVREF3 1K 0.1uF
A_RVREF1 A1 ARA[2]
P3 A2 1% C705 C707
A2 ARA[3] ARA[3] N2 H1 1uF 10uF
H1 N2 A3 VREFDQ
R707 VREFDQ A3 ARA[4] P8 10V
1K C714 P8 ARA[4]
1% ARA[5] P2 A4 1% R721
0.1uF 1% A4 ARA[5] 240
P2 A5 R716 1K C736
R710 240 A5 ARA[6] ARA[6] R8 L8 1% 0.1uF
L8 R8 A6 ZQ
ZQ A6 ARA[7] ARA[7] R2
R2 +1.5V_DDR
+1.5V_DDR ARA[8] T8 A7
A7 ARA[8]
+1.5V_DDR T8 A8
A8 ARA[9] ARA[9] R3 B2
B2 R3 A9 VDD_1
VDD_1 A9 ARA[10] ARA[10] L7 D9 +1.5V_DDR +1.5V_DDR
D9 L7 A10/AP VDD_2
A_RVREF4 VDD_2 A10/AP ARA[11] ARA[11] R7 G7
C715 G7 R7 A11 VDD_3
R708 0.1uF VDD_3 A11 ARA[12] ARA[12] N7 K2
1K K2 N7 A12/BC VDD_4
1% VDD_4 A12/BC ARA[13] T3 K8 A_RVREF3 C733
K8 T3 ARA[13] C704
ARA[14] A13 VDD_5 R718 0.1uF C745 C751 C753 C755 C754 C702
VDD_5 A13 ARA[14] T7 N1 1K 0.1uF 1uF 10uF
N1 T7 A14 VDD_6 1% 0.1uF 0.1uF 0.1uF 0.1uF
VDD_6 A14 M7 N9 10V
R709 N9 M7 A15 VDD_7
1K C716 VDD_7 A15 R1
1% 0.1uF R1 VDD_8
VDD_8 M2 R9 R719
R9 M2 ARBA0 BA0 VDD_9 1K C734
VDD_9 BA0 ARBA0 N8 1%
N8 ARBA1 0.1uF
ARBA1 ARCLK1 BA1
BA1 M3
M3 ARBA2 BA2
BA2 ARBA2 ARCLK0 A1
A1 VDDQ_1
VDDQ_1 J7 A8
A8 J7 R714 CK VDDQ_2
VDDQ_2 CK R712 100 K7 C1
C1 K7 100 5% CK VDDQ_3
VDDQ_3 CK 5% K9 C9
C9 K9 ARCKE CKE VDDQ_4
VDDQ_4 CKE ARCKE D2
D2 VDDQ_5
VDDQ_5 /ARCLK0 /ARCLK1 L2 E9
E9 L2 /ARCSX CS VDDQ_6
VDDQ_6 CS /ARCS K1 F1
F1 K1 ARODT ODT VDDQ_7
VDDQ_7 ODT ARODT J3 H2
H2 J3 /ARRAS RAS VDDQ_8
VDDQ_8 RAS /ARRAS K3 H9
H9 K3 /ARCAS CAS VDDQ_9
VDDQ_9 CAS /ARCAS L3
L3 /ARWE WE
WE /ARWE J1
J1 NC_1
NC_1 T2 J9
J9 T2 ARREST RESET NC_2
NC_2 RESET ARREST L1
L1 NC_3
NC_3 L9
L9 NC_4
NC_4 F3
F3 ARDQS2 DQSL
DQSL ARDQS0 G3
G3 /ARDQS2 DQSL
DQSL /ARDQS0
C7 A9
A9 C7 ARDQS3 DQSU VSS_1
VSS_1 DQSU ARDQS1 B7 B3 IC703-*3
B3 B7 /ARDQS3 DQSU VSS_2
IC701-*1
H5TQ4G63AFR-PBC
IC703-*1
H5TQ4G63AFR-PBC
IC701-*2
MT41K256M16HA-125:E
IC703-*2
MT41K256M16HA-125:E
IC701-*3
MT41K128M16JT-125:K
MT41K128M16JT-125:K
IC105
VSS_2 DQSU /ARDQS1 E1 LGE2122[A2_M13]
DDR_256MB_MICRON
DDR_512MB_MICRON DDR_256MB_MICRON
DDR_512MB_Hynix DDR_512MB_Hynix DDR_512MB_MICRON N3 M8
E1 VSS_3
N3
P7
A0 VREFCA
M8
N3
P7
A0 VREFCA
M8
N3
P7
A0 VREFCA
M8 N3
P7
A0 VREFCA
M8 N3
P7
A0 VREFCA
M8
P7
P3
A0
A1
VREFCA

VSS_3 E7 G8 P3
A1
A2 P3
A1
A2
P3
A1
A2
P3
A1
A2
P3
A1
A2 N2
A2
A3 VREFDQ
H1

G8 E7 ARDQM2 DML VSS_4

N2
P8
A3 VREFDQ
H1
N2
A3 VREFDQ
H1
N2
P8
A3 VREFDQ
H1 N2
P8
A3 VREFDQ
H1 N2
P8
A3 VREFDQ
H1
P8
A4

VSS_4 DML ARDQM0 ARDQ[16-23] D3 J2

P2
R8
A4
A5
L8
P8
P2
A4
A5
P2
R8
A4
A5
L8
P2
R8
A4
A5
L8
P2
R8
A4
A5
L8
P2
R8
A5
A6 ZQ
L8 +1.5V_DDR
J2 D3 ARDQM3 DMU VSS_5 R2
A6
A7
ZQ R8
R2
A6
A7
ZQ
L8
R2
A6
A7
ZQ
R2
A6
A7
ZQ
R2
A6
A7
ZQ R2
T8
A7
A8
+1.5V_DDR
VSS_5 DMU ARDQM1 J8
T8
R3
A8
A9 VDD_1
B2
T8
R3
A8
B2
T8
R3
A8
A9 VDD_1
B2
T8
R3
A8
A9 VDD_1
B2
T8
R3
A8
A9 VDD_1
B2
R3
L7
A9 VDD_1
B2
D9
J8 VSS_6
L7
A10/AP VDD_2
D9
L7
A9 VDD_1
D9
L7
A10/AP VDD_2
D9 L7
A10/AP VDD_2
D9 L7
A10/AP VDD_2
D9
R7
A10/AP VDD_2
G7
R1 D12
VSS_6 ARDQ[0-7] ARDQ[16] E3 M1
R7
N7
A11 VDD_3
G7
K2
R7
A10/AP
A11
VDD_2
VDD_3
G7
R7
N7
A11 VDD_3
G7
K2
R7
N7
A11 VDD_3
G7
K2
R7
N7
A11 VDD_3
G7
K2
N7
A11
A12/BC
VDD_3
VDD_4
K2

ARDQM0
M1 E3 ARDQ[0] T3
A12/BC VDD_4
K8
N7
T3
A12/BC VDD_4
K2
K8
T3
A12/BC VDD_4
K8 T3
A12/BC VDD_4
K8 T3
A12/BC VDD_4
K8
T3
A13 VDD_5
K8
N1
DDRV_1 ARDQM0
ARDQ[17] DQL0 VSS_7 T7
A13
A14
VDD_5
VDD_6
N1
T7
A13 VDD_5
N1
A13 VDD_5
VDD_6
N1
A13 VDD_5
VDD_6
N1
A13 VDD_5
VDD_6
N1
M7
VDD_6
N9 R2 D14
VSS_7 DQL0 ARDQ[1] F7 M9
M7
A15 VDD_7
N9
R1
M7
A14
A15
VDD_6
VDD_7
N9
M7
NC_5 VDD_7
N9
R1
M7
NC_5 VDD_7
N9
R1
M7
NC_5 VDD_7
N9
R1
NC_5 VDD_7
VDD_8
R1
RVREF_A C746 DDRV_2 ARDQS0 ARDQS0
M9 F7 DQL1 VSS_8 M2
BA0
VDD_8
VDD_9
R9
M2
VDD_8
R1
R9
M2
BA0
VDD_8
VDD_9
R9 M2
BA0
VDD_8
VDD_9
R9 M2
BA0
VDD_8
VDD_9
R9
M2
N8
BA0 VDD_9
R9

R730 R3 C14
VSS_8 DQL1 ARDQ[18] F2 P1
N8
BA1 N8
BA0 VDD_9 N8
BA1
N8
BA1
N8
BA1 M3
BA1
0.1uF /ARDQS0 ARDQ[0-7]
P1 F2 ARDQ[2] M3
BA2
A1
M3
BA1
BA2
M3
BA2
A1
M3
BA2
A1
M3
BA2
A1
BA2
VDDQ_1
A1
1K DDRV_3 ARDQS0 ARDQ[0]
ARDQ[19] DQL2 VSS_9 J7
VDDQ_1
A8
J7
VDDQ_1
A1
A8
J7
VDDQ_1
A8 J7
VDDQ_1
A8 J7
VDDQ_1
A8
J7
K7
CK VDDQ_2
A8
C1 1% R4 B17
VSS_9 DQL2 ARDQ[3] F8 P9 K7
CK
CK
VDDQ_2
VDDQ_3
C1
K7
CK
CK
VDDQ_2
VDDQ_3
C1
K7
CK
CK
VDDQ_2
VDDQ_3
C1 K7
CK
CK
VDDQ_2
VDDQ_3
C1 K7
CK
CK
VDDQ_2
VDDQ_3
C1
K9
CK
CKE
VDDQ_3
VDDQ_4
C9
DDRV_4 ARDQ0 ARDQ[1]
P9 F8 DQL3 VSS_10
K9
CKE VDDQ_4
C9
D2
K9
CKE VDDQ_4
C9
K9
CKE VDDQ_4
C9
D2
K9
CKE VDDQ_4
C9
D2
K9
CKE VDDQ_4
C9
D2 VDDQ_5
D2
R5 D10
VSS_10 DQL3 ARDQ[20] H3 T1
L2
VDDQ_5
E9
L2
VDDQ_5
D2
E9
L2
VDDQ_5
E9 L2
VDDQ_5
E9 L2
VDDQ_5
E9
L2
K1
CS VDDQ_6
E9
F1

T1 H3 ARDQ[4] K1
CS
ODT
VDDQ_6
VDDQ_7
F1
K1
CS VDDQ_6
F1
K1
CS
ODT
VDDQ_6
VDDQ_7
F1 K1
CS
ODT
VDDQ_6
VDDQ_7
F1 K1
CS
ODT
VDDQ_6
VDDQ_7
F1
J3
ODT VDDQ_7
H2 DDRV_5 ARDQ1 ARDQ[2]
ARDQ[21] DQL4 VSS_11 J3
K3
RAS VDDQ_8
H2
H9
J3
ODT
RAS
VDDQ_7
VDDQ_8
H2
J3
K3
RAS VDDQ_8
H2
H9
J3
K3
RAS VDDQ_8
H2
H9
J3
K3
RAS VDDQ_8
H2
H9
K3
RAS
CAS
VDDQ_8
VDDQ_9
H9
K3 C17
VSS_11 DQL4 ARDQ[5] H8 T9 L3
CAS
WE
VDDQ_9 K3
L3
CAS VDDQ_9
H9
L3
CAS
WE
VDDQ_9
L3
CAS
WE
VDDQ_9
L3
CAS
WE
VDDQ_9 L3
WE
J1
R731 DDRV_6 ARDQ2 ARDQ[3]
T9 H8 DQL5 VSS_12 NC_1
J1 WE
NC_1
J1 NC_1
J1
NC_1
J1
NC_1
J1
T2
RESET
NC_1
NC_2
J9
1K C747 R6 C10
VSS_12 DQL5 ARDQ[22] G2
T2
RESET NC_2
J9
L1
T2
RESET NC_2
J9
T2
RESET NC_2
J9
L1
T2
RESET NC_2
J9
L1
T2
RESET NC_2
J9
L1 NC_3
L1

G2 ARDQ[6] NC_3
L9 NC_3
L1
L9
NC_3
L9
NC_3
L9
NC_3
L9
F3
NC_4
L9
T7 1% 0.1uF DDRV_7 ARDQ3 ARDQ[4]
ARDQ[23] DQL6 F3
DQSL
NC_4
F3
NC_4 F3
DQSL
NC_4
A14
T7 F3
DQSL
NC_4
A14
T7 F3
DQSL
NC_4
NC_6
T7
G3
DQSL NC_6
L8 C18
DQL6 ARDQ[7] ARDQ[24-31] H7
G3
DQSL G3
DQSL
DQSL
G3
DQSL
G3
DQSL
G3
DQSL
DQSL

DDRV_8 ARDQ4 ARDQ[5]

H7 DQL7 C7
B7
DQSU VSS_1
A9
B3
C7
DQSU VSS_1
A9
C7
B7
DQSU VSS_1
A9
B3
C7
B7
DQSU VSS_1
A9
B3
C7
B7
DQSU VSS_1
A9
B3
C7
B7
DQSU
DQSU
VSS_1
VSS_2
A9
B3
M8 B9
DQL7 B1 DQSU VSS_2
VSS_3
E1
B7
DQSU VSS_2
B3
E1
DQSU VSS_2
VSS_3
E1
DQSU VSS_2
VSS_3
E1
DQSU VSS_2
VSS_3
E1
E7
VSS_3
E1
G8
DDRV_9 ARDQ5 ARDQ[6]
B1 ARDQ[8-15] VSSQ_1
E7
DML VSS_4
G8
E7
DML
VSS_3
VSS_4
G8
E7
DML VSS_4
G8 E7
DML VSS_4
G8 E7
DML VSS_4
G8
D3
DML
DMU
VSS_4
VSS_5
J2
D17 E18
VSSQ_1 ARDQ[24] D7 B9
D3
DMU VSS_5
J2
J8
D3
DMU VSS_5
J2
D3
DMU VSS_5
J2
J8
D3
DMU VSS_5
J2
J8
D3
DMU VSS_5
J2
J8 VSS_6
J8

B9 D7 ARDQ[8] E3
VSS_6
M1
E3
VSS_6
J8
M1
E3
VSS_6
M1 E3
VSS_6
M1 E3
VSS_6
M1
E3
F7
DQ0 VSS_7
M1
M9
DDRV_10 ARDQ6 ARDQ[7]
ARDQ[25] DQU0 VSSQ_2 F7
DQL0
DQL1
VSS_7
VSS_8
M9
F7
DQL0 VSS_7
M9
F7
DQ0
DQ1
VSS_7
VSS_8
M9 F7
DQ0
DQ1
VSS_7
VSS_8
M9 F7
DQ0
DQ1
VSS_7
VSS_8
M9
F2
DQ1 VSS_8
P1 A19 D9
VSSQ_2 DQU0 ARDQ[9] C3 D1
F2
F8
DQL2 VSS_9
P1
P9
F2
DQL1
DQL2
VSS_8
VSS_9
P1
F2
F8
DQ2 VSS_9
P1
P9
F2
F8
DQ2 VSS_9
P1
P9
F2
F8
DQ2 VSS_9
P1
P9
F8
DQ2
DQ3
VSS_9
VSS_10
P9
DDRV_11 ARDQ7
D1 C3 DQU1 VSSQ_3 H3
DQL3
DQL4
VSS_10
VSS_11
T1
F8
H3
DQL3 VSS_10
P9
T1
H3
DQ3
DQ4
VSS_10
VSS_11
T1 H3
DQ3
DQ4
VSS_10
VSS_11
T1 H3
DQ3
DQ4
VSS_10
VSS_11
T1
H3
H8
DQ4 VSS_11
T1
T9

VSSQ_3 DQU1 ARDQ[26] C8 D8

H8
DQL5 VSS_12
T9
H8
DQL4 VSS_11
T9
H8
DQ5 VSS_12
T9 H8
DQ5 VSS_12
T9 H8
DQ5 VSS_12
T9
G2
DQ5 VSS_12

D8 C8 ARDQ[10] G2
H7
DQL6 G2
DQL5
DQL6
VSS_12 G2
H7
DQ6
G2
H7
DQ6
G2
H7
DQ6 H7
DQ6
DQ7

ARDQ[27] DQU2 VSSQ_4 DQL7

B1
H7
DQL7
B1
DQ7
B1
DQ7
B1
DQ7
B1
D7
VSSQ_1
B1
B9 J22 C15
VSSQ_4 DQU2 ARDQ[11] C2 E2 D7
DQU0
VSSQ_1
VSSQ_2
B9
D7
DQU0
VSSQ_1
VSSQ_2
B9
D7
DQ8
VSSQ_1
VSSQ_2
B9 D7
DQ8
VSSQ_1
VSSQ_2
B9 D7
DQ8
VSSQ_1
VSSQ_2
B9
C3
DQ8
DQ9
VSSQ_2
VSSQ_3
D1
TP700 MEMTP ARDQM1 ARDQM1
E2 C2 DQU3 VSSQ_5
C3
C8
DQU1 VSSQ_3
D1
D8
C3
DQU1 VSSQ_3
D1
C3
C8
DQ9 VSSQ_3
D1
D8
C3
C8
DQ9 VSSQ_3
D1
D8
C3
C8
DQ9 VSSQ_3
D1
D8
C8
DQ10 VSSQ_4
D8
K22 A13
VSSQ_5 DQU3 ARDQ[28] A7 E8
C2
DQU2 VSSQ_4
E2
C8
C2
DQU2 VSSQ_4
D8
E2
C2
DQ10 VSSQ_4
E2 C2
DQ10 VSSQ_4
E2 C2
DQ10 VSSQ_4
E2
C2
A7
DQ11 VSSQ_5
E2
E8
TP701 ARDQS1
E8 A7 ARDQ[12] A7
DQU3
DQU4
VSSQ_5
VSSQ_6
E8
A7
DQU3 VSSQ_5
E8
A7
DQ11
DQ12
VSSQ_5
VSSQ_6
E8 A7
DQ11
DQ12
VSSQ_5
VSSQ_6
E8 A7
DQ11
DQ12
VSSQ_5
VSSQ_6
E8
A2
DQ12 VSSQ_6
F9 MEMTN ARDQS1
ARDQ[29] DQU4 VSSQ_6 A2
B8
DQU5 VSSQ_7
F9
G1
A2
DQU4
DQU5
VSSQ_6
VSSQ_7
F9
A2
B8
DQ13 VSSQ_7
F9
G1
A2
B8
DQ13 VSSQ_7
F9
G1
A2
B8
DQ13 VSSQ_7
F9
G1
B8
DQ13
DQ14
VSSQ_7
VSSQ_8
G1 RVREF_A B13 ARDQ[8-15]
VSSQ_6 DQU4 ARDQ[13] A2 F9 A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G9
B8
A3
DQU6 VSSQ_8
G1
G9
A3
DQ14
DQ15
VSSQ_8
VSSQ_9
G9 A3
DQ14
DQ15
VSSQ_8
VSSQ_9
G9 A3
DQ14
DQ15
VSSQ_8
VSSQ_9
G9
A3
DQ15 VSSQ_9
G9

ARDQS1 /ARDQS1
ARDQ[8]
F9 A2 DQU5 VSSQ_7
DQU7 VSSQ_9
B11
VSSQ_7 DQU5 ARDQ[30] B8 G1
G1 B8 ARDQ[14] ARDQ8 ARDQ[9]
ARDQ[31] DQU6 VSSQ_8 D18 B16
VSSQ_8 DQU6 ARDQ[15] A3 G9 RVREF_A ARDQ9 ARDQ[10]
G9 A3 DQU7 VSSQ_9 A11
VSSQ_9 DQU7 ARDQ10 ARDQ[11]
A17
ARDQ11 ARDQ[12]
G8 C12
ARCKE ARCKE ARDQ12 ARDQ[13]
A16
ARDQ13 ARDQ[14]
B5 C11
ARCLK1 ARCLK1 ARDQ14 ARDQ[15]
A5 C16
/ARCLK1 ARCLK1 ARDQ15

B14 A3
ARCLK0 ARCLK0 ARDQM2 ARDQM2
A14 D5
/ARCLK0 ARCLK0 ARDQS2 ARDQS2
C5
ARDQS2 /ARDQS2
ARDQ[16] ARDQ[16-23]
F13 E7
ARODT ARODT ARDQ16 ARDQ[17]
E13 B2
/ARRAS ARRAS ARDQ17 ARDQ[18]
G13 C8
/ARCAS ARCAS ARDQ18 ARDQ[19]
G15 B1
/ARCS ARCS ARDQ19 ARDQ[20]
H18 A9
/ARWE ARWE ARDQ20 ARDQ[21]
C1
ARDQ21 ARDQ[22]
G16 C9
ARREST ARRESET ARDQ22 ARDQ[23]
C3
+1.5V_DDR ARDQ23
D15
ARBA0 ARBA0
F9 C6
ARBA1 ARBA1 ARDQM3 ARDQM3
G18 A4
ARBA2 ARBA2 ARDQS3 ARDQS3
C703 C701 B4 ARDQ[24-31]
C718 C720 C722 C726 C728 ARDQS3 /ARDQS3
1uF 10uF F15 A1 ARDQ[24]
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
10V /ARCSX ARCSX ARDQ24 ARDQ[25]
B7
ARA[14] ARDQ25 ARDQ[26]
D11 C4
ARA[13] ARA14 ARDQ26 ARDQ[27]
F16 C7
ARA[12] ARA13 ARDQ27 ARDQ[28]
D8 B3
ARA[11] ARA12 ARDQ28 ARDQ[29]
E11 A7
ARA[10] ARA11 ARDQ29 ARDQ[30]
G9 A2
ARA[9] ARA10 ARDQ30 ARDQ[31]
E16 D7
+1.5V_DDR ARA[8] ARA9 ARDQ31
F11
ARA8 VDD3V3
ARA[7] G17
ARA[6] ARA
F10 A20
ARA[5] ARA6 AVDD33_MEMPLL
C717 C719 C750 C723 C725 C727 C706 C708 E17 H9
1uF 10uF ARA[4] ARA5 AVSS33_MEMPLL
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF E10
10V ARA[3] ARA4
E15 C700
ARA[2] ARA3 0.1uF
F17
ARA[1] ARA2
G10
ARA[0] ARA1
F18
ARA0
ARA[0-14]

IC702
MT41K128M16JT-125:K
+1.5V_DDR B_RVREF6 IC702-*1 IC702-*2 IC702-*3
IC105
DDR_256MB_MICRON BRA[0-14] K4B2G1646E-BCK0 H5TQ2G63DFR-PBC H5TQ2G63FFR-PBC LGE2122[A2_M13]
M8 N3 BRA[0] DDR_256MB_SS DDR_256MB_HYNIX_NC4.0 DDR_256MB_HYNIX_NC4.5 +1.5V_DDR RVREF_C
B_RVREF5 C709 VREFCA A0 BRA[1] N3 M8 N3 M8 N3
A0 VREFCA
M8
P7 P7
A0 VREFCA
P7
A0 VREFCA P7
R702 0.1uF A1 P3
A1 A1 P3
A1

1K B_RVREF5 P3 BRA[2] N2
A2
H1
P3
A2 N2
A2
H1
N2 H1
1% A2 A3 VREFDQ A3 VREFDQ P8
A3 VREFDQ
RVREF_C C2 L1
H1 N2 BRA[3] P8
A4
P8
A4 P2
A4 C741 RVREF_C BRDQM0 BRDQM0
P2
A5
P2
A5 A5 R726 0.1uF H2
VREFDQ A3 BRA[4] R8 L8 R8 L8 R8
A6 ZQ
L8
1K BRDQS0
P8 R2
A6 ZQ
R2
A6 ZQ R2
1% BRDQS0
A4 A7 A7 T8
A7 H1
R703 P2 BRA[5] T8
A8
T8
A8 A8
BRDQS0 /BRDQS0 BRDQ[0-7]
1K C710 1% R3
A9 VDD_1
B2 R3
A9 VDD_1
B2 R3
A9 VDD_1
B2
J2 E2 BRDQ[0]
1% R711 240 A5 BRA[6] L7 D9 L7 D9 L7
A10/AP VDD_2
D9
BRCLK0
0.1uF L8 R8 R7
A10/AP VDD_2
G7 R7
A10/AP VDD_2
G7 R7 G7 BRCLK0 BRDQ0 BRDQ[1]
ZQ A6 A11 VDD_3 A11 VDD_3 N7
A11 VDD_3
K2 J1 N3
R2 BRA[7] N7
A12/BC VDD_4
K2 N7
A12/BC VDD_4
K2 A12/BC VDD_4 R727 /BRCLK0 BRCLK0 BRDQ1
+1.5V_DDR T3
A13 VDD_5
K8 T3
A13 VDD_5
K8 T3
A13 VDD_5
K8
1K C742 E1 BRDQ[2]
A7 BRA[8] N1 N1 VDD_6
N1
1%
T8 M7
VDD_6
N9 M7
VDD_6
N9 M7 N9 0.1uF BRDQ2 BRDQ[3]
A8 NC_5 VDD_7
R1 NC_5 VDD_7 NC_5 VDD_7
R1 N1
B2 R3 BRA[9] VDD_8 VDD_8
R1 VDD_8
BRDQ3
M2
BA0 VDD_9
R9 M2
BA0 VDD_9
R9 M2
BA0 VDD_9
R9
D1 BRDQ[4]
+1.5V_DDR VDD_1 A9 BRA[10] N8 N8 N8
BA1
D9 L7 M3
BA1
M3
BA1 M3 BRDQ4 BRDQ[5]
VDD_2 A10/AP BA2
A1 BA2 BA2
A1 P1
G7 R7 BRA[11] VDDQ_1 VDDQ_1
A1 VDDQ_1
BRDQ5
J7
CK VDDQ_2
A8 J7
CK VDDQ_2
A8 J7
CK VDDQ_2
A8
L6 D2 BRDQ[6]
VDD_3 A11 BRA[12] K7 C1 K7 C1 K7
CK VDDQ_3
C1
BRCKE
B_RVREF6 K2 N7 K9
CK VDDQ_3
C9 K9
CK VDDQ_3
C9 K9 C9 BRCKE BRDQ6 BRDQ[7]
C711 VDD_4 A12/BC CKE VDDQ_4
D2 CKE VDDQ_4 CKE VDDQ_4
D2 N2
R704 K8 T3 BRA[13] VDDQ_5 VDDQ_5
D2
L2
VDDQ_5
E9 BRDQ7
1K 0.1uF L2
CS VDDQ_6
E9 L2
CS VDDQ_6
E9 CS VDDQ_6 E3
VDD_5 A13 K1 F1 K1 F1 K1
ODT VDDQ_7
F1
BRODT
1% N1 J3
ODT VDDQ_7
H2 J3
ODT VDDQ_7
H2 J3 H2 BRODT
VDD_6 K3
RAS VDDQ_8
H9 K3
RAS VDDQ_8
H9 K3
RAS VDDQ_8
H9 L4 H3
N9 M7 L3
CAS VDDQ_9
L3
CAS VDDQ_9 L3
CAS VDDQ_9 /BRRAS BRRAS BRDQM1 BRDQM1
VDD_7 NC_5 BRA[15] WE
J1 WE
J1
WE
J1 D3 K1
R1 T2
NC_1
J9 T2
NC_1
J9 T2
NC_1
J9 /BRCAS BRCAS BRDQS1 BRDQS1
R705 VDD_8 RESET NC_2
L1 RESET NC_2
L1
RESET NC_2
L1 D4 K2 BRDQ[8-15]
1K C712 R9 M2 NC_3
L9 NC_3
L9
NC_3
L9 /BRCS BRCS BRDQS1 /BRDQS1
BRDQ[8]
1% VDD_9 BA0 BRBA0 NC_4 NC_4 F3
NC_4
T7 N4
0.1uF N8
F3
DQSL NC_6
T7 F3
DQSL NC_6
T7 DQSL NC_6
BRDQ8
G3 G3 G3
DQSL J4 F2 BRDQ[9]
BA1 BRBA1 DQSL DQSL
M3 C7 A9 C7 A9 C7 A9 BRBA0 BRBA0 BRDQ9 BRDQ[10]
BA2 BRBA2 BRCLK0 B7
DQSU VSS_1
B3 B7
DQSU VSS_1
B3 B7
DQSU VSS_1
B3 M6 M3
A1 DQSU VSS_2
E1 DQSU VSS_2
E1
DQSU VSS_2
E1 BRBA1 BRBA1 BRDQ10 BRDQ[11]
VDDQ_1 E7
VSS_3
G8 E7
VSS_3
G8 E7
VSS_3
G8 E4 F1
A8 J7 D3
DML VSS_4
J2 D3
DML VSS_4
J2 D3
DML VSS_4
J2 BRBA2 BRBA2 BRDQ11 BRDQ[12]
VDDQ_2 CK R713 DMU VSS_5
J8 DMU VSS_5
J8
DMU VSS_5
J8 L2
C1 K7 100 E3
VSS_6
M1 E3
VSS_6
M1 E3
VSS_6
M1 BRDQ12 BRDQ[13]
VDDQ_3 CK 5% F7
DQL0 VSS_7
M9 F7
DQL0 VSS_7
M9 F7
DQL0 VSS_7
M9 BRA[0-15] K4 F3
C9 K9 F2
DQL1 VSS_8
P1 F2
DQL1 VSS_8
P1 F2
DQL1 VSS_8
P1 /BRWE BRWE BRDQ13 BRDQ[14]
VDDQ_4 CKE BRCKE F8
DQL2 VSS_9
P9 F8
DQL2 VSS_9
P9 F8
DQL2 VSS_9
P9 M4
DQL3 VSS_10
D2 H3
DQL3 VSS_10
T1 H3
DQL3 VSS_10
T1 H3 T1
BRA[15] BRDQ14 BRDQ[15]
VDDQ_5 /BRCLK0 H8
DQL4 VSS_11
T9 H8
DQL4 VSS_11
T9 H8
DQL4 VSS_11
T9 J3 G3
DQL5 VSS_12
E9 L2 G2
DQL5 VSS_12
G2
DQL5 VSS_12 G2
BRA[14] BRA15 BRDQ15
VDDQ_6 CS /BRCS H7
DQL6
H7
DQL6 H7
DQL6 P4
DQL7
F1 K1 DQL7
B1 DQL7
B1 B1
BRA[13] BRA14
VDDQ_7 ODT BRODT D7
VSSQ_1
B9 D7
VSSQ_1
B9 D7
VSSQ_1
B9 G5
DQU0 VSSQ_2
H2 J3 C3
DQU0 VSSQ_2
D1 C3
DQU0 VSSQ_2
D1 C3 D1
BRA[12] BRA13
VDDQ_8 RAS /BRRAS C8
DQU1 VSSQ_3
D8 C8
DQU1 VSSQ_3
D8 C8
DQU1 VSSQ_3
D8 P6
DQU2 VSSQ_4
H9 K3 C2
DQU2 VSSQ_4
E2 C2
DQU2 VSSQ_4
E2 C2 E2
BRA[11] BRA12
VDDQ_9 CAS /BRCAS A7
DQU3 VSSQ_5
E8 A7
DQU3 VSSQ_5
E8 A7
DQU3 VSSQ_5
E8 P5
DQU4 VSSQ_6
L3 A2
DQU4 VSSQ_6
F9 A2
DQU4 VSSQ_6
F9 A2 F9
BRA[10] BRA11
WE /BRWE B8
DQU5 VSSQ_7
G1 B8
DQU5 VSSQ_7
G1 B8
DQU5 VSSQ_7
G1 L5
DQU6 VSSQ_8
J1 A3
DQU6 VSSQ_8
G9 A3
DQU6 VSSQ_8
G9 A3 G9
BRA[9] BRA10
NC_1 DQU7 VSSQ_9 DQU7 VSSQ_9 DQU7 VSSQ_9 F4
J9 T2 BRA[8] BRA9
NC_2 RESET BRREST P3
L1 BRA[7] BRA8
NC_3 H4
L9 BRA[6] BRA7
NC_4 P2
T7 F3 BRA[5] BRA6
BRA[14] NC_6 DQSL BRDQS0 K6
G3 BRA[4] BRA5
DQSL /BRDQS0 M5
BRA[3] BRA4
K5
A9 C7 BRA[2] BRA3
VSS_1 DQSU BRDQS1 G6
B3 B7 BRA[1] BRA2
VSS_2 DQSU /BRDQS1 N5
E1 BRA[0] BRA1
VSS_3 E5
G8 E7 BRA0
VSS_4 DML BRDQM0 +1.5V_DDR
J2 D3
VSS_5 DMU BRDQM1
J8
VSS_6 BRDQ[0-7] B19
M1 E3 BRDQ[0] DDRV_12
VSS_7 DQ0 C19
M9 F7 BRDQ[1] DDRV_13
VSS_8 DQ1 D19
P1 F2 BRDQ[2] DDRV_14
VSS_9 DQ2 E19
P9 F8 BRDQ[3] DDRV_15
VSS_10 DQ3 F19
T1 H3 BRDQ[4] DDRV_16
VSS_11 DQ4 G19
T9 H8 BRDQ[5] DDRV_17
VSS_12 DQ5 F5
G2 BRDQ[6] DDRV_18
DQ6 H5
H7 BRDQ[7] DDRV_19
DQ7 N8 G4
B1 DDRV_20 BRRESET BRREST
BRDQ[8-15] P8
VSSQ_1
B9 D7 BRDQ[8] DDRV_21
VSSQ_2 DQ8 D13
D1 C3 BRDQ[9] DDRV_22
VSSQ_3 DQ9 E8
D8 C8 BRDQ[10] DDRV_23
VSSQ_4 DQ10 G11
E2 C2 BRDQ[11] DDRV_24
VSSQ_5 DQ11 D20
E8 A7 BRDQ[12] DDRV_25
VSSQ_6 DQ12 E20
F9 A2 BRDQ[13] DDRV_26
VSSQ_7 DQ13 F20
G1 B8 BRDQ[14] DDRV_27
VSSQ_8 DQ14 G20
G9 A3 BRDQ[15] DDRV_28
VSSQ_9 DQ15 R7
DDRV_29
R8
DDRV_30
T5
DDRV_31
T6
DDRV_32
T7
DDRV_33
T8
DDRV_34

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2011.12.09
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. DDR ONE SIDE 12
 SPDIF

+3.3V_NORMAL

GND
SPDIF OUT
1

Fiber Optic

JST1223-001
JK3602
R3611 VCC
2.7K 2
R3610 OPT
33 VINPUT
3

SPDIF_OUT
C3602
4

0.1uF
FIX_POLE

16V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS JACK HIGH / MID 2011.11.21
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 36
 +3.5V_ST_WAKE
+3.5V_ST L4111
BLM18PG121SN1D
MAX 0.4A
WIFI

R4117 R4118
10K 10K
5% 5%
C4113 C4112
C4111
R4113 10uF 10uF 0.1uF
100 P4101
P4102 10V
KEY1 10V 16V
12507WR-08L
12507WR-10L WIFI WIFI WIFI
R4114 D4101
100 5.6V
KEY2
AMOTECH CO., LTD. GND For EMI
C4100 C4102 OPT 1
0.1uF 0.1uF
D4100
5.6V KEY1
+3.5V_ST AMOTECH CO., LTD. 2
OPT P4100
12507WR-06L
KEY2
3
L4100
WIFI
BLM18PG121SN1D +3.5V_ST
4 1

GND 2
C4104 R4125 10K 5 WIFI_DM
1000pF LED_R
50V LED_R
Place Near Micom LOGO/LED_R 3
+3.5V_ST 6 WIFI_DP
ZD4100 ZD4101
IR 4 ADLC 5S 02 015 ADLC 5S 02 015
7 WIFI_ESD WIFI_ESD TP4100 RTS

R4131 GND
10K

8 5 WOL/ETH_POWER_ON
R4133
OPT

22 NON_EYE_Q_8P 22
LOGO_LIGHT R4137 R4130
100 9 6 OPT
EYE_SCL 9
LOGO_LIGHT C
EYE_Q_10P D4105 WOL/WIFI_POWER_ON
B 7 22 M_REMOTE_RX
LOGO_LIGHT ADMC 5M 02 200L 10 R4136 TP4101
LOGO_LIGHT

1K Q4100
LOGO_LIGHT

R4138 OPT WIFI

R4134 EYE_Q_10P
R4132

E 100
C4120 LOGO_LIGHT MMBT3904(NXP) EYE_SDA 11
10K

0.1uF TP4102 M_REMOTE_TX

16V EYE_Q_10P D4106
ADMC 5M 02 200L
TP4103 M_RFModule_RESET
OPT
+3.5V_ST
TP4104 CTS

R4107
10K

IR
C4107 D4104 OPT
100pF 5.6V
50V AMOTECH CO., LTD.

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS IR / KEY 2011.11.21
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 41
 DEBUG FOR INTERNAL AMOD.

OPT
R3801
0

DTV/MNT_V_OUT_SOC
R3800
75
1%
For TU_Debug
TU_DEBUG Disconnet R374

AV/COMPONENT REAR

ADUC 5S 02 0R5L
UART FOR DEBUG
COMP1_Y/AV1_CVBS

ZD3804
+3.3V_NORMAL

OPT
Mold_AV NON_Mold_AV
PPJ245N2-01 PPJ245-01
JK3800-*1 JK3800 R3806
[GN]E-LUG 10K
7A
R3811
7A [GN/YL]E-LUG 1K
[GN]C-SPRING AV1_CVBS_DET
6A
UART_4PIN_STRAIGHT
6A [GN/YL]O-SPRING
+3.5V_ST P3800 [GN]CONTACT C3800
4A D3803 0.1uF
12507WS-04L 5.6V
4A [GN/YL]CONTACT 16V
[BL]C-SPRING AV_COMP_ESD
5B COMP1_Pb
5B [BL]O-SPRING +3.3V_NORMAL
1 [RD1]E-LUG-S
8C
8C [RD1]E-LUG-S
[RD1]C-SPRING R3810
2 6C COMP1_Pr 10K
SOC_RX
6C [RD1]O-SPRING R3812
[RD1]CONTACT 1K
4C COMP1_DET
3 4C [RD1]CONTACT
[WH]C-SPRING
5D COMP1/AV1/DVI_L_IN D3800
5D 5.6V
4 [WH]O-SPRING
SOC_TX
4E AV_COMP_ESD
D3801
4E [RD2]CONTACT [RD2]CONTACT 5.6V
5
6E AV_COMP_ESD
6E [RD2]O-SPRING [RD2]C-SPRING
7E
7E [RD2]E-LUG [RD2]E-LUG

COMP1/AV1/DVI_R_IN

D3802
5.6V
AV_COMP_ESD

Apply "AV_COMP_ESD" when your model’s ESD Test is failed

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS JACK_COMMON 2011.11.21
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 38
 L5404-*1
10.0uH
Audio_Coil_TAIYO
NRS6045T100MMGK

L5405-*1
10.0uH Audio_Coil_TAIYO
NRS6045T100MMGK

DUAL COMPONENT +3.3V_NORMAL AMP_RESET_N

L5402-*1
10.0uH Audio_Coil_TAIYO
C5415
1000pF
Q1801 50V NRS6045T100MMGK
1ST : 0TRIY80001A 2ND : 0TR387500AA

50V
L5401

22000pF
L5403-*1

C5416
BLM18PG121SN1D +24V_AMP
OPT 10.0uH Audio_Coil_TAIYO
AUD_MASTER_CLK R5406
3.3 NRS6045T100MMGK

+24V_AMP OPT
+24V
C5418 C5420 C5422 C5424
0.1uF 0.1uF 10uF 0.01uF
C5413 C5414 50V
50V 50V 35V
L5400
0.1uF
10uF
[EP]GND
VDD_IO
GND_IO

PGND1A

PVDD1A
PVDD1B
10V
UBW2012-121F 16V SPK_L+

CLK_I

RESET
BST1A

OUT1A
R5407 R5414
12 12 L5404
10uH C5436 R5415
Audio_Coil_ABCO 0.1uF

AD
C5400 C5401 C5411 C5429 50V 5.1K
0.1uF 0.1uF 0.1uF 390pF LPH6045T-100M
50V 50V 16V 50V C5434
L5405 0.47uF
C5430
10uH Audio_Coil_ABCO
50V
SPEAKER_L
390pF C5437
40
39
38
37
36
35
34
33
32
31
50V LPH6045T-100M 0.1uF R5416
50V
R5408 R5412 5.1K
AGND_PLL 1 30 OUT1B 12 12
SPK_L-
VDD_PLL 2 29 PGND1B C5425
THERMAL 22000pF
DGND_PLL 3 41 28 BST1B 50V WAFER-ANGLE

GND 4 27 VDR1
SPK_L+
4
OPT C5440 DGND 5 IC5400 26 VCC5
0.1uF C5412
1uF
16V 10V DVDD 6 NTP7513 25 AGND SPK_L-
3

AUD_LRCH
SDATA 7 24 VDR2 SPK_R+
2

WCK
0x54 BST2A
C5427
1uF
C5428
1uF
C5433
1uF
AUD_LRCK 8 23 10V 10V 10V SPK_R-
1

AUD_SCK
BCK 9 22 PGND2A C5426
22000pF P5400

I2C_SDA1
R5402 100 SDA 10 21 OUT2A 50V
11
12
13
14
15
16
17
18
19
20

R5403 100
I2C_SCL1
C5406 C5408
SCL
FAULT
MONITOR_0
MONITOR_1
MONITOR_2
BST2B
PGND2B
OUT2B
PVDD2B
PVDD2A

POWER_DET
33pF 33pF
SPK_R+
AMP_MUTE_PWR_DET

50V 50V

+3.3V_NORMAL
+24V_AMP
R5409 R5413
R5419 100

12 12 L5402
10uH Audio_Coil_ABCO C5438 R5417
AMP_MUTE_MICOM LPH6045T-100M 0.1uF 5.1K
R5401 C5431
10K 390pF C5435 50V
50V 0.47uF
R5405 100 C5419 C5421 C5423
L5403
10uH Audio_Coil_ABCO
50V
SPEAKER_R
AMP_MUTE_MICOM 0.1uF 0.1uF 10uF C5432
C C5404 390pF
50V 50V 50V LPH6045T-100M C5439 R5418
1000pF 35V
R5400 10K B C5417
AMP_MUTE Q5400 50V R5410 R5411 0.1uF 5.1K
AMP_MUTE_MICOM MMBT3904(NXP) 22000pF 12 12 50V
E AMP_MUTE_MICOM 50V
SPK_R-

[AMP_MUTE_PWR_DET]
-->For fixing AC-OFF POP noise 32"POLA/ROW model
-->32"POLA/ROW LPB’s 3.5st drop time is very fast

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS AMP_NEO 2011.11.21
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 54
 HP_OUT_H13 HP_OUT_H13

C6104-*1 C6109-*1

EARPHONE AMP 18pF

18pF

IC6100
TPA6138A2

HP_OUT_MTK +INR +INL HP_OUT_MTK

C6104 1 14 C6109
HP_OUT
C6100 180pF HP_OUT HP_OUT HP_OUT 180pF HP_OUT C6101
1uF R6100 R6106 R6104 R6101 1uF
-INR -INL HP_OUT
HP_OUT 10K
10V 43K HP_OUT 2 13
43K 10K 10V
HP_OUT
HP_ROUT_MAIN HP_LOUT_MAIN
R6103 1% C6108 C6106 1% R6102
33K 10pF OUTR OUTL 10pF 33K
HP_OUT_MTK 50V 3 12 50V HP_OUT_MTK HP_OUT_H13
HP_OUT_H13 HP_LOUT_AMP R6102-*1
R6103-*1 HP_ROUT_AMP 43K
+3.3V_NORMAL GND_1 UVP
43K 4 11 +3.3V_NORMAL
1%
1%

HP_OUT
MUTE GND_2
4.7K
HP_OUT

5 10 L6100
R6105
120-ohm
SIDE_HP_MUTE VSS VDD BLM18PG121SN1D
6 9
HP_OUT HP_OUT
HP_OUT
C6105 C6107
C6102 CN CP 1uF 0.1uF
1uF 7 8
10V 16V
10V

C6103
1uF
10V

HP_OUT

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. 2011.09.29
HEADPHONE AMP
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR 61
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
 LOCAL DIMMING
[To LED DRIVER]
P7600
12507WR-08L
L/DIM_OUT_8P

1 R7601
10K
L/DIM_OUT_8P
2

3 L/DIM0_SCLK_PWR

5 L/DIM0_MOSI_PWR
R7603
33
6 I2C_SCL1
L/DIM_OUT_8P
R7602
33
7 I2C_SDA1
L/DIM_OUT_8P

8 L/DIM0_VS_PWR

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LOCAL DIMMING 2011.12.13
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 76
 IC8100-*4
IC8100-*1 IC8100-*2 IC8100-*3
THGBM5G7A2JBAIR
THGBM5G5A1JBAIR H26M21001ECR KLM2G1HE3F-B001

A3 C8
A3 C8 A3 C8 A3 C8 DAT0 NC_23
DAT0 NC_23 DAT0 NC_25 DAT0 NC_25 A4 C9
A4 C9 A4 C9 A4 C9 DAT1 NC_24

eMMC I/F A5
B2
DAT1
DAT2
DAT3
NC_24
NC_25
NC_26
C10
C11
A5
B2
DAT1
DAT2
DAT3
NC_26
NC_27
NC_28
C10
C11
A5
B2
DAT1
DAT2
DAT3
NC_26
NC_27
NC_28
C10
C11
A5
B2
B3
DAT2
DAT3
NC_25
NC_26
C10
C11
C12
B3 C12 B3 C12 B3 C12 DAT4 NC_27
DAT4 NC_27 DAT4 NC_29 DAT4 NC_29 B4 C13
EMMC DATA LINE 47K PULL/UP 3.3V_EMMC B4 C13 B4 C13 B4 C13 DAT5 NC_28
DAT5 NC_28 DAT5 NC_30 DAT5 NC_30 B5 C14
B5 C14 B5 C14 B5 C14 DAT6 NC_29
47K
47K
47K
47K
47K

47K
47K
47K

DAT6 NC_29 DAT6 NC_31 DAT6 NC_31 B6 D1

B6 D1 B6 D1 B6 D1 DAT7 NC_30
DAT7 NC_30 DAT7 NC_32 DAT7 NC_32 D2
D2 D2 D2 NC_31
NC_31 NC_33 NC_33 D3
D3 D3 D3 NC_32
R8104-*1
R8100-*1
R8101-*1
R8102-*1
R8103-*1

R8105-*1
R8106-*1
R8107-*1

NC_32 NC_34 NC_34 M6 D4

R8117

R8116
10K
10K
10K
10K

10K
10K
10K
10K

EMMC DATA LINE M6 D4 M6 D4 M6 D4 CLK NC_33

CLK NC_33 CLK NC_35 CLK NC_35 M5 D12

10K

10K
10K PULL/UP M5 D12 M5 D12 M5 D12 CMD NC_34
FOR M13 CMD NC_34 CMD NC_36 CMD NC_36 D13
R8100
R8101
R8102
R8103

R8104
R8105
R8106
R8107

D13 D13 D13 NC_35

NC_35 NC_37 NC_37 D14
IC8100 D14 D14 D14 NC_36
NC_36 NC_38 NC_38 A6 E1
EMMC_SERIAL_22 H26M31002GPR A6 E1 A6 E1 A6 E1 RFU_1 NC_37
EMMC_DATA[0-7] RFU_1 NC_37 NC_3 NC_39 NC_3 NC_39 A7 E2
AR8100 A7 E2 A7 E2 A7 E2 RFU_2 NC_38
22 RFU_2 NC_38 NC_4 NC_40 NC_4 NC_40 C5 E3
1/16W C5 E3 C5 E3 C5 E3 NC_21 NC_39
NC_21 NC_39 NC_23 NC_41 NC_23 NC_41 E5 E12
EMMC_DATA[0] A3 C8 E5 E12 E5 E12 E5 E12 RFU_3 NC_40
DAT0 NC_25 RFU_3 NC_40 NC_42 NC_46 NC_42 NC_46 E8 E13
EMMC_DATA[1] A4 C9 E8 E13 E8 E13 E8 E13 RFU_4 NC_41
DAT1 NC_26 RFU_4 NC_41 NC_43 NC_47 NC_43 NC_47 E9 E14
EMMC_DATA[2] A5 C10 E9 E14 E9 E14 E9 E14 RFU_5 NC_42
DAT2 NC_27 RFU_5 NC_42 NC_44 NC_48 NC_44 NC_48 E10 F1
EMMC_DATA[3] B2 C11 E10 F1 E10 F1 E10 F1 RFU_6 NC_43
EMMC_DATA[4] DAT3 NC_28 RFU_6 NC_43 NC_45 NC_49 NC_45 NC_49 F10 F2
B3 C12 F10 F2 F10 F2 F10 F2 RFU_7 NC_44
EMMC_DATA[5] DAT4 NC_29 RFU_7 NC_44 NC_52 NC_50 NC_52 NC_50 G3 F3
B4 C13 G3 F3 G3 F3 G3 F3 RFU_8 NC_45
EMMC_DATA[6] DAT5 NC_30 RFU_8 NC_45 NC_58 NC_51 NC_58 NC_51 G10 F12
EMMC_SERIAL_22 B5 C14 G10 F12 G10 F12 G10 F12 RFU_9 NC_46
EMMC_DATA[7] AR8101 DAT6 NC_31 RFU_9 NC_46 NC_59 NC_53 NC_59 NC_53 H5 F13
22 B6 D1 H5 F13 H5 F13 H5 F13 RFU_10 NC_47
1/16W DAT7 NC_32 DAT5 RFU_10 NC_47 NC_66 NC_54 NC_66 NC_54 J5 F14
D2 J5 F14 J5 F14 J5 F14 RFU_11 NC_48
NC_33 RFU_11 NC_48 NC_73 NC_55 NC_73 NC_55 K6 G1
D3 K6 G1 K6 G1 K6 G1 RFU_12 NC_49
NC_34 RFU_12 NC_49 NC_80 NC_56 NC_80 NC_56 K7 G2
M6 D4 K7 G2 K7 G2 K7 G2 RFU_13 NC_50
CLK NC_35 RFU_13 NC_50 NC_81 NC_57 NC_81 NC_57 K10 G12
M5 D12 K10 G12 K10 G12 K10 G12 RFU_14 NC_51
CMD NC_36 RFU_14 NC_51 NC_82 NC_60 NC_82 NC_60 P7 G13
D13 P7 G13 P7 G13 P7 G13 RFU_15 NC_52
NC_37 RFU_15 NC_52 NC_116 NC_61 NC_116 NC_61 P10 G14
D14 P10 G14 P10 G14 P10 G14 RFU_16 NC_53
NC_38 RFU_16 NC_53 NC_119 NC_62 NC_119 NC_62 H1

HYNIX_EMMC_2GB
A6 E1 H1 H1 H1 NC_54

TOSHIBA_EMMC_4GB
NC_3 NC_39 NC_54 NC_63 NC_63 H2
A7 E2 H2 H2 H2 NC_55
NC_4 NC_40 NC_55 NC_64 NC_64 K5 H3

TOSHIBA_EMMC_16GB
C5 E3 K5 H3 K5 H3 K5 H3 RSTN NC_56
NC_23 NC_41 RST_N NC_56 RESET NC_65 RSTN NC_65 H12

SAMSUNG_EMMC_2GB
E5 E12 H12 H12 H12 NC_57
NC_42 NC_46 NC_57 NC_67 NC_67 H13
EMMC_SERIAL_22 E8 E13 H13 H13 H13 NC_58
NC_43 NC_47 NC_58 NC_68 NC_68 C6 H14
AR8102 22 E9 E14 C6 H14 C6 H14 C6 H14 VCCQ_1 NC_59
EMMC_CLK NC_44 NC_48 VCCQ_1 NC_59 VCCQ_1 NC_69 VDD_1 NC_69 M4 J1
E10 F1 M4 J1 M4 J1 M4 J1 VCCQ_2 NC_60
EMMC_CMD NC_45 NC_49 DAT6 VCCQ_2 NC_60 VCCQ_2 NC_70 VDD_2 NC_70 N4 J2
F10 F2 N4 J2 N4 J2 N4 J2 VCCQ_3 NC_61
EMMC_RST NC_52 NC_50 VCCQ_3 NC_61 VCCQ_3 NC_71 VDD_3 NC_71 P3 J3
G3 F3 P3 J3 P3 J3 P3 J3 VCCQ_4 NC_62
NC_58 NC_51 VCCQ_4 NC_62 VCCQ_4 NC_72 VDD_4 NC_72 P5 J12
G10 F12 P5 J12 P5 J12 P5 J12 VCCQ_5 NC_63
NC_59 NC_53 VCCQ_5 NC_63 VCCQ_5 NC_74 VDD_5 NC_74 J13
H5 F13 J13 J13 J13 NC_64
NC_66 NC_54 NC_64 NC_75 NC_75 J14
J5 F14 J14 J14 J14 NC_65
C8107 NC_73 NC_55 NC_65 NC_76 NC_76 E6 K1
eMMC serial 100 ohm option OPT 10pF K6 G1 E6 K1 E6 K1 E6 K1 VCC_1 NC_66
NC_80 NC_56 VCC_1 NC_66 VCC_1 NC_77 VDDF_1 NC_77 F5 K2
50V K7 G2 F5 K2 F5 K2 F5 K2 VCC_2 NC_67
NC_81 NC_57 VCC_2 NC_67 VCC_2 NC_78 VDDF_2 NC_78 J10 K3
K10 G12 J10 K3 J10 K3 J10 K3 VCC_3 NC_68
AR8100-*1 AR8101-*1 AR8102-*1 NC_82 NC_60 VCC_3 NC_68 VCC_3 NC_79 VDDF_3 NC_79 K9 K12
100 100 100 P7 G13 K9 K12 K9 K12 K9 K12 VCC_4 NC_69
1/16W 1/16W 1/16W NC_116 NC_61 VCC_4 NC_69 VCC_4 NC_83 VDDF_4 NC_83 K13
EMMC_SERIAL_100

EMMC_SERIAL_100

EMMC_SERIAL_100

P10 G14 K13 K13 K13 NC_70

NC_119 NC_62 NC_70 NC_84 NC_84 K14
H1 K14 K14 K14 NC_71
NC_63 NC_71 NC_85 NC_85 C2 L1
H2 C2 L1 C2 L1 C2 L1 VDDI NC_72
NC_64 VDDI NC_72 VDDI NC_86 VDDI NC_86 L2
K5 H3 L2 L2 L2 NC_73
RESET NC_65 NC_73 NC_87 NC_87 L3
H12 L3 L3 L3 NC_74
C8100 NC_67 NC_74 NC_88 NC_88 E7 L12
OPT 0.1uF H13 E7 L12 E7 L12 C4 L12 VSS_1 NC_75
NC_68 VSS_1 NC_75 VSS_1 NC_89 VSS_1 NC_89 G5 L13
16V C6 H14 G5 L13 G5 L13 E7 L13 VSS_2 NC_76
VCCQ_1 NC_69 VSS_2 NC_76 VSS_2 NC_90 VSS_2 NC_90 H10 L14
3.3V_EMMC 3.3V_EMMC M4 J1 H10 L14 H10 L14 G5 L14 VSS_3 NC_77
N4
VCCQ_2 HYNIX_EMMC_4GB NC_70
J2 K8
VSS_3 NC_77
M1 K8
VSS_3 NC_91
M1 H10
VSS_3 NC_91
M1
K8
VSS_4 NC_78
M1
VCCQ_3 NC_71 VSS_4 NC_78 VSS_4 NC_92 VSS_4 NC_92 C4 M2
P3 J3 C4 M2 C4 M2 K8 M2 VSSQ_1 NC_79
VCCQ_4 NC_72 VSSQ_1 NC_79 VSSQ_1 NC_93 VSS_5 NC_93 N2 M3
P5 J12 N2 M3 N2 M3 N2 M3 VSSQ_2 NC_80
VCCQ_5 NC_74 VSSQ_2 NC_80 VSSQ_2 NC_94 VSS_6 NC_94 N5 M7
DAT6

EMMC_CLK_BALL

EMMC_CMD_BALL

EMMC_RESET_BALL
DAT3

DAT4

DAT5

J13 N5 M7 N5 M7 N5 M7 VSSQ_3 NC_81

C8105 C8106 NC_75 VSSQ_3 NC_81 VSSQ_3 NC_95 VSS_7 NC_95 P4 M8
0.1uF 2.2uF J14 EMMC_RESET_BALL P4 M8 P4 M8 P4 M8 VSSQ_4 NC_82
NC_76 VSSQ_4 NC_82 VSSQ_4 NC_96 VSS_8 NC_96 P6 M9
16V 10V E6 K1 P6 M9 P6 M9 P6 M9 VSSQ_5 NC_83
VCC_1 NC_77 VSSQ_5 NC_83 VSSQ_5 NC_97 VSS_9 NC_97 M10
F5 K2 M10 M10 M10 NC_84
VCC_2 NC_78 NC_84 NC_98 NC_98 M11
J10 K3 M11 M11 M11 NC_85
VCC_3 NC_79 NC_85 NC_99 NC_99 M12
K9 K12 M12 M12 M12 NC_86
VCC_4 NC_83 NC_86 NC_100 NC_100 A1 M13
K13 A1 M13 A1 M13 A1 M13 NC_1 NC_87
NC_84 NC_1 NC_87 NC_1 NC_101 NC_1 NC_101 A2 M14
EMMC_VDDI K14 A2 M14 A2 M14 A2 M14 NC_2 NC_88
NC_85 NC_2 NC_88 NC_2 NC_102 NC_2 NC_102 A8 N1
C2 L1 A8 N1 A8 N1 A8 N1 NC_3 NC_89
VDDI NC_86 NC_3 NC_89 NC_5 NC_103 NC_5 NC_103 A9 N3
L2 A9 N3 A9 N3 A9 N3 NC_4 NC_90
C8104 105C NC_87 NC_4 NC_90 NC_6 NC_104 NC_6 NC_104 A10 N6
1uF L3 A10 N6 A10 N6 A10 N6 NC_5 NC_91
NC_88 NC_5 NC_91 NC_7 NC_105 NC_7 NC_105 A11 N7
6.3V E7 L12 A11 N7 A11 N7 A11 N7 NC_6 NC_92
VSS_1 NC_89 NC_6 NC_92 NC_8 NC_106 NC_8 NC_106 A12 N8
G5 L13 A12 N8 A12 N8 A12 N8 NC_7 NC_93
VSS_2 NC_90 NC_7 NC_93 NC_9 NC_107 NC_9 NC_107 A13 N9
H10 L14 A13 N9 A13 N9 A13 N9 NC_8 NC_94
VSS_3 NC_91 NC_8 NC_94 NC_10 NC_108 NC_10 NC_108 A14 N10
K8 M1 A14 N10 A14 N10 A14 N10 NC_9 NC_95
VSS_4 NC_92 NC_9 NC_95 NC_11 NC_109 NC_11 NC_109 B1 N11
C8102 C8103 C4 M2 B1 N11 B1 N11 B1 N11 NC_10 NC_96
0.1uF 2.2uF VSSQ_1 NC_93 NC_10 NC_96 NC_12 NC_110 NC_12 NC_110 B7 N12
N2 M3 B7 N12 B7 N12 B7 N12 NC_11 NC_97
16V 10V VSSQ_2 NC_94 NC_11 NC_97 NC_13 NC_111 NC_13 NC_111 B8 N13
N5 M7 B8 N13 B8 N13 B8 N13 NC_12 NC_98
VSSQ_3 NC_95 NC_12 NC_98 NC_14 NC_112 NC_14 NC_112 B9 N14
P4 M8 B9 N14 B9 N14 B9 N14 NC_13 NC_99
VSSQ_4 NC_96 NC_13 NC_99 NC_15 NC_113 NC_15 NC_113 B10 P1
P6 M9 B10 P1 B10 P1 B10 P1 NC_14 NC_100
VSSQ_5 NC_97 NC_14 NC_100 NC_16 NC_114 NC_16 NC_114 B11 P2
M10 B11 P2 B11 P2 B11 P2 NC_15 NC_101
NC_98 NC_15 NC_101 NC_17 NC_115 NC_17 NC_115 B12 P8
M11 B12 P8 B12 P8 B12 P8 NC_16 NC_102
NC_99 NC_16 NC_102 NC_18 NC_117 NC_18 NC_117 B13 P9
M12 B13 P9 B13 P9 B13 P9 NC_17 NC_103
NC_100 NC_17 NC_103 NC_19 NC_118 NC_19 NC_118 B14 P11
A1 M13 B14 P11 B14 P11 B14 P11 NC_18 NC_104
DAT3 NC_1 NC_101 NC_18 NC_104 NC_20 NC_120 NC_20 NC_120 C1 P12
A2 M14 C1 P12 C1 P12 C1 P12 NC_19 NC_105
DAT4 NC_2 NC_102 NC_19 NC_105 NC_21 NC_121 NC_21 NC_121 C3 P13
A8 N1 C3 P13 C3 P13 C3 P13 NC_20 NC_106
NC_5 NC_103 NC_20 NC_106 NC_22 NC_122 NC_22 NC_122 C7 P14
A9 N3 EMMC_CMD_BALL C7 P14 C7 P14 C7 P14 NC_22 NC_107
NC_6 NC_104 NC_22 NC_107 NC_24 NC_123 NC_24 NC_123
A10 N6
NC_7 NC_105
A11 N7
NC_8 NC_106
A12 N8
NC_9 NC_107
A13 N9
NC_10 NC_108
A14 N10
NC_11 NC_109
B1 N11
NC_12 NC_110
B7 N12
NC_13 NC_111
B8 N13
NC_14 NC_112
B9 N14
NC_15 NC_113
B10 P1
NC_16 NC_114
B11 P2 EMMC_CLK_BALL
NC_17 NC_115

Don’t Connect Power At VDDI EMMC_VDDI

B12
B13
B14
NC_18
NC_19
NC_117
NC_118
P8
P9
P11
IC8100-*5
KLM4G1FE3B-B001
IC8100-*6
THGBM5G6A2JBAIR
IC8100-*7
KLMAG2GE4A-A001
A3
IC8100-*8
H26M42002GMR

C8 A3
IC8100-*9
MTFC4GMVEA-1M WT

C8
EMMC 4.5Ver
NC_20 NC_120 A3 C8 A3 C8 A3 C8
A4
DAT0
DAT1
NC_25
NC_26
C9 A4
DAT0 NC_23
C9
C1 P12 A4
DAT0 NC_25
C9 A4
DAT0 NC_23
C9 A4
DAT0 NC_22
C9
A5
DAT2
C10 A5
DAT1 NC_24
C10

SAMSUNG_EMMC_16G
NC_27
A5
DAT1 NC_26
C10 A5
DAT1 NC_24
C10 A5
DAT1 NC_23
C10 B2 C11 DAT2 NC_25
NC_21 NC_121 DAT2 NC_27 DAT2 NC_25 DAT2 NC_24
B3
DAT3 NC_28
C12
B2
DAT3 NC_26
C11

HYNIX_EMMC_8GB
B2 C11 B2 C11 B2 C11

(Just Interal LDO Capacitor) C3 P13 DAT4 NC_29 B3 C12

DAT3 NC_28 DAT3 NC_26 DAT3 NC_25
B3 C12 B3 C12 B3 C12 B4 C13 DAT4 NC_27
SAMSUNG_EMMC_4GB

TOSHIBA_EMMC_8GB

DAT4 NC_29 DAT4 NC_27 DAT4 NC_26 DAT5 NC_30

B4 C13 B4 C13 B4 C13 B4 C13
DAT5 NC_22 NC_122 B5
DAT5
DAT6
NC_30
NC_31
C14 B5
DAT5
DAT6
NC_28
NC_29
C14 B5
DAT5
DAT6
NC_27
NC_28
C14
B5
B6
DAT6 NC_31
C14
D1 B5
DAT5 NC_28
C14 IC8100-*10 IC8100-*11 IC8100-*12
C7 P14 B6
DAT7 NC_32
D1
D2
B6
DAT7 NC_30
D1
D2
B6
DAT7 NC_29
D1
D2
DAT7 NC_32
D2 B6
DAT6 NC_29
D1
MTFC4GMCDM-1M WT THGBMAG5A1JBAIR H26M31003GMR

MICRON_EMMC_4GB
NC_33 NC_31 NC_30 NC_33 DAT7 NC_30
NC_24 NC_123 D3 D2

DEV_EMMC4.5_TOSHIBA_4G
D3 D3 D3

DEV_EMMC4.5_MICRON_4G
NC_34 NC_32 NC_31 NC_34 NC_31
M6 D4 M6 D4 M6 D4 M6 D4 D3 A3 C8 A3 C8 A3 C8
CLK NC_35 CLK NC_33 CLK NC_32 CLK NC_35 DAT0 NC_23 DAT0 NC_23 DAT0 NC_23

DEV_EMMC4.5_SKHynix_4G
M5 D12 M5 D12 M5 D12 M5 D12 NC_32 A4 C9 A4 C9 A4 C9
CMD NC_36
D13
CMD NC_34
D13
CMD NC_33
D13 CMD NC_36 M6 D4 A5
DAT1 NC_24
C10 A5
DAT1 NC_24
C10 A5
DAT1 NC_24
C10
NC_37 NC_35 NC_34 D13 CLK NC_33 DAT2 NC_25 DAT2 NC_25 DAT2 NC_25
D14 D14 D14 NC_37 M5 D12 B2 C11 B2 C11 B2 C11
NC_38 NC_36 NC_35 D14 CMD NC_34 DAT3 NC_26 DAT3 NC_26 DAT3 NC_26
A6 E1 A6 E1 A6 E1 NC_38 D13 B3 C12 B3 C12 B3 C12
NC_3 NC_39 RFU_1 NC_37 RFU_1 NC_36 A6 E1 DAT4 NC_27 DAT4 NC_27 DAT4 NC_27
A7 E2 A7 E2 A7 E2 NC_3 NC_39 NC_35 B4 C13 B4 C13 B4 C13
C5
NC_4 NC_40
E3 C5
RFU_2 NC_38
E3 C5
RFU_2 NC_37
E3 A7 E2 D14 B5
DAT5 NC_28
C14 B5
DAT5 NC_28
C14 B5
DAT5 NC_28
C14
NC_23 NC_41 NC_21 NC_39 RFU_3 NC_38 NC_4 NC_40 NC_36 DAT6 NC_29 DAT6 NC_29 DAT6 NC_29
E5 E12 E5 E12 E5 E12 C5 E3 A6 E1 B6 D1 B6 D1 B6 D1
E8
NC_42 NC_46
E13 E8
RFU_3 NC_40
E13 E8
RFU_4 NC_40
E13
NC_23 NC_41 RFU_1 NC_37 DAT7 NC_30
D2
DAT7 NC_30
D2
DAT7 NC_30
D2
E5 E12 A7 E2
NC_43 NC_47 RFU_4 NC_41 RFU_5 NC_41 NC_42 NC_46 NC_31 NC_31 NC_31
E9 E14 E9 E14 E9 E14 E8 E13 RFU_2 NC_38 D3 D3 D3
E10
NC_44 NC_48
F1 E10
RFU_5 NC_42
F1 E10
RFU_6 NC_42
F1 NC_43 NC_47
C5 E3 M6
NC_32
D4 M6
NC_32
D4 M6
NC_32
D4
NC_45 NC_49 RFU_6 NC_43 NC_39 NC_43 E9 E14 NC_21 NC_39 CLK NC_33 CLK NC_33 CLK NC_33
F10 F2 F10 F2 F10 F2 NC_44 NC_48 E5 E12 M5 D12 M5 D12 M5 D12
G3
NC_52 NC_50
F3 G3
RFU_7 NC_44
F3 G3
RFU_7 NC_44
F3
E10 F1 RFU_3 NC_40 CMD NC_34
D13
CMD NC_34
D13
CMD NC_34
D13
NC_58 NC_51 RFU_8 NC_45 RFU_8 NC_45 NC_45 NC_49 E8 E13 NC_35 NC_35 NC_35
G10 F12 G10 F12 G10 F12 F10 F2 RFU_4 NC_41 D14 D14 D14
NC_52 NC_50 E9 E14
DU1 DU9 H5
J5
NC_59
NC_66
NC_53
NC_54
F13
F14
H5
J5
RFU_9
RFU_10
NC_46
NC_47
F13
F14
H5
J5
RFU_9
RFU_10
NC_46
NC_47
F13
F14
G3
G10
NC_58 NC_51
F3
F12 E10
RFU_5 NC_42
F1
A6
A7
RFU_1
NC_36
NC_37
E1
E2
A6
A7
RFU_1
NC_36
NC_37
E1
E2
A6
A7
RFU_1
NC_36
NC_37
E1
E2

DUMMY_1 DUMMY_9 K6
NC_73
NC_80
NC_55
NC_56
G1 K6
RFU_11
RFU_12
NC_48
NC_49
G1 K6
RFU_11
RFU_12
NC_48
NC_49
G1 H5
NC_59 NC_53
F13 F10
RFU_6 NC_43
F2 C5
RFU_2
NC_21
NC_38
NC_39
E3 C5
RFU_2
NC_21
NC_38
NC_39
E3 C5
RFU_2
NC_21
NC_38
NC_39
E3

DU2 DU10 K7
K10
NC_81
NC_82
NC_57
NC_60
G2
G12
K7
K10
RFU_13
RFU_14
NC_50
NC_51
G2
G12
K7
K10
RFU_13
RFU_14
NC_50
NC_51
G2
G12
J5
K6
NC_66
NC_73
NC_54
NC_55
F14
G1
G3
RFU_7
RFU_8
NC_44
NC_45
F3
E5
E8
RFU_3
RFU_4
NC_40
NC_41
E12
E13
E5
E8
RFU_3
RFU_4
NC_40
NC_41
E12
E13
E5
E8
RFU_3
RFU_4
NC_40
NC_41
E12
E13

DUMMY_2 DUMMY_10 P7
P10
NC_116 NC_61
G13
G14
P7
P10
RFU_15 NC_52
G13
G14
P7
P10
RFU_15 NC_52
G13
G14 K7
NC_80 NC_56
G2
G10
H5
RFU_9 NC_46
F12
F13
E9
E10
RFU_5 NC_42
E14
F1
E9
E10
RFU_5 NC_42
E14
F1
E9
E10
RFU_5 NC_42
E14
F1
DU3 DU11 NC_119 NC_62
NC_63
H1
H2
RFU_16 NC_53
NC_54
H1
H2
NC_104 NC_53
NC_54
H1
H2
K10
P7
NC_81
NC_82
NC_57
NC_60
G12
G13
J5
RFU_10 NC_47
F14
F10
G3
RFU_6
RFU_7
NC_43
NC_44
F2
F3
F10
G3
RFU_6
RFU_7
NC_43
NC_44
F2
F3
F10
G3
RFU_6
RFU_7
NC_43
NC_44
F2
F3
DUMMY_3 DUMMY_11 K5
NC_64
H3 K5
NC_55
H3 K5
NC_55
H3 P10
NC_116 NC_61
G14 K6
RFU_11 NC_48
G1 G10
RFU_8 NC_45
F12 G10
RFU_8 NC_45
F12 G10
RFU_8 NC_45
F12

DU4 DU12 RSTN NC_65

NC_67
H12
H13
RSTN NC_56
NC_57
H12
H13
RESET NC_56
NC_57
H12
H13
NC_119 NC_62
NC_63
H1 K7
RFU_12
RFU_13
NC_49
NC_50
G2 H5
J5
RFU_9
RFU_10
NC_46
NC_47
F13
F14
H5
J5
RFU_9
RFU_10
NC_46
NC_47
F13
F14
H5
J5
RFU_9
RFU_10
NC_46
NC_47
F13
F14

DUMMY_4 DUMMY_12 C6
VDD_1
NC_68
NC_69
H14 C6
VCCQ_1
NC_58
NC_59
H14 C6
VDD_1
NC_58
NC_59
H14
K5
NC_64
H2
H3
K10
P7
RFU_14 NC_51
G12
G13
K6
RFU_11
RFU_12
NC_48
NC_49
G1 K6
RFU_11
RFU_12
NC_48
NC_49
G1 K6
RFU_11
RFU_12
NC_48
NC_49
G1

DU5 DU13 M4
N4
VDD_2
VDD_3
NC_70
NC_71
J1
J2
M4
N4
VCCQ_2
VCCQ_3
NC_60
NC_61
J1
J2
M4
N4
VDD_2
VDD_3
NC_60
NC_61
J1
J2
RESET NC_65
NC_67
H12 P10
RFU_15 NC_52
G14
K7
K10
RFU_13
RFU_14
NC_50
NC_51
G2
G12
K7
K10
RFU_13
RFU_14
NC_50
NC_51
G2
G12
K7
K10
RFU_13
RFU_14
NC_50
NC_51
G2
G12

DUMMY_5 DUMMY_13 P3
P5
VDD_4 NC_72
J3
J12
P3
P5
VCCQ_4 NC_62
J3
J12
P3
P5
VDD_4 NC_62
J3
J12 NC_68
H13 RFU_16 NC_53
H1
P7
P10
RFU_15 NC_52
G13
G14
P7
P10
RFU_15 NC_52
G13
G14
P7
P10
RFU_15 NC_52
G13
G14
DU6 DU14 VDD_5 NC_74
NC_75
J13
J14
VCCQ_5 NC_63
NC_64
J13
J14
VDD_5 NC_63
NC_64
J13
J14
C6
M4
VCCQ_1
VCCQ_2
NC_69
NC_70
H14
J1
NC_54
NC_55
H2 RFU_16 NC_53
NC_54
H1
H2
RFU_16 NC_53
NC_54
H1
H2
RFU_16 NC_53
NC_54
H1
H2
DUMMY_6 DUMMY_14 E6
NC_76
K1 E6
NC_65
K1 E6
NC_65
K1
N4
VCCQ_3 NC_71
J2 K5
RSTN NC_56
H3
H12
K5
NC_55
H3 K5
NC_55
H3 K5
NC_55
H3

DU7 DU15 F5
J10
VDDF_1
VDDF_2
NC_77
NC_78
K2
K3
F5
J10
VCC_1
VCC_2
NC_66
NC_67
K2
K3
F5
J10
VDDF_1
VDDF_2
NC_66
NC_67
K2
K3
P3
P5
VCCQ_4 NC_72
J3
J12
NC_57
H13
RST_N NC_56
NC_57
H12
H13
RST_N NC_56
NC_57
H12
H13
RST_N NC_56
NC_57
H12
H13

DUMMY_7 DUMMY_15 K9
VDDF_3
VDDF_4
NC_79
NC_83
K12 K9
VCC_3
VCC_4
NC_68
NC_69
K12 K9
VDDF_3
VDDF_4
NC_68
NC_69
K12
VCCQ_5 NC_74
NC_75
J13 C6
NC_58
H14 C6
VCCQ_1
NC_58
NC_59
H14 C6
VCCQ_1
NC_58
NC_59
H14 C6
VCCQ_1
NC_58
NC_59
H14

DU8 DU16 NC_84

NC_85
K13
K14
NC_70
NC_71
K13
K14
NC_70
NC_71
K13
K14
E6
NC_76
J14
K1
M4
VCCQ_1
VCCQ_2
NC_59
NC_60
J1
M4
N4
VCCQ_2
VCCQ_3
NC_60
NC_61
J1
J2
M4
N4
VCCQ_2
VCCQ_3
NC_60
NC_61
J1
J2
M4
N4
VCCQ_2
VCCQ_3
NC_60
NC_61
J1
J2

DUMMY_8 DUMMY_16 C2
VDDI NC_86
NC_87
L1
L2
C2
VDDI NC_72
NC_73
L1
L2
C2
VDDI NC_72
NC_73
L1
L2
F5
J10
VCC_1
VCC_2
NC_77
NC_78
K2
N4
P3
VCCQ_3 NC_61
J2
J3
P3
P5
VCCQ_4
VCCQ_5
NC_62
NC_63
J3
J12
P3
P5
VCCQ_4
VCCQ_5
NC_62
NC_63
J3
J12
P3
P5
VCCQ_4
VCCQ_5
NC_62
NC_63
J3
J12
L3 L3 L3 K3 VCCQ_4 NC_62 J13 J13 J13
NC_88 NC_74 NC_74 VCC_3 NC_79 P5 J12 NC_64 NC_64 NC_64
E7 L12 E7 L12 E7 L12 K9 K12 J14 J14 J14
VSS_2 NC_89 VSS_1 NC_75 VSS_2 NC_75 VCC_4 NC_83 VCCQ_5 NC_63 NC_65 NC_65 NC_65
G5 L13 G5 L13 G5 L13 K13 J13 E6 K1 E6 K1 E6 K1
H10
VSS_3 NC_90
L14 H10
VSS_2 NC_76
L14 H10
VSS_3 NC_76
L14 NC_84 NC_64 F5
VCC_1 NC_66
K2 F5
VCC_1 NC_66
K2 F5
VCC_1 NC_66
K2
VSS_4 NC_91 VSS_3 NC_77 VSS_4 NC_77 K14 J14 VCC_2 NC_67 VCC_2 NC_67 VCC_2 NC_67
K8 M1 K8 M1 K8 M1 NC_85 NC_65 J10 K3 J10 K3 J10 K3
VSS_5 NC_92 VSS_4 NC_78 VSS_9 NC_78 C2 L1 E6 K1 VCC_3 NC_68 VCC_3 NC_68 VCC_3 NC_68
C4 M2 C4 M2 C4 M2 VDDI NC_86 K9 K12 K9 K12 K9 K12
VSS_1 NC_93 VSSQ_1 NC_79 VSS_1 NC_79 L2 VCC_1 NC_66 VCC_4 NC_69 VCC_4 NC_69 VCC_4 NC_69
N2 M3 N2 M3 N2 M3 NC_87
F5 K2 K13 K13 K13
N5
VSS_6 NC_94
M7 N5
VSSQ_2 NC_80
M7 N5
VSS_5 NC_80
M7 L3 VCC_2 NC_67 NC_70
K14
NC_70
K14
NC_70
K14
VSS_7 NC_95 VSSQ_3 NC_81 VSS_6 NC_81 NC_88 J10 K3 NC_71 NC_71 NC_71
P4 M8 P4 M8 P4 M8 E7 L12 VCC_3 NC_68 C2 L1 C2 L1 C2 L1
P6
VSS_8 NC_96
M9 P6
VSSQ_4 NC_82
M9 P6
VSS_7 NC_82
M9
VSS_1 NC_89 K9 K12 VDDI NC_72
L2
VDDI NC_72
L2
VDDI NC_72
L2
G5 L13 VCC_4 NC_69
VSS_9 NC_97 VSSQ_5 NC_83 VSS_8 NC_83 VSS_2 NC_90 NC_73 NC_73 NC_73
M10 M10 M10 H10 L14 K13 L3 L3 L3
NC_98
M11
NC_84
M11
NC_84
M11 VSS_3 NC_91 NC_70 E7
NC_74
L12 E7
NC_74
L12 E7
NC_74
L12
NC_99 NC_85 NC_85 K8 M1 K14 VSS_1 NC_75 VSS_1 NC_75 VSS_1 NC_75
M12 M12 M12 VSS_4 NC_92 NC_71 G5 L13 G5 L13 G5 L13
A1
NC_100
M13 A1
NC_86
M13 A1
NC_86
M13
C4 M2 C2 L1 H10
VSS_2 NC_76
L14 H10
VSS_2 NC_76
L14 H10
VSS_2 NC_76
L14
NC_1 NC_101 NC_1 NC_87 NC_1 NC_87 VSSQ_1 NC_93 VDDI NC_72 VSS_3 NC_77 VSS_3 NC_77 VSS_3 NC_77
A2 M14 A2 M14 A2 M14 N2 M3 L2 K8 M1 K8 M1 K8 M1
NC_2 NC_102 NC_2 NC_88 NC_2 NC_88 VSSQ_2 NC_94 NC_73 VSS_4 NC_78 VSS_4 NC_78 VSS_4 NC_78
A8 N1 A8 N1 A8 N1 N5 M7 L3 C4 M2 C4 M2 C4 M2
NC_5 NC_103 NC_3 NC_89 NC_3 NC_89 VSSQ_3 NC_95 VSSQ_1 NC_79 VSSQ_1 NC_79 VSSQ_1 NC_79
A9 N3 A9 N3 A9 N3 P4 M8 NC_74 N2 M3 N2 M3 N2 M3
A10
NC_6 NC_104
N6 A10
NC_4 NC_90
N6 A10
NC_4 NC_90
N6 VSSQ_4 NC_96 E7 L12 N5
VSSQ_2 NC_80
M7 N5
VSSQ_2 NC_80
M7 N5
VSSQ_2 NC_80
M7
NC_7 NC_105 NC_5 NC_91 NC_5 NC_91 P6 M9 VSS_1 NC_75 VSSQ_3 NC_81 VSSQ_3 NC_81 VSSQ_3 NC_81
A11 N7 A11 N7 A11 N7 VSSQ_5 NC_97 G5 L13 P4 M8 P4 M8 P4 M8
NC_8 NC_106 NC_6 NC_92 NC_6 NC_92 M10 VSS_2 NC_76 VSSQ_4 NC_82 VSSQ_4 NC_82 VSSQ_4 NC_82
A12 N8 A12 N8 A12 N8 NC_98 H10 L14 P6 M9 P6 M9 P6 M9
NC_9 NC_107 NC_7 NC_93 NC_7 NC_93 M11 VSSQ_5 NC_83 VSSQ_5 NC_83 VSSQ_5 NC_83
A13 N9 A13 N9 A13 N9 NC_99 VSS_3 NC_77 M10 M10 M10
A14
NC_10 NC_108
N10 A14
NC_8 NC_94
N10 A14
NC_8 NC_94
N10 M12 K8 M1 NC_84
M11
NC_84
M11
NC_84
M11
NC_11 NC_109 NC_9 NC_95 NC_9 NC_95 NC_100 VSS_4 NC_78 NC_85 NC_85 NC_85
B1 N11 B1 N11 B1 N11 A1 M13 C4 M2 M12 M12 M12
B7
NC_12 NC_110
N12 B7
NC_10 NC_96
N12 B7
NC_10 NC_96
N12
NC_1 NC_101 VSSQ_1 NC_79 A1
NC_86
M13 A1
NC_86
M13 A1
NC_86
M13
A2 M14 N2 M3
NC_13 NC_111 NC_11 NC_97 NC_11 NC_97 NC_2 NC_102 NC_1 NC_87 NC_1 NC_87 NC_1 NC_87
B8 N13 B8 N13 B8 N13 A8 N1 VSSQ_2 NC_80 A2 M14 A2 M14 A2 M14
B9
NC_14 NC_112
N14 B9
NC_12 NC_98
N14 B9
NC_12 NC_98
N14 NC_5 NC_103
N5 M7 A8
NC_2 NC_88
N1 A8
NC_2 NC_88
N1 A8
NC_2 NC_88
N1
NC_15 NC_113 NC_13 NC_99 NC_13 NC_99 A9 N3 VSSQ_3 NC_81 NC_3 NC_89 NC_3 NC_89 NC_3 NC_89
B10 P1 B10 P1 B10 P1 NC_6 NC_104 P4 M8 A9 N3 A9 N3 A9 N3
B11
NC_16 NC_114
P2 B11
NC_14 NC_100
P2 B11
NC_14 NC_100
P2
A10 N6 VSSQ_4 NC_82 A10
NC_4 NC_90
N6 A10
NC_4 NC_90
N6 A10
NC_4 NC_90
N6
NC_17 NC_115 NC_15 NC_101 NC_15 NC_101 NC_7 NC_105 P6 M9 NC_5 NC_91 NC_5 NC_91 NC_5 NC_91
B12 P8 B12 P8 B12 P8 A11 N7 VSSQ_5 NC_83 A11 N7 A11 N7 A11 N7
NC_18 NC_117 NC_16 NC_102 NC_16 NC_102 NC_8 NC_106 M10 NC_6 NC_92 NC_6 NC_92 NC_6 NC_92
B13 P9 B13 P9 B13 P9 A12 N8 A12 N8 A12 N8 A12 N8
NC_19 NC_118 NC_17 NC_103 NC_17 NC_103 NC_9 NC_107 NC_84 NC_7 NC_93 NC_7 NC_93 NC_7 NC_93
B14 P11 B14 P11 B14 P11 A13 N9 M11 A13 N9 A13 N9 A13 N9
C1
NC_20 NC_120
P12 C1
NC_18 NC_104
P12 C1
NC_18 RFU_16
P12 NC_10 NC_108 NC_85 A14
NC_8 NC_94
N10 A14
NC_8 NC_94
N10 A14
NC_8 NC_94
N10
NC_21 NC_121 NC_19 NC_105 NC_19 NC_105 A14 N10 M12 NC_9 NC_95 NC_9 NC_95 NC_9 NC_95
C3 P13 C3 P13 C3 P13 NC_11 NC_109 NC_86 B1 N11 B1 N11 B1 N11
NC_22 NC_122 NC_20 NC_106 NC_20 NC_106 B1 N11 A1 M13 NC_10 NC_96 NC_10 NC_96 NC_10 NC_96
C7 P14 C7 P14 C7 P14 NC_12 NC_110 B7 N12 B7 N12 B7 N12
NC_24 NC_123 NC_22 NC_107 NC_21 NC_107 B7 N12 NC_1 NC_87 NC_11 NC_97 NC_11 NC_97 NC_11 NC_97
NC_13 NC_111
A2 M14 B8 N13 B8 N13 B8 N13
B8 N13 NC_2 NC_88 B9
NC_12 NC_98
N14 B9
NC_12 NC_98
N14 B9
NC_12 NC_98
N14
NC_14 NC_112 A8 N1 NC_13 NC_99 NC_13 NC_99 NC_13 NC_99
B9 N14 NC_3 NC_89 B10 P1 B10 P1 B10 P1
NC_15 NC_113 A9 N3 B11
NC_14 NC_100
P2 B11
NC_14 NC_100
P2 B11
NC_14 NC_100
P2
B10 P1 NC_4 NC_90
NC_16 NC_114 NC_15 NC_101 NC_15 NC_101 NC_15 NC_101
DU1 DU9 B11 P2 A10 N6 B12 P8 B12 P8 B12 P8
DU2
DUMMY_1 DUMMY_9
DU10 NC_17 NC_115 NC_5 NC_91 B13
NC_16 NC_102
P9 B13
NC_16 NC_102
P9 B13
NC_16 NC_102
P9
DUMMY_2 DUMMY_10 B12 P8 A11 N7 NC_17 NC_103 NC_17 NC_103 NC_17 NC_103
DU3 DU11 NC_18 NC_117 NC_6 NC_92 B14 P11 B14 P11 B14 P11
DU4
DUMMY_3 DUMMY_11
DU12
B13 P9 A12 N8 C1
NC_18 NC_104
P12 C1
NC_18 NC_104
P12 C1
NC_18 NC_104
P12
DUMMY_4 DUMMY_12 NC_19 NC_118 NC_7 NC_93 NC_19 NC_105 NC_19 NC_105 NC_19 NC_105
DU5 DU13 B14 P11 A13 N9 C3 P13 C3 P13 C3 P13
DUMMY_5 DUMMY_13 NC_20 NC_120 NC_8 NC_94 NC_20 NC_106 NC_20 NC_106 NC_20 NC_106
DU6 DU14 C1 P12 A14 N10 C7 P14 C7 P14 C7 P14
DUMMY_6 DUMMY_14 NC_21 NC_121 NC_22 NC_107 NC_22 NC_107 NC_22 NC_107
DU7 DU15 C3 P13 NC_9 NC_95
DU8
DUMMY_7 DUMMY_15
DU16 NC_22 NC_122 B1 N11
DUMMY_8 DUMMY_16 C7 P14 NC_10 NC_96
NC_24 NC_123 B7 N12
NC_11 NC_97
B8 N13
NC_12 NC_98
B9 N14
NC_13 NC_99
B10 P1
NC_14 NC_100
B11 P2
NC_15 NC_101
B12 P8
NC_16 NC_102
B13 P9
NC_17 NC_103
B14 P11
NC_18 NC_104
C1 P12
NC_19 NC_105
C3 P13

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

NC_20 NC_106
C7 P14
NC_22 NC_107

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.

FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS eMMC 11.09.29
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
81
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
 +24V_AMP

OPT
C5450
10uF
35V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
 M13 EAX64872104 BASE M13 PCB P/NO C114-*2
3.3pF
C115-*2 C114-*1 C115-*1
3.3pF 2.7pF
14y Smart TV EAX64797001* : LD33B
50V
EAX6558850X_3.3pF
50V
EAX6558850X_3.3pF
50V
2.7pF
50V
EAX6561020X_2.7pF EAX6561020X_2.7pF

EAX64872101* : LA33B X-TAL X100

27MHz
X-TAL_1 GND_2
MT5398_XTAL_IN 1 4
Close to eMMC Flash C114
GND_1 X-TAL_2
EAX6561090X_1pF 1.0pF 2 3 MT5398_XTAL_OUT
IC100-*1
(IC8100) 50V C115
M24256-BRMN6TP 1.0pF EAX6561090X_1pF
+3.3V_NORMAL
NVRAM E0
1 8
VCC NC4.5 PCB P/NO EMMC_CLK
50V

E1

E2
2

3
7

6
WC

SCL
NON CI : EAX65610201 R168
10K
R101
4.7K
R102
4.7K
IC100
AT24C256C-SSHL-T
+3.3V_NORMAL VSS
4 5
SDA
CI :
OPT NVRAM_ST
R100 A0 VCC
1 8 Write Protection M13 vs Lean Smart
4.7K del. FE_LNA_Ctrl1/2
OPT A1 WP - Low : Normal Operation
2 7
- High : Write Protection cause of Tuner change 13y to 14y
A2 SCL
R135 33 VDD3V3 IC105
3 6 I2C_SCL5 LGE2122[A2_M13]
+3.3V_NORMAL
GND SDA
4 5 R134 33
I2C_SDA5

R195
R194
AK10 AH15

10K
10K
L/DIM0_MOSI JTCK U0TX SOC_TX
NVRAM_ATMEL AK11 AH14
L/DIM0_SCLK JTDI U0RX SOC_RX R183 R184
AL9 4.7K 4.7K
JTDO
AJ11 AH13
JTMS U1TX M_REMOTE_TX
AJ12 AG13
L/DIM0_VS JTRST U1RX M_REMOTE_RX

HDCP EEPROM OSDA0

OSCL0
AH11
AH10
OSDA0
OSCL0
POWE
POOE
D24
B25
EMMC_CMD

D25 FE_LNA_Ctrl1/2 EMMC_DATA[2-7]

POCE1
AF11 A25
OSDA1 OSDA1 POCE0 EMMC_DATA[7]
AG11 C22
OSCL1 OSCL1 PDD7 EMMC_DATA[6]
B22
PDD6 EMMC_DATA[5]
AVDD_33SB AN29 A22
MT5398_XTAL_IN XTALI PDD5 EMMC_DATA[4]
AM29 C23 AVDD_33SB

Deleted STRAPPING LED_PWM0 LED_PWM1 OPCTRL3 OPCTRL7

MT5398_XTAL_OUT

AN30
XTALO
Wake On Lan

AVDD33_XTAL_STB
PDD4
PDD3
PDD2
A23
B23
EMMC_DATA[3]
EMMC_DATA[2]
R188
CAM_SLIDE_DET

C111 AL29 D23 4.7K

ICE mode + 27M + serial boot 1 0 0 0 0.1uF AVSS33_XTAL_STB PDD1
C24
PDD0 WOL/ETH_POWER_ON
ICE mode + 27M + ROM to Nand boot 1 0 0 1 C25 CAM_SLIDE_DET
PARB R187
AVDD_33SB A26 4.7K
+3.3V_NORMAL ICE mode + 27M + ROM to 60bit ECC Nand boot 1 0 1 0 PACLE EMMC_DATA[1]
AN17 B26 OPT +3.3V_NORMAL
AVDD33_VGA_STB PAALE EMMC_DATA[0]
ICE mode + 27M + ROM to eMMC boot from 1 0 1 1 C110 AL17 C21
0.1uF AVSS33_AVSS33_VGA_STB EMMC_CLK EMMC_CLK
EMMC pins (share pins w/s NAND)
R158 R189
VDD3V3 AL15
ICE mode + 27M + ROM to eMMC 1 1 0 0 OPWRSB 10K
R155 R157 R162 R163 AL26
1K OPT 1K 1K Boot from SDIO pins 22 OPT
1K AVDD33_PLL R186
C109 AC21 AK20
0.1uF AVSS33_PLLGP ORESET SOC_RESET
H21
LED_PWM0 AVSS33_CPUPLL 22 C117
AF17 0.1uF
LED_PWM1 OIRI
16V
OPCTRL3
AM17 C20
OPCTRL7 AVDD10_LDO FSRC_WR
C107
R154 R156 R160 4.7uF AL14
1K 1K OPT 1K OPT
R161 10V STB_SCL STB_SCL Q100 +3.3V_NORMAL
1K AN16 AK15 D100
OPT

AVDD10_ELDO STB_SDA STB_SDA R196 PMV48XP

1N4148W
C112 240

S
4.7uF AE14 R193 4.7K

R180 4.7K
10V POR_BND 100V

R190
G

10K
IC105
I2C_1 : AMP, L/DIMMING,HDCP KEY CI_ADDR[0-14]
LGE2122[A2_M13]
I2C_2 : T-CON, CI_ADDR[0-14]
I2C_3 : MICOM OTP_WRITE
CI_ADDR[0] B30 P30 FE_DEMOD1_TS_DATA[0-7]
I2C_4 : S/Demod,T2/Demod, LNB, MHL(Sil1292) GPIO0 DEMOD_RST PCM_RST
I2C R147-*1 R142-*1
I2C_5
I2C_6
:
:
NVRAM
TUNER_MOPLL(T/C,ATV)
CI_ADDR[1]
CI_ADDR[2]
A31
B31
GPIO1
GPIO2
DEMOD_TSCLK
DEMOD_TSDATA0
N32
R27
FE_DEMOD1_TS_CLK FE_DEMOD1_TS_DATA[0]
FE_DEMOD1_TS_DATA[1]
CI_ADDR[3] A32 T26
TU_Q_SG TU_Q_SG GPIO3 DEMOD_TSDATA1
1.5K 1.5K +3.3V_NORMAL CI_ADDR[4] C30 T27 FE_DEMOD1_TS_DATA[2]
R152-*1 R153-*1 GPIO4 DEMOD_TSDATA2 FE_DEMOD1_TS_DATA[3]
CI_ADDR[5] A33 P26
TU_Q_KR TU_Q_KR GPIO5 DEMOD_TSDATA3 EXTERNAL DEMOD
NON_TU_Q_SG

NON_TU_Q_SG

1.5K CI_ADDR[6] B32 R28 FE_DEMOD1_TS_DATA[4]

1.5K
NON_TU_Q_KR

NON_TU_Q_KR

GPIO6 DEMOD_TSDATA4 FE_DEMOD1_TS_DATA[5] -> SOC

CI_ADDR[7] C31 U27
R121 R124 R132 R133 R138 R141 R142 R147 R150 R151 R152-*2 R153-*2 GPIO7 DEMOD_TSDATA5 FE_DEMOD1_TS_DATA[6]
R152 R153 CI_ADDR[8] E30 U26
1.2K 1.2K 2.7K 2.7K 2.7K 2.7K 2.7K 2.7K 2.7K 2.7K TU_N_TW/BR TU_N_TW/BR SOC -> CI SLOT GPIO8 DEMOD_TSDATA6 FE_DEMOD1_TS_DATA[7]
2.7K 2.7K CI_ADDR[9] F29 R26
1.2K 1.2K GPIO9 DEMOD_TSDATA7
MT5398_MCLKI CI_ADDR[10] F27 R29
STB_SCL R120 33 I2C_SCL1 GPIO10 DEMOD_TSSYNC FE_DEMOD1_TS_SYNC
MT5398_MIVAL_ERR CI_ADDR[11] F28 P27
STB_SDA R115 33 I2C_SDA1 GPIO11 DEMOD_TSVAL FE_DEMOD1_TS_VAL
MT5398_MISTRT CI_ADDR[12] C32
OPCTRL_11_SCL R116 33 M13 vs Lean Smart CI_ADDR[13] F30
GPIO12
L25
R117 33 I2C_SCL2/SDA2 del. I2C_SCL2/SDA2 GPIO13 CI_INT /PCM_REG
OPCTRL_10_SDA CI_ADDR[14] F32 N33
SOC -> CI SLOT
OSCL1 R118 33 I2C_SCL_MICOM
cause of EPI block deletion D30
GPIO14 CI_TSCLK
K26
/PCM_CE1
MT5398_TS_OUT[0-7] GPIO15 CI_TSDATA0 MT5398_TS_SYNC CI SLOT -> SOC
OSDA1 R119 33 I2C_SDA_MICOM D32 N30 /PCM_WE
R110 33 GPIO16 CI_TSSYNC
OSCL2 I2C_SCL4 F31 N31 /PCM_OE
R111 33 GPIO17 CI_TSVAL
OSDA2 I2C_SDA4 MT5398_TS_OUT[0] F33
R112 33 GPIO18
OSCL0 I2C_SCL5 MT5398_TS_OUT[1] E31 M31
R113 33 GPIO19 PVR_TSCLK MT5398_TS_VAL CI SLOT -> SOC
OSDA0 I2C_SDA5 MT5398_TS_OUT[2] E32 M27
R114 33 GPIO20 PVR_TSVAL CI_A_VS1
OPCTRL_1_SCL I2C_SCL6 MT5398_TS_OUT[3] D31 L27
R109 33 GPIO21 PVR_TSSYNC MT5398_TS_CLK CI SLOT -> SOC
OPCTRL_0_SDA I2C_SDA6 MT5398_TS_OUT[4] D33 M29
GPIO22 PVR_TSDATA0 /PCM_IRQA
MT5398_TS_OUT[5] E29 M30
CI_DATA[0-7] GPIO23 PVR_TSDATA1 /PCM_WAIT
MT5398_TS_OUT[6] C33
GPIO24 +3.3V_NORMAL
MT5398_TS_OUT[7] B33 L30
GPIO25 SPI_CLK1 /CI_CD2
CI_DATA[0] A30 L33
GPIO26 SPI_CLK /CI_CD1
CI_DATA[1] E28 L32
GPIO27 SPI_DATA /PCM_IORD R174 R177
CI_DATA[2] C29 K27 4.7K 4.7K
GPIO28 SPI_CLE /PCM_IOWR
CI_DATA[3] J28 OPT OPT
GPIO29 R179 PWM_DIM2
+3.3V_NORMAL Model Option CI_DATA[4]
CI_DATA[5]
H29
J26
GPIO30 OPWM2
AL8
AM8 22
PWM_DIM2
GPIO31 OPWM1 PWM_DIM1
CI_DATA[6] G30 AM9 R178 22
GPIO32 OPWM0 /RST_HUB
CI_DATA[7] G27
GPIO33 R173 R176 /RST_HUB
MTK_DVB_T2_TUNER

E27 D27
MTK_DVB_S_TUNER

MT5398_TS_IN[0] 1K 1K
Country_AJJA

GPIO34 SD_D0
MTK_DDR_1.25GB

D29 C27
MODULE_V13

MTK_CP_BOX

MT5398_TS_IN[1] GPIO35 SD_D1

MTK_SMALL
FRC_120Hz

D28 D26
Country_TW

PWM2_PULL_DOWN_1K
MTK_FHD

MT5398_TS_IN[2] GPIO36 SD_D2

R140
4.7K
R137
4.7K

R145
4.7K
R130
4.7K

R146
4.7K
R131
4.7K
R123
4.7K
R106
4.7K

R108
4.7K

R149
4.7K

H28 C26 PWM1_PULL_DOWN_1K

R105
4.7K

OPT

MT5398_TS_IN[3]
CI SLOT -> SOC GPIO37 SD_D3
J27 A28
MT5398_TS_IN[4] GPIO38 SD_CMD
G29 E24
GPIO45(EMMC_RST) is dedicated to reset MT5398_TS_IN[5] GPIO39 SD_CLK
HIGH LOW G31 SMARTCARD_CLK/SD_EMMC_DATA[0]
MT5398_TS_IN[6] SMARTCARD_CLK/SD_EMMC_DATA[0]
EMMC for improving A1’s leakage current GPIO40 SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]
MODEL_OPT_0 G28 SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]
MT5398_TS_IN[7]
MODEL_OPT_0 Country_TW TW Non_TW GPIO41 SMARTCARD_RST/SD_EMMC_DATA[2]
/USB_OCD2 B28 SMARTCARD_RST/SD_EMMC_DATA[2]
MODEL_OPT_1 GPIO42
K28 SMARTCARD_DET/SD_EMMC_DATA[3]
MODEL_OPT_1 FRC FRC(120Hz) No FRC(60Hz) /USB_OCD1 SMARTCARD_DET/SD_EMMC_DATA[3]
MODEL_OPT_2 GPIO43 SMARTCARD_VCC/SD_EMMC_CMD
/USB_OCD3 E25 SMARTCARD_VCC/SD_EMMC_CMD
MODEL_OPT_2 Panel FHD HD GPIO44 SMARTCARD_DATA/SD_EMMC_CLK
D21 SMARTCARD_DATA/SD_EMMC_CLK
MODEL_OPT_3 EMMC_RST GPIO45
MODEL_OPT_3 Country_AJJA AJJA Non_AJJA G23
/S2_RESET USB_CTL1 GPIO46
MODEL_OPT_4 C28
MODEL_OPT_4 Module V13 V12 #SIL_RESET GPIO47
MODEL_OPT_5 F24 AF15
M13 vs Lean Smart EPI_LOCK6 AB8
GPIO48 LED_PWM1 LED_PWM1
MODEL_OPT_5 DDR DDR_1.25G DDR_1.5G AG15
MODEL_OPT_6 CTS GPIO49 LED_PWM0 LED_PWM0
del. EPI_LOCK6 AA7
MODEL_OPT_6 CP BOX Enable Disable RTS GPIO50
MODEL_OPT_7 cause of EPI block deletion AD6
OTP_WRITE GPIO51
MODEL_OPT_8 MODEL_OPT_7 AC8 5V Tolerance
T2 Tuner Support Not Support MODEL_OPT_3 GPIO52
Non_Country_AJJA

AC7 AL16
MODEL_OPT_7 OPCTRL_11_SCL
MTK_NON_DVB_T2_TUNER

MODEL_OPT_9 GPIO53 OPCTRL11

MTK_NON_DVB_S_TUNER

MODEL_OPT_8 S Tuner Support Not Support AB6 AM16

MODEL_OPT_5 GPIO54 OPCTRL10 OPCTRL_10_SDA
NON_Country_TW

MTK_NON_CP_BOX

MODEL_OPT_10 SC_ID_SOC AC6 AE17

MTK_DDR_1.5GB
NON_FRC_60Hz

MODEL_OPT_9 MODEL_OPT_6 GPIO55 OPCTRL9 COMP1_DET

MODULE_V12

DDR DDR_0.78G NON_DDR_0.78G NON_EU AG19

MTK_LARGE

OPCTRL8 SC_DET
MTK_HD

R169
R129
4.7K

10K
R103
4.7K

AJ23 AH17
R104
4.7K

R128
4.7K
R122
4.7K
R107
4.7K

R139
4.7K
R136
4.7K

R143
4.7K

R144
4.7K

R148
4.7K

M13 vs Lean Smart ADIN0_SRV OPCTRL7 OPCTRL7

M13 vs Lean Smart MODEL_OPT_10 EPI OPT R170
Default Option Name change 10K AH23 AE19
Option Name change ADIN1_SRV OPCTRL6 HP_DET
Support to Opt AE28 AH19
Not Support to Deafult ADIN2_SRV OPCTRL5 AV1_CVBS_DET
AD28 AK16
USB_CTL3 MODEL_OPT_0 ADIN3_SRV OPCTRL4 AMP_RESET_SOC
AF22 AG17
M_RFModule_RESET ADIN4_SRV OPCTRL3 OPCTRL3 R182
DDR_1.25G DDR_1.5G DDR_0.768G AK21 AJ17
OPC_EN ADIN5_SRV OPCTRL2 RF_SWITCH_CTL AMP_RESET_SOC AMP_RESET_N
AG24 AF19 33
/TU_RESET1 ADIN6_SRV OPCTRL1 OPCTRL_1_SCL
MODEL_OPT_5 AM18 AJ19 R185
High Low High OPCTRL_0_SDA
MODEL_OPT_4 /S2_RESET ADIN7_SRV OPCTRL0 10K
MODEL_OPT_9
Low Low High

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS MID_MAIN_1 2013.07.16
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 508
 PLACE AT JACK SIDE
Close to JACK Close to Main Chip

C345
+5V_NORMAL 10uF 1608 sizs For EMI 1.0Vpp 1608 sizs For EMI
16V R344
0 R374
COMP1/AV1/DVI_L_IN COMP1/AV1/DVI_L_IN_SOC COMP1_Y/AV1_CVBS COMP1_Y/AV1_CVBS_SOC
R308 30K 1/4W
1.2K R328 3216

ZD302
OPT C388 C394

ADLC 5S 02 015
C338 C342 C384
470K 27pF 27pF R355
560pF 100pF 75 10pF
OPT 50V 50V 50V
50V 50V
OPT OPT 1% R381
R302 10V OPT 0
180 COMP1_COM_SOC
ARC C311 1uF
HDMI_ARC 1/16W
R303
82 R309 C346 1608 sizs For EMI
100K 10uF 0
1608 sizs For EMI COMP1_Pb R373 COMP1_Pb_SOC
16V R345
COMP1/AV1/DVI_R_IN COMP1/AV1/DVI_R_IN_SOC C386 C391
30K R354 C379
27pF 27pF

ZD304
ADLC 5S 02 015
50V 50V 75 10pF
R329 C339 C343
OPT OPT 1% 50V
470K 560pF 100pF
OPT 50V 50V
OPT

1608 sizs For EMI

0 R372
COMP1_Pr COMP1_Pr_SOC

C385 C392 C378

R353
27pF

ZD306
27pF 75 10pF

ADLC 5S 02 015
50V 50V 50V
FOR EMI 1%
OPT OPT

IC105
LGE2122[A2_M13]

IC105 Y1
TXC4N
BE0P
LGE2122[A2_M13] Y2
TXC4P
BE0N
W3
BE1P TXC3N
W4
BE1N TXC3P
V26 AG30 V3
BE2P TXCCLKN
HDMI_CEC TP381 HDMI_CEC HDMI_0_RX_0 V4
AG31 TXCCLKP
HDMI_0_RX_0B BE2N
AC27 AF30 V1
BECKP TXC2N
HDMI_0_SCL HDMI_0_RX_1 V2
AB27 AF31 TXC2P
DDC_SCL_3_JACK HDMI_1_SCL HDMI_0_RX_1B BECKN
AA26 AE32 U3
DDC_SCL_1_SOC BE3P TXC1N
HDMI_2_SCL HDMI_0_RX_2 AA8 U4
W27 AE33 MODEL_OPT_8 TCON0 TXC1P
DDC_SCL_MHL HDMI_3_SCL HDMI_0_RX_2B BE3N
AG32 AA9 T3
MODEL_OPT_9 TCON1 BE4P TXC0N
HDMI_0_RX_C M13 vs Lean Smart W6 T4
AC26 AG33 MODEL_OPT_10 TCON2 TXC0P
HDMI_0_SDA HDMI_0_RX_CB del. list BE4N
AB26 U6
DDC_SDA_3_JACK HDMI_1_SDA (cause of EPI Block deletion) GCLK_SOC TCON3
Y26 AD30 GCLK_SOC U7 AD1
DDC_SDA_1_SOC D0+_HDMI3_JACK MCLK_SOC TCON4 BO0P TXD4N
HDMI_2_SDA HDMI_1_RX_0 MCLK_SOC V8 AD2
W26 AD31 GST_SOC TCON5 TXD4P
DDC_SDA_MHL HDMI_3_SDA HDMI_1_RX_0B D0-_HDMI3_JACK GST_SOC BO0N
AC32 EO_SOC V6 AC3
D1+_HDMI3_JACK EO_SOC TCON6 BO1P TXD3N
HDMI_1_RX_1 VCOM_DYN AB7 AC4
AE29 AC33 VCOM_DYN PMIC_RESET TXD3P
HDMI_0_PWR5V HDMI_1_RX_1B D1-_HDMI3_JACK TCON7 BO1N
R305 Y27 AC30 PMIC_RESET W9 AB3
5V_HDMI_3_JACK 1K TCON8 BO2P TXDCLKN
HDMI_1_PWR5V HDMI_1_RX_2 D2+_HDMI3_JACK U8 AB4
R306 1K AA28 AC31 2D/3D_CTL TXDCLKP
5V_HDMI_1_SOC HDMI_2_PWR5V HDMI_1_RX_2B D2-_HDMI3_JACK TCON9 BO2N
V28 AE30 U9 AB1
5VBUS R307 1K MODEL_OPT_2 TCON10 BOCKP TXD2N
HDMI_3_PWR5V HDMI_1_RX_C CK+_HDMI3_JACK V9 AB2
AE31 PCM_5V_CTL TCON11 TXD2P
HDMI_1_RX_CB CK-_HDMI3_JACK BOCKN
AD29 V7 AA3
USB_CTL2 TCON12 BO3P TXD1N
HDMI_0_HPD AA4
AA27 Y30 +1.2V_MTK_AVDD TXD1P
HDMI_HPD_3_JACK HDMI_1_HPD HDMI_2_RX_0 D0+_HDMI1_SOC BO3N
AA29 Y31 Y3
HDMI_HPD_1_SOC D0-_HDMI1_SOC BO4P TXD0N
HDMI_2_HPD HDMI_2_RX_0B Y4
V29 W32 TXD0P
HDMI_HPD_4_MHL HDMI_3_HPD HDMI_2_RX_1 D1+_HDMI1_SOC BO4N
+1.2V_MTK_AVDD W33 AN1
HDMI_2_RX_1B D1-_HDMI1_SOC AVDD12_LVDS_1
AA33 W30 C350 C354 AN2 AH1
D2+_HDMI1_SOC AVDD12_LVDS_2 AE0P TXA4N
AVDD12_HDMI_0_RX HDMI_2_RX_2 0.1uF 0.1uF VDD3V3 AN3 AH2
AA32 W31 TXA4P
C303 C306 AVDD12_HDMI_1_RX HDMI_2_RX_2B D2-_HDMI1_SOC AVDD12_LVDS_3 AE0N
P33 AA30 AN4 AG3
0.1uF 0.1uF CK+_HDMI1_SOC AVDD33_LVDS AE1P TXA3N
VDD3V3_HDMI AVDD12_HDMI_2_RX HDMI_2_RX_C AG4
P32 AA31 TXA3P
AVDD12_HDMI_3_RX HDMI_2_RX_CB CK-_HDMI1_SOC C347 AE1N
AF3
0.1uF AE2P TXACLKN
AH33 U30 AM4 AF4 CI_ADDR[0-14]
D0+_HDMI4_MHL AVSS12_LVDS_1 AE2N TXACLKP
AVDD33_HDMI HDMI_3_RX_0 AM3 AF1
U31 AVSS12_LVDS_2 TXA2N
HDMI_3_RX_0B D0-_HDMI4_MHL AECKP CI_ADDR[0]
C304 C307 T32 AF5 AF2 TP312
D1+_HDMI4_MHL AVSS12_LVDS_3 AECKN TXA2P CI_ADDR[1]
0.1uF 0.1uF HDMI_3_RX_1 AE3
T33 TXA1N TP313
HDMI_3_RX_1B D1-_HDMI4_MHL AE3P CI_ADDR[2]
T30 AE5 AE4 TP314
D2+_HDMI4_MHL AVSS33_LVDS_1 AE3N TXA1P CI_ADDR[3]
HDMI_3_RX_2 AC5 AD3
AE27 T31 TXA0N TP315
AVSS33_HDMI_RX_1 HDMI_3_RX_2B D2-_HDMI4_MHL AVSS33_LVDS_2 AE4P CI_ADDR[4]
T25 V30 V5 AD4 TP316
CK+_HDMI4_MHL AVSS33_LVDS_3 AE4N TXA0P CI_ADDR[5]
AVSS33_HDMI_RX_2 HDMI_3_RX_C
W25 V31 TP317
AVSS33_HDMI_RX_3 HDMI_3_RX_CB CK-_HDMI4_MHL CI_ADDR[6]
AD27 T1 AM1 TP318
REXT_VPLL AO0P TXB4N CI_ADDR[7]
AVSS33_HDMI_RX_4 AM2
R343 TXB4P TP319
AO0N CI_ADDR[8]
24K AL3 TP320
AO1P TXB3N CI_ADDR[9]
1% AL4 TP321
AO1N TXB3P MT5398_MCLKI CI_ADDR[10]
AK3 TP322
AO2P TXBCLKN MT5398_MIVAL_ERR CI_ADDR[11]
AK4 TP323
AO2N TXBCLKP MT5398_MISTRT CI_ADDR[12]
AK1 TP324
IC105 AOCKP TXB2N CI_ADDR[13]
AK2 TP325
LGE2122[A2_M13] AOCKN TXB2P CI_ADDR[14]
AJ3 TP326
AO3P TXB1N
AJ4 MT5398_TS_OUT[0-7] TP327
AO3N TXB1P For PCB Pattern
AH3 TP328
H32 AL13 AO4P TXB0N
USB_DP3 USB_DP_P0 TXVP_0 EPHY_TDP AH4 HP_OUT TP329
H33 AM13 AO4N TXB0P HP_OUT MT5398_TS_OUT[0]
USB_DM3 USB_DM_P0 TXVN_0 EPHY_TDN For PCB Pattern 1.2K R351 1.2K R369 TP330
HP_ROUT_MAIN MT5398_TS_OUT[1]
1.2K R352 1.2K R370 TP331
J32 AL12 HP_LOUT_MAIN MT5398_TS_OUT[2]
USB_DP2 USB_DP_P1 RXVP_1 EPHY_RDP SC_R_IN_SOC HP_OUT C377 C383 C390 C395 TP332
J31 AM12 HP_OUT MT5398_TS_OUT[3]
1200pF 1200pF 1200pF
USB_DM2 USB_DM_P1 RXVN_1 EPHY_RDN SC_L_IN_SOC IC105 1200pF
MT5398_TS_OUT[4]
TP333
Port was changed !!!! LGE2122[A2_M13] HP_OUT HP_OUT HP_OUT HP_OUT
TP334
K32 AF13 MT5398_TS_OUT[5]
USB_DP1 USB_DP_P2 PHYLED1 MODEL_OPT_1 CI_DATA[0-7] TP335
K31 AJ13 SCART_Rout_SOC MT5398_TS_OUT[6]
WIFI USB_DM1 USB_DM_P2 PHYLED0 /TU_RESET2 TP336
SCART_Lout_SOC MT5398_TS_OUT[7]
0 R382 AL32 AK30 TP337
WIFI_DP AN10 AN12 24K R315 CI_DATA[0]
USB_DP_P3 REXT AIN1_R_AADC AR0_ADAC TP338
0 AM10 AN32 AJ29 CI_DATA[1]
USB_DM_P3 AVDD_33SB AIN1_L_AADC AL0_ADAC TP339
Wake On Lan AM33 CI_DATA[2]
WIFI_DM R383 VDD3V3 PC_R_IN_SOC TP379 AIN2_R_AADC
AM31 AJ31 TP340
WIFI K33 AN14 CI_DATA[3]
AVDD33_USB_P0P1P2 AVDD33_ETH C328 PC_L_IN_SOC TP380 AIN2_L_AADC AR1_ADAC TP341
C398 C399 AN8 AE13 AM32 AK29 CI_DATA[4]
5pF 5pF 0.1uF AIN3_R_AADC AL1_ADAC TP342
AVDD33_USB_P3 AVSS33_ELDO AK33 CI_DATA[5]
50V 50V C302 AIN3_L_AADC TP343
WIFI WIFI 0.1uF M25 AC16 AL33 AJ30 CI_DATA[6]
COMP1/AV1/DVI_R_IN_SOC AIN4_R_AADC AR2_ADAC Ready For commercial Audio_R_OUT TP344
AVSS33_USB_P1 AVSS33_LD AN33 AH28 CI_DATA[7]
AE11 AC15 COMP1/AV1/DVI_L_IN_SOC
AVSS33_USB_P3 AVSS33_COM AIN4_L_AADC AL2_ADAC Ready For commercial Audio_L_OUT TP345
MT5398_TS_IN[0] TP346
MT5398_TS_IN[1] TP347
MT5398_TS_IN[2] TP348
Close to AVDD33_ADAC & AVDD33_AADC AJ33
AVDD33_ADAC MT5398_TS_IN[3]
AC23 TP349
VDD3V3 SPDIF_OUT MT5398_TS_IN[4]
AVSS33_ADAC TP350
AVDD3V3_AADC
L304 AVDD3V3_AADCAJ32 MT5398_TS_IN[5] TP351
ARC
AVDD3V3_AADC AVDD33_AADC MT5398_TS_IN[6] TP352
C365 C305 C362 AC24 AG9
10uF AVSS33_AADC ALIN MT5398_TS_IN[7] TP353
1uF 0.1uF AG10
10V 10V ASPDIF0
TUNER_SIF AN31 V27 SC_ID_SOC TP354
VMID_AADC ASPDIF1 /CI_CD2
AK9 R366 100 TP355
AOBCK AUD_SCK /CI_CD1
Close to MT5369 C352 0.01uF AH25 AJ9 R367 100 TP356
MPXP AOLRCK AUD_LRCK
AF10 R368 100 /PCM_IORD TP357
R339 TU_HK AOMCLK AUD_MASTER_CLK
TU_S/N/Q_T/US/KR/TW AH9 R371 100 /PCM_IOWR TP358
C312 2.2K AUD_LRCH
AOSDATA4
TU_HK C363 AK8 PCM_RST TP307
Close to Tuner C358
1uF
AOSDATA3
AJ8
C387 C389 C393 C396
/PCM_REG
0.1uF Don’t use as GPIO 22pF 22pF 22pF 33pF TP308
33pF AOSDATA2
TU_S/N/Q_T/US/KR/TW

TU_S/N/Q_T/US/KR/TW 10V AH8

R346 OPT OPT OPT OPT /PCM_CE1 TP309
1K AOSDATA1
R334 51 AJ10 MT5398_TS_SYNC TP310
IF_P AOSDATA0
C336 1uF /PCM_WE
TU_S/N/Q_T/US/KR/TW TP311
10V /PCM_OE
R380

TP359
TU_S/N/Q_T/US/KR/TW TU_S/N/Q_T/US/KR/TW
1K

R331 MT5398_TS_VAL TP360

1K C337 1uF R335 51 CI_A_VS1 TP361
IF_N IC105 MT5398_TS_CLK TP362
10V TU_S/N/Q_T/US/KR/TW
TU_S/N/Q_T/US/KR/TW
C310
LGE2122[A2_M13] /PCM_IRQA TP363
/PCM_WAIT TP364
33pF SC_R_IN_SOC TP365
TU_S/N/Q_T/US/KR/TW VDD3V3 AM27 AK18 SC_L_IN_SOC
ADCINP_DEMOD HSYNC TP376 TP366
+1.2V_MTK_AVDD AN27 AL18
ADCINN_DEMOD VSYNC TP305 SC_CVBS_IN_SOC TP367
AL20
C364 RP TP303 SC_COM_SOC TP368
AN26 AM20
C351 0.1uF AVDD33_DEMOD GP TP306 SC_G_SOC TP369
AL19
0.1uF BP TP304 SC_R_SOC TP370
AN28 AN20
AVDD12_DEMOD COM TP382 SC_B_SOC TP371
AK19
SOG TP383 SC_FB_SOC TP372
AL28 AG22
TU_S/N/Q_T/US/KR/TW TU_S/N/Q_T/US/KR/TW AVSS33_DEMOD VGA_SDA TP301 DTV/MNT_V_OUT_SOC TP373
AL27 AH22
R332 10K R342 10K AVSS12_DEMOD VGA_SCL TP302 SCART_Rout_SOC
IF_AGC TP374
HP_OUT C355 SCART_Lout_SOC TP375
Close to Tuner AL21
L303 C341 0.047uF COM1 SC_COM_SOC
BLM18PG121SN1D 0.047uF TU_S/N/Q_T/US/KR/TW AK22
PB1P SC_G_SOC PCM_5V_CTL TP377
TU_S/N/Q_T/US/KR/TW L26 AL22
HP_LOUT_AMP HP_LOUT IF_AGC PR1P SC_R_SOC SC_DET TP378
M28 AM21
Close to MT5369 TP300 RF_AGC Y1P SC_B_SOC
HP_OUT AN21
C332 SOY1 SC_FB_SOC
AJ27 AM23 0.01uF C371 51 R361
0.22uF LOUTN COM0
10V AK27 AL23 0.01uF C372 51 R362 For PCB Pattern
LOUTP PB0P
AL24 0.01uF C373 51 R363
PR0P COMP1_COM_SOC
N27 AN23 0.01uF C374 51 R364
OSCL2 OSCL2 Y0P COMP1_Pb_SOC
N26 AK23 1500pF C375
OSDA2 OSDA2 SOY0 COMP1_Pr_SOC
COMP1_Y/AV1_CVBS_SOC
AH24
VDACX_OUT
AJ24 10 R350
HP_OUT VDACY_OUT DTV/MNT_V_OUT_SOC
SC_CVBS_IN_SOC
L302 EU
VDD3V3
BLM18PG121SN1D AK26 AN25
For PCB Pattern CVBS3P AVDD33_VIDEO
HP_ROUT_AMP HP_ROUT R341 100 C360 0.047uF AM25
COMP1_Y/AV1_CVBS_SOC CVBS2P
HP_OUT R340 100 C359 0.047uF AH26
C331 TU_CVBS CVBS1P
TU_HK TU_HK AK25 AN18
0.22uF CVBS0P AVDD12_RGB
10V C361 1uF AJ26 +1.2V_MTK_AVDD
CVBS_COM
Near the SOC
VDD3V3
AM26 AC19
AVDD33_CVBS AVSS33_VDAC_BG C382
AK17
Place at JACK SIDE AB20
AVSS12_RGB
AVSS33_VDAC
AE20
0.1uF

AVSS33_CVBS_1
AB22
AVSS33_CVBS_2

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS MID_MAIN_2 2013.07.16
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 509
 FROM LPB & PSU
HDMI LEAKAGE Workaround in MTK A2(A0) (Default= with HDMI_LEAKAGE) +12V TYP 1450mA
+3.5V_ST

R2408
MMBT3906(NXP)
Q2401
M13 vs 14y Smart TV
Apply New Wafer (P2401-1*1)
Change Pin Assign(P2401)
+3.3V_NORMAL
L2408
BLM18SG121TN1D
PANEL_POWER
R2454
DEV_POWER_WAFER_18PIN 0 OPT
1 3
RL_ON 10K PANEL_VCC
1/16W Q2407
2 P2400 5% DMP2130L
R2401 SMAW200-H24S5 +3.3V_NORMAL C2433

D
10K C2432 0.1uF
R2426 0.01uF

R2442
L/DIM_OUT PANEL_VCC 50V
1K 50V

33K

PANEL DISCHARGE RESISTOR

+3.5V_ST R2425

PANEL DISCHARGE RESISTOR

L2402 INV_CTL R2459
PWR ON 1 INV ON 100 33
UBW2012-121F 2 R2453 G
3.5V PDIM#1 L/DIM0_SCLK L/DIM0_SCLK_PWR
3 4 PWM_DIM1 10K C2435 C2440
3.5V 3.5V L/DIM_OUT VDD3V3_HDMI 4.7uF 1uF
5 6 +24V R2458

R2451

R2452
25V

1/8W
C2406 L2403

1/8W
5V 50V C2443

2K

2K
GND 7 8 PDIM#2 33 OPT
ZD2403 0.1uF PWM_DIM2 UBW2012-121F L/DIM0_MOSI L/DIM0_MOSI_PWR 0.1uF
16V 24V 9 10 24V
L/DIM_OUT 50V

R2441
5.6K
GND 11 12 GND OPT R2456
C2413 C2458

D
12V 12V 33
13 14 0.1uF 10uF L/DIM0_VS L/DIM0_VS_PWR NTR4501NT1G
12V NC 50V 35V

L/DIM_OUT
+12V 15 16 Q2408

R2457
C

4.7K
L2401 GND 17 18 GND R2437
UBW2012-121F C2453 10K B Q2406
GND 19 20 GND PANEL_CTL
0.1uF MMBT3904(NXP)
C2401 GND 21 22 L/DIMO_VS 16V
19 L/DIM0_VS_PWR
0.1uF L/DIM0_MOSI 23 24 L/DIM0_SCLK E
L/DIM0_MOSI_PWR L/DIM0_SCLK_PWR
.

50V

25
SMAW200-H18S5
IC2401-*3
P2401
APX803D29
DEV_POWER_WAFER_24PIN
VCC 3 2 RESET

IC2401-*5 1
IC2401-*4
APX803D29 GND
APX803D29

VCC 3 2 RESET
P_DET_BOTH_24_3.5V_DIODES

IC2401-*1
VCC 3 2 RESET
+5V_Normal
1 1
NCP803SN293
GND R2412-*1 GND P_DET_BOTH_12_24V_DIODES +5V_NORMAL
8.2K
P_DET_BOTH_12_3.5V_DIODES VCC 3 2 RESET
P_DET_BOTH_12_24V IC2401-*2
1 IC2404
NCP803SN293
R2411-*1 RT8289GSP [EP]GND

JP2411
GND

JP2408

JP2409

JP2410
P_DET_BOTH_24_3.5V_OnSemi P_DET_BOTH_12_24V C2410-*2 C2423
1.5K
R2410-*1 P_DET_BOTH_12_24V 1% R2416-*2 0.1uF 0.01uF
P_DET_BOTH_12_3.5V 100K VCC 3 2 RESET 50V L2407
2.7K R2418-*1 50V 4.7uH
1% 100 P_DET_BOTH_12_24V BOOT SW
R2410-*2 1 1 8
P_DET_BOTH_12_24V
2.7K

THERMAL
P_DET_BOTH_12_3.5V P_DET_BOTH_24_3.5V C2410-*1 1% R2418-*2 GND P_DET_BOTH_12_24V_OnSemi 125C 125C

D2401
B540C
R2409-*1 0.1uF 100 C2425 C2426 C2429
NC_1 VIN C2428

40V
1.2K R2416-*1 50V 2 7 22uF 22uF 0.1uF
P_DET_BOTH_12_24V 10uF 16V
1% 100K P_DET_BOTH_24_3.5V R2409-*2 P_DET_BOTH_12_24V 10V 10V
10V
P_DET_BOTH_24_3.5V 1.2K
+24V NC_2 GND
1% 3 6

Power_DET IC2402-*1
APX803D29
L2406

BLM18PG121SN1D
FB
4
5A 5
EN

POWER_ON/OFF1
POWER_ON/OFF2_1
POWER_ON/OFF2_2
+12V VCC 3 2 RESET
+3.5V_ST R2417 POWER_ON/OFF2_3
100K +3.5V_ST POWER_ON/OFF2_4
1 POWER_ON/OFF2_3
C2417
P_DET_ONLY_12V GND C2422
R2421 P_DET_DIODES
10uF 0.1uF
R2410 R2413 10K 35V 50V R2439
0 IC2402 10K
2.7K OPT
1% 5% NCP803SN293 1%
C2427
P_DET_BOTH_24_3.5V R2419 51K 0.1uF
POWER_DET
VCC 3 2 RESET
100 R2438 R1 16V

R2436
16K
R2
1%
C2411 1
P_DET_ONLY_12V 0.1uF GND P_DET_OnSemi
R2409 16V
1.2K C2424
1% C2412 150pF
0.1uF 50V
16V

P_DET_BOTH_12_3.5V
+3.5V_ST R2416
+24V
100K
not to RESET at 8kV ESD
Vout=1.222*(1+R1/R2)
On-semi R2412
8.2K
R2400
0 IC2401
P_DET_BOTH_12_3.5V NCP803SN293

P_DET_BOTH_24_3.5V R2418
VCC RESET 100
3 2
R2411 1 P_DET_BOTH_12_3.5V
1.5K C2410 24V-->3.48V
1% 0.1uF GND
P_DET_BOTH_12_3.5V_OnSemi 12V-->3.58V
50V
P_DET_BOTH_24_3.5V
P_DET_BOTH_12_3.5V ST_3.5V-->3.5V

DDR MAIN 1.5V

DDR MAIN 1.5V
POWER_ON/OFF2_1
R2430

+3.3V_NORMAL
10K

C2420 +3.3V_NORMAL
MAX 3.4 A
0.1uF +12V
+3.5V_ST 16V C2455
+1.2V_MTK_CORE 0.1uF
+1.5V_DDR L2410
L2409 IC2405 2uH
+12V 16V TPS54327DDAR [EP]GND
BLM18PG121SN1D
L2405
EP[GND]

VIN_3

PWRGD

L2404 BLM18PG121SN1D 16V NR8040T2R0N

BOOT

EN VIN

R2427
1 8
L2400 0.1uF
EN

IC2400 2uH

THERMAL
C2437 C2438 C2439 C2442 C2444 C2445

30K
BD86106EFJ

1%
BLM18PG121SN1D [EP] L2411 Placed on SMD-TOP VFB VBST 10uF 10uF 10uF 10uF 100pF

9
16

15

14

13

2 7
VIN_1 PH_3 2.2uH 10V 10V 10V 10V 50V
1 12 OPT
PGND
1 8
SW_2
THERMAL VREG5 SW R1

R2440

1/16W
VIN_2 PH_2
R2404

2 11 3 6

ZENER_3.3V_NORMAL
17

3.3K
THERMAL

C2407 C2408 C2409 C2414 C2441 C2430 C2431 C2434

5.1K

Placed on SMD-TOP 10uF 10uF 10uF 10uF 47pF GND_1 PH_1 NR5040T2R2N 10uF 10uF 0.1uF
1%

VIN SW_1 3 10
9

3A

1%
2 7 C2418 C2419 SS GND
10V 10V 10V 10V 50V C2448 IC2403 C2457 16V 16V 16V 4 5

ZD2400
C2405 OPT 10uF 10uF 0.1uF GND_2 4 9 SS/TR
TPS54319TRE C2456 C2451 C2454 C2447 0.1uF OPT
AGND EN
10uF 10uF 10uF 10uF

5V
3 6 0.0068uF 10V 10V 16V 16V
5

C2400 C2402 C2403 R2402 R1 C2450 10V 10V 10V 10V

10uF 10uF 0.1uF 6.8K 50V
AGND

VSENSE

COMP

RT/CLK

FB
6A COMP
ZD2401

16V 16V 16V 4 5

2.5V

OPT

R2428
0.01uF
47K 1%
R2455

10K
50V

1%
R2
OPT
ZD2402
2.5V
R2406
10K
1%

R2432 C2452
OPT

R2403 1/16W 330K 5% 100pF R2414

10K
POWER_ON/OFF1 R2 R1 POWER_ON/OFF2_2
10KC2436 C2415 C2416
C2404 50V
R2431 C2421 1uF 3300pF
0.1uF 4700pF 0.1uF
15K 10V 50V
16V 16V
1/16W 5% 50V

R2433
56K R2
1/16W
1%
Vout=0.765*(1+R1/R2)
3A
Vout=0.8*(1+R1/R2)
Vout=0.827*(1+R1/R2)=1.521V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS MID_POWER
2011.11.25
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 24
 Renesas MICOM

For Debug For CEC

+3.5V_ST
+3.5V_ST

8pF
8pF
MICOM_DEBUG

R3016 1K
R3014 10K

R3034

C3003
C3002
R3033 LOGO_LIGHT
Don’t remove R3014,

MICOM_DEBUG
MICOM_DEBUG 27K 120K

LOGO_LIGHT
MICOM_RESET
not making float P40

G
P3000
12507WS-04L D3000
X3000
BAT54_SUZHO
1 CEC_REMOTE HDMI_CEC

S
32.768KHz
2
MICOM_DEBUG Q3001 HDMI_WAUP:HDMI_INIT +3.5V_ST
RUE003N02 R3028
3
HDMI_CEC_FET_ROHM 4.7M

G
4
MICOM_RESET OPT
Q3001-*1 MHL_DET
5
SI1012CR-T1-GE3 MHL_DET

10K
D

S
HDMI_CEC_FET_VISHAY

R3032

10K

R3030
GND MICOM_RESET_SW

MICOM_RESET_22OHM
SW3000
JTP-1127WEM

22
2 1

R3031
Ready For C3004

270K
OPT
P124/XT2/EXCLKS
0.1uF

0.47uF
Commercial
+3.5V_ST 16V 4 3

R3029
P122/X2/EXCLK

P41/TI07/TO07
C3001

P137/INTP0

P120/ANI19
P40/TOOL0
ST_BY_DET_CAM ST_BY_DET_CAM

P123/XT1
C3000

P121/X1
0.1uF
MICOM_RESET_33OHM
R3029-*1 33

RESET
+3.5V_ST

REGC
VDD
VSS
R3011 R3021
10K 10K
GP4 High/MID Power SEQUENCE

48
47
46
45
44
43
42
41
40
39
38
37
HDMI_EXT_EDID

P60/SCLA0 1 36 P140/PCLBUZ0/INTP6 RL_ON

I2C_SCL_MICOM
POWER_ON/OFF! P61/SDAA0 2 35 P00/TI00/TXD1
I2C_SDA_MICOM SCART_MUTE SCART_MUTE

EDID_WP EDID_WP
P62 3 34 P01/TO00/RXD1
POWER_ON/OFF2_4 POWER_ON/OFF2_4

P63 4 33 P130
POWER_ON/OFF2_1 PANEL_CTL
P31/TI03/TO03/INTP4 IC3000 P20/ANI0/AVREFP
POWER_ON/OFF2_1

WOL/WIFI_POWER_ON 5 32 KEY2

IR
P75/KR5/INTP9/SCK01/SCL01 6 R5F100GEAFB 31 P21/ANI1/AVREFM
POWER_ON/OFF2_2 KEY1
P74/KR4/INTP8/SI01/SDA01 7 30 P22/ANI2
HDMI_CEC MODEL1_OPT_1
P73/KR3/SO01 MICOM_LEAD_Au P23/ANI3
POWER_ON/OFF2_3 POWER_ON/OFF2_2 8 29 MODEL1_OPT_4

POWER_ON/OFF2_3
P72/KR2/SO21 9 28 P24/ANI4
MODEL1_OPT_0
P71/KR1/SI21/SDA21 10 27 P25/ANI5
EYE_SDA SIDE_HP_MUTE
POWER_ON/OFF2_4
P70/KR0/SCK21/SCL21 11 26 P26/ANI6
EYE_SCL MODEL1_OPT_3
P30/INTP3/RTC1HZ/SCK11/SCL11 12 25 P27/ANI7
CAM_PWR_ON_CMD CAM_PWR_ON_CMD MODEL1_OPT_2
SOC_RESET

13
14
15
16
17
18
19
20
21
22
23
24
EYE_Q
R3035

R3036
EYE_Q
3.3K

3.3K

+3.5V_ST

P50/INTP1/SI11/SDA11
P51/INTP2/SO11
P17/TI02/TO02
P16/TI01/TO01/INTP5
P15/PCLBUZ1/SCK20/SCL20
P14/RXD2/SI20/SDA20
P13/TXD2/SO20
P12/SO00/TXD0/TOOLTXD
P11/SI00/RXD0/TOOLRXD/SDA00
P10/SCK00/SCL00
P146
P147/ANI18
MICOM MODEL OPTION MICOM MODEL OPTION
+3.5V_ST

0 1
MICOM_OLED_MAIN

MICOM_OLED_FRC
R3007-*1

R3007-*2

MODEL_OPT_0 NON LOGO LOGO For LOGO LIGHT

MICOM_NC4.5_5KEY

MICOM_LOGO_LIGHT
MICOM_TOUCH_KEY
10K

10K

10K

10K

10K
10K

56K

22K
MICOM_GED

MICOM_H13

MICOM_PDP

MODEL_OPT_1 TACT_KEY TOUCH_KEY Ready for sample set

R3002

R3003

R3006

R3007

R3013
R3010

MODEL_OPT_2 LCD / OLED PDP Need to Assign ADC port

MODEL_OPT_3 IR_wafer(12/15) IR_wafer(10pin) Ready for sample set

P124/XT2/EXCLKS
P122/X2/EXCLK

P41/TI07/TO07
MODEL_OPT_4 M13 H13

P137/INTP0

P120/ANI19
P40/TOOL0
MODEL1_OPT_0

P123/XT1
P121/X1
MODEL1_OPT_1

RESET
MODEL_OPT_5 NON_GED GED

REGC
VDD
VSS
MODEL1_OPT_2

MODEL1_OPT_3

48
47
46
45
44
43
42
41
40
39
38
37
MODEL1_OPT_4 P60/SCLA0 1 36 P140/PCLBUZ0/INTP6
P61/SDAA0 P00/TI00/TXD1

POWER_DET

SOC_RX

AMP_MUTE

CAM_CTL
2 35
WOL/ETH_POWER_ON

SOC_RESET

INV_CTL

MODEL1_OPT_5
WOL_CTL
POWER_ON/OFF1

SOC_TX
MODEL1_OPT_5

LED_R
P62 3 34 P01/TO00/RXD1
P63 4 33 P130
P31/TI03/TO03/INTP4 IC3000-*1 P20/ANI0/AVREFP
MICOM_NON_LOGO_LIGHT

5 32
P75/KR5/INTP9/SCK01/SCL01 6 R5F100GEAFB#30 31 P21/ANI1/AVREFM
MICOM_NC4_8KEY

MICOM_LCD/OLED

MICOM_TACT_KEY
MICOM_NON_GED

P74/KR4/INTP8/SI01/SDA01 P22/ANI2
10K

10K

10K

10K

10K

10K

7 30
MICOM_M13

P73/KR3/SO01 MICOM_LEAD_Cu P23/ANI3

8 29
P72/KR2/SO21 9 28 P24/ANI4
P71/KR1/SI21/SDA21 P25/ANI5
R3000

R3001

R3004

R3005

R3008

R3012

10 27
P70/KR0/SCK21/SCL21 11 26 P26/ANI6
P30/INTP3/RTC1HZ/SCK11/SCL11 12 25 P27/ANI7
LED_R

CAM_CTL

13
14
15
16
17
18
19
20
21
22
23
24
P50/INTP1/SI11/SDA11
P51/INTP2/SO11
P17/TI02/TO02
P16/TI01/TO01/INTP5
P15/PCLBUZ1/SCK20/SCL20
P14/RXD2/SI20/SDA20
P13/TXD2/SO20
P12/SO00/TXD0/TOOLTXD
P11/SI00/RXD0/TOOLRXD/SDA00
P10/SCK00/SCL00
P146
P147/ANI18
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS NetCast4.0 2013.02.05
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MICOM (RENESAS) 530
 CK+_HDMI4_JACK
CK-_HDMI4_JACK
D0+_HDMI4_JACK
D1+_HDMI4_JACK

D0-_HDMI4_JACK
D2+_HDMI4_JACK
D2-_HDMI4_JACK

D1-_HDMI4_JACK
CHANGE NET Demod_Core
1.2V_MHL
Demod_Core
L3302
BLM18PG121SN1D

IP4294CZ10-TBR
IP4294CZ10-TBR
TU_DEMOD_CORE

10
10

9
8
7
6
9
8
7
6

D3302
Close to SIL1292

D3303

1
2
3
4
5
1
2
3
4
5
Field Issue
Latch Up C3316 C3320

R3388
5.1
VDD3V3_HDMI (+3.3V_NORMAL -> VDD3V3)

R3389
0.1uF 0.1uF

5.1
16V 16V
VDD3V3_HDMI
SIL_HPD/CBUS

[EP]GND
VDD33_2

VDD33_1
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
+12V OPT
2N7002K

R3376

R3384 S
Q3304

1K 1.2V_MHL
OPT

SIDE
0

G VDD3V3_HDMI
1.2V_MHL

40
39
38
37
36
35
34
33
32
31
+5V_NORMAL
ADUC 20S 02 010L

5V_MHL
D VDD3V3_HDMI
RSVDL1 1 30 AVDD12 L3301
VDD12_1 TXC- BLM18PG121SN1D
2 29 CK-_HDMI4_MHL
C3311 C3318
R3356 THERMAL 0.1uF 0.1uF
10K RSVDL2 TXC+ 16V 16V
VA3302

BODY_SHIELD 3 41 28 CK+_HDMI4_MHL
R3371
ADUC 20S 02 010L

C3321
RESET 4 27 TX0-
820

5VBUS #SIL_RESET 0.1uF

D0-_HDMI4_MHL
16V
GND L3303 +12V C3314 PWR5V_DET 5 IC3304 26 TX0+ D0+_HDMI4_MHL
BLM18PG121SN1D D MHL_DET
R3370 OPT 0.1uF
R3351 INT TX1-
20 1K 16V 6 SIL1292CNUC 25 D1-_HDMI4_MHL
Q3314
VA3303

FREEPORT HP_DET 4.7K OPT

G PMBFJ177
DDC_SDA_MHL
DSDA 7 24 TX1+ D1+_HDMI4_MHL
5V_MHL
19
5V S
DSCL 8 23 TX2-
18 DDC_SCL_MHL D2-_HDMI4_MHL
GND R3348
CBUS/HPD TX2+
ADUC 20S 02 010L

17 SIL_HPD/CBUS 9 22 D2+_HDMI4_MHL
10K
DDC_DATA R3308 100
DDC_SDA_MHL VDD5_IN 10 21 HPD_IN HDMI_HPD_4_MHL
16 Improve EMI(Apply the Mold B/C Model)
DDC_CLK R3309 100 5V_MHL
ADUC 20S 02 010L

11
12
13
14
15
16
17
18
19
20
15 DDC_SCL_4_JACK R3358
NC
VA3300

VA3301

4.7K 5V_MHL
14 OPT
CE_REMOTE

RSVDNC
VREG33_OUT
PS_CTRL
HDMI_DET
GPIO1/CI2CA
GPIO0
CSDA
CSCL
CEC_A
VDD12_2
CEC_REMOTE C3313
13
CK- BODY_SHIELD BODY_SHIELD 0.1uF 1.2V_MHL R3362
BODY_SHIELD
CK-_HDMI4_JACK 16V 10K
12
CK_GND 20
20 20
EAG62611204

11
CK+ 19 19 HDMI_DET
10 CK+_HDMI4_JACK
19
HOT_PLUG_DETECT
HOT_PLUG_DETECT HOT_PLUG_DETECT

D0- 18 18
18 VDD[+5V] VDD[+5V] VDD3V3_HDMI
9 D0-_HDMI4_JACK VDD[+5V]
17 17
R3357 C
D0_GND +3.5V_ST 17 DDC/CEC_GND DDC/CEC_GND 10K Q3310
8 DDC/CEC_GND OPT B
16 16 R3355
16 SDA SDA MMBT3904(NXP)
D0+ SDA
MHL_DET

R3363 10K
7 15 15 E
D0+_HDMI4_JACK 15 SCL SCL
R3374

SCL 4.7K
D1- 14 14 OPT
10K

6 14 RESERVED RESERVED R3345

D1-_HDMI4_JACK RESERVED
D1_GND 13 13
E MMBT3906(NXP) 13 CEC CEC
5 R3375 CEC 4.7K
10K Q3302 12
12 12
D1+ TMDS_CLK- TMDS_CLK-
TMDS_CLK-
4 D1+_HDMI4_JACK 11 11
B 11 TMDS_CLK_SHIELD TMDS_CLK_SHIELD
D2- TMDS_CLK_SHIELD
3 C 10 10
D2-_HDMI4_JACK C 10 TMDS_CLK+ TMDS_CLK+
R3373 TMDS_CLK+
D2_GND 1K 9 9
2 B
MHL_DET 9
TMDS_DATA0-
TMDS_DATA0- TMDS_DATA0- #MHL_OCP TP3300

I2C_SDA4

I2C_SCL4
D2+ 1/16W Q3301 8 8
8
R3386

TMDS_DATA0_SHIELD TMDS_DATA0_SHIELD

HDMI_DET
1 TMDS_DATA0_SHIELD
180K

D2+_HDMI4_JACK 5% C3322 MMBT3904(NXP) E 7 7

0.1uF (CD_SENCE) 7
TMDS_DATA0+
TMDS_DATA0+ TMDS_DATA0+ Current Limit
16V 6 6 5VBUS
6 TMDS_DATA1- TMDS_DATA1-
OPT TMDS_DATA1-
R3387

5 5 IC3301 5V_MHL
120K

5 TMDS_DATA1_SHIELD TMDS_DATA1_SHIELD TPS2051BDBVR

51U019S-312HFN-E-R-B-LG TMDS_DATA1_SHIELD
4 4
4 TMDS_DATA1+ TMDS_DATA1+
JK3301 TMDS_DATA1+
3 3
3 TMDS_DATA2- TMDS_DATA2- D3322 OUT IN
TMDS_DATA2-
2 2 1 5
2 TMDS_DATA2_SHIELD TMDS_DATA2_SHIELD 5V_MHL
TMDS_DATA2_SHIELD +3.5V_ST 30V
1 1 ZD501 C3315
C3312
UI : HDMI3 FOOSUNG
1
TMDS_DATA2+ FOOSUNG
TMDS_DATA2+
FOOSUNG
TMDS_DATA2+
10uF
R3359 GND
2
5V
OPT
0.1uF
16V
10V 100K
DAADR019A DAADR019A
DAADR019A 5V_MHL

A1

A2
OC EN

MMBD6100
JK3301-*1 JK3303-*1
JK3300-*1 3 4 MHL_DET

D3301

R3332
10K
C
5V_HDMI_1_SOC R3338 #MHL_OCP
5V_HDMI_3_JACK 10K
R3361
47K
SIDE SIDE
VA3310
ADUC 20S 02 010L
DDC_SCL_MHL
VA3304 30V
ADUC 20S 02 010L DDC_SCL_4_JACK
BAT54_SUZHO
D3304
ADUC 20S 02 010L
ADUC 20S 02 010L

R3304 R3306
R3330 R3336 1K 4.7K 5V_MHL
BODY_SHIELD HDMI_INTERNAL_EDID
1K 4.7K
GND
BODY_SHIELD C Q3309
20 R3305 PMV48XP
C Q3300 B 1K
R3331
VA3311

20 HP_DET HDMI_HPD_1_SOC

D
FREEPORT
VA3305

Q3303 B 1K MMBT3904(NXP)
FREEPORT HP_DET HDMI_HPD_3_JACK 19
MMBT3904(NXP) 5V R3301
19 100K E R3321

30V

BAT54_SUZHO
D3312
30V

BAT54_SUZHO
D3313
R3379
5V R3327 4.7K
18
ADUC 20S 02 010L

22K
100K GND G
HDMI_EXT_EDID
ADUC 20S 02 010L

ADUC 20S 02 010L

18
GND 17
DDC_DATA R3302 100
17 DDC_SDA_1_SOC
DDC_DATA R3328 100 16
DDC_SDA_3_JACK DDC_CLK R3303 100
ADUC 20S 02 010L

16
ADUC 20S 02 010L

DDC_CLK R3329 100 15 DDC_SCL_1_SOC C R3380 R3307

VA3308

R3381
VA3309

DDC_SCL_3_JACK NC
VA3306

VA3307

15 22K B Q3311 1.8K 1.8K

ARC
HDMI_ARC
14
CE_REMOTE MHL_DET MMBT3904(NXP)
14 CEC_REMOTE
CE_REMOTE 13 DDC_SDA_MHL
CEC_REMOTE CK- E
D3319
VA3313

13
CK- D3320 12 IP4294CZ10-TBR DDC_SCL_MHL
IP4294CZ10-TBR CK_GND
12
EAG62611204

CK_GND 1 10
11 CK-_HDMI1_SOC
CK+
EAG62611204

1 10 2 9
11 CK-_HDMI3_JACK 10 CK+_HDMI1_SOC
CK+ 2 9
10 D0- 3 8
CK+_HDMI3_JACK
3 8 9 4 7
D0-
9 D0_GND D0-_HDMI1_SOC +5V_NORMAL
4 7 5 6
D0-_HDMI3_JACK 8 D0+_HDMI1_SOC
D0_GND 5 6
8 D0+_HDMI3_JACK D0+
7
HDMI_EXT_EDID

A1

A2
D0+

MMBD6100
7 D1-

D3314
6
D1- D3321
6 D1_GND CEC_REMOTE
IP4294CZ10-TBR 5 D3318
5V_HDMI_1_SOC +5V_NORMAL

C
D1_GND IP4294CZ10-TBR HDMI_EXT_EDID
5 1 10 D1+ E
D1-_HDMI3_JACK 4 1 10
D1+ 2 9
4 D1-_HDMI1_SOC MMBT3904(NXP)
ADUC 20S 02 010L
VA3312

D1+_HDMI3_JACK D2- EDID_WP

HDMI_EXT_EDID
3 2 9
D2- 3 8 D1+_HDMI1_SOC Q3313 B

HDMI_INTERNAL_EDID
3 3 8

A1

A2
4 7 D2_GND

HDMI_INTERNAL_EDID
C

R3378
2

R3377
D2_GND D2-_HDMI3_JACK 4 7 IC3300
5 6 D2-_HDMI1_SOC MMBD6100 C3302

47K
2 R3337 R3339 R3340

47K
D2+_HDMI3_JACK D2+ 5 6 0.1uF
1 M24C02-RMN6T D3300 16V 47K 47K 47K
D2+ D2+_HDMI1_SOC

C
1

E0 VCC
1 8
JK3300 DDC_SCL_1_SOC
R3390
HDMI_EXT_EDID

HDMI_EXT_EDID
JK3303 DDC_SDA_1_SOC
51U019S-312HFN-E-R-B-LG E1 WC 10K
51U019S-312HFN-E-R-B-LG 2 7 R3323 R3325
HDMI_EXT_EDID 47K 47K
R3319
UI : HDMI1 UI : HDMI2 E2
3
HDMI_EXT_EDID
6
SCL 22 DDC_SDA_MHL
DDC_SCL_1_SOC
HDMI_EXT_EDID
R3320
VSS SDA 22
4 5 DDC_SDA_1_SOC
HDMI_EXT_EDID

DDC_SCL_3_JACK

DDC_SDA_3_JACK

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS HDMI 4 2013.07.16
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 533
 RS-232C Control INTERFACE(NORTH AMERICA)
JK3700
PEJ034-01

Closed to Jack E_SPRING 3

RS232C_US
100
R3720
R_SPRING 4
+3.5V_ST HP_ROUT
T_SPRING 5
HP_LOUT

RS232C_US
B_TERMINAL2 7B

100
R3721
T_TERMINAL2 6B

OPT OPT
ZD3702 ZD3703
ADUC 20S 02 010L ADUC 20S 02 010L
RS232C_US 20V 20V +3.3V_NORMAL
RS232C_US C3713
0.1uF
IC3700 R3706
MAX3232CDR 10K
R3705
1K
C1+ VCC HP_DET
RS232C_US 1 16
C3708
0.1uF V+ GND
RS232C_US 2 15
C3709
0.1uF C1- DOUT1
3 14

RS232C_US C2+ RIN1

4 13
C3710
0.1uF C2- ROUT1
5 12
SOC_RX

V- DIN1
RS232C_US 6 11 SOC_TX
C3711
0.1uF DOUT2 DIN2
7 10

RIN2 ROUT2
8 9

EAN41348201

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 14Y Phone Jack 2013.08.27
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 537
 +3.3V_NORMAL

USB1
OCP USB1 DVR Ready
R4500 +5V_USB_1
10K R4501
10K
OPT
MAX 1.5A
IC4500
AP2171DM8G +5V_USB_1 3AU04S-305-ZC-(LG)
JK4500
+5V_NORMAL
GND NC

1
1 8
USB_Serial_2.2ohm USB_Serial_0ohm

USB DOWN STREAM

R4502 R4502-*1
IN_1 OUT_2 2.2 0

2
2 7 USB_DM1
USB_Serial_2.2ohm
C4500 R4503 USB_Serial_0ohm
C4501 2.2
0.1uF IN_2 OUT_1

3
3 6 10uF USB_DP1 R4503-*1
16V 0
10V
EN FLG C4502

4
4 5 10uF
/USB_OCD1
10V

5
USB_CTL1

+5V_USB_2
USB2
OCP USB2/3 MAX 1.5A
+3.3V_NORMAL

3AU04S-305-ZC-(LG)
JK4302
USB_Serial_0ohm
10K

10K

1
USB_Serial_2.2ohm R4303-*1
IC4306

USB DOWN STREAM

R4303 0
R4301

TPS2066CDGNR [EP]GND
R4302

2.2
USB_Serial_0ohm

2
+5V_NORMAL USB_DM2
USB_Serial_2.2ohm R4304-*1
R4304
GND FLT1 2.2 0
1 8 /USB_OCD2

3
C4302 USB_DP2
THERMAL

0.1uF +5V_USB_2
16V IN OUT1 C4322
9

2 7

4
10uF
10V

5
EN1 OUT2 +5V_USB_3
USB_CTL2 3 6

EN2 FLT2
USB_CTL3 4 5 /USB_OCD3

C4337 C4301
10uF 10uF
10V 10V
USB2/3_OCP_TI

IC4306-*1
DIODES TAIWAN INC
[EP]GND

GND
1 8
FLG1
+5V_USB_3
USB3
MAX 1.5A
THERMAL

IN OUT1
9

2 7
3AU04S-305-ZC-(LG)
JK4300
EN1 OUT2
3 6 USB_Serial_0ohm

1
R4305-*1
USB_Serial_2.2ohm

USB DOWN STREAM

EN2 FLG2 0
4 5 R4305
2.2
2
USB_DM3 USB_Serial_0ohm
USB_Serial_2.2ohm
R4306 R4306-*1
2.2 0
3

USB2/3_OCP_DIODES USB_DP3

C4310
4

10uF
5

10V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS USB2_USB3 2013.11.25
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 543
 Ethernet Block

C5000 C5001
0.1uF 0.01uF
16V 50V

MOLD_LAN_JACK METAL_LAN_JACK
JK5000-*1 JK5000
RV3-2032ADA3 RJ45VT-01SN002

TD+ 1
1 1
EPHY_TDP

TCT 2
2 2

TD- 3
3 3
EPHY_TDN

RD+ 4
4 4
EPHY_RDP

RCT 5
5 5

RD- 6
6 6
EPHY_RDN

R7 7
7 7
D5000 D5001 D5002 D5003
GND 8 5.5V 5.5V 5.5V 5.5V
8 8
LAN_ESD LAN_ESD LAN_ESD LAN_ESD

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LAN_VERTICAL 2013.11.26
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 550
 DEV_TU_KR_US DEV_TU_TW DEV_TU_KR_PIP
DEV_TU_AJ_T

TU6401-*1
DEV_TU_BR

TU6402-*1
DEV_TU_CO_T2

TU6402-*2
DEV_TU_AJ_T2

TU6402-*3
DEV_TU_HK

TU6402-*4
TU6401 TU6403 TU6402
TDJH-G101D TDJM-B101F TDJM-K101F TDJM-G105D TDJM-C301D

1
B1[+3.3V]
1
B1[+3.3V]
1
B1[+3.3V]
1
B1[+3.3V]
1
B1[+3.3V]
TDJH-H101F TDJK-T101F TDJM-H101F
NC_1 RF_SW_CTL RF_SW_CTL NC_1 RF_SW_CTL
2 2 2 2 2
IF_AGC AIF_AGC AIF_AGC AIF_AGC NC_1
3 3 3 3 3
SCL SCL_RF SCL_RF SCL_RF SCL_RF
4 4 4 4 4
SDA SDA_RF SDA_RF SDA_RF SDA_RF
5
IF[P]
5
AIF[P]
5
AIF[P]
5
AIF[P]
5
NC_2
B1[+3.3V] B1[+3.3V] B1[+3.3V]
6
IF[N]
6
AIF[N]
6
AIF[N]
6
AIF[N]
6
NC_3
1 1 1 +3.3V_LNA_TU 1
7 7 7 7 7
NC_2 NC_1 NC_1 NC_2 SIF
8
NC_3
8
NC_2
8
NC_2
8
NC_3
8
CVBS
NC_1 RF_S/W_CTL NC_1
9 9
NC_3
9
NC_3
9
NC_4
9
NC_4
2 2 2 RF_SWITCH_CTL_TU 2
10 10 10 10
A1 B1 NC_4 NC_4 B2[+3.3V] NC_5
A1
47
B1 11
ERROR
11
ERROR
11
ERROR
11
ERROR
IF_AGC IF_AGC M_DIF_AGC
12
GND_1
12
GND_1
12
GND_1
12
GND_1
3 3 3 IF_AGC_TU 3
SHIELD 13 13 13 13
MCLK MCLK MCLK MCLK
14
SYNC
14
SYNC
14
SYNC
14
SYNC
SCL SCL SCL_RF
15
VAILD
15
VAILD
15
VAILD
15
VAILD
4 4 4 I2C_SCL6_TU 4
16 16 16 16
D0 D0 D0 D0
17
D1
17
D1
17
D1
17
D1
SDA SDA SDA_RF
18
D2
18
D2
18
D2
18
D2
5 5 5 I2C_SDA6_TU 5
19 19 19 19
D3 D3 D3 D3
20
D4
20
D4
20
D4
20
D4
IF[P] IF[P] M_DIF[P]
21
D5
21
D5
21
D5
21
D5
6 6 6 IF_P 6
22 22 22 22
D6 D6 D6 D6
23
D7
23
D7
23
D7
23
D7
IF[N] IF[N] M_DIF[N]
24
RESET_DEMOD
24
RESET_DEMOD
24
RESET_DEMOD
24
RESET_DEMOD
7 7 7 IF_N 7
25 25 25 25
B2[+3.3V] B2[+3.3V] B3[+3.3V] B2[+3.3V]
26
SCL_DEMOD
26
SCL_DEMOD
26
SCL_DEMOD
26
SCL_DEMOD
NC_2 NC_1 S_SIF
27
B3[+1.1V]
27
B3[+1.1V]
27
B4[+1.1V]
27
B3[+1.1V]
8 8 8 TU_SIF_TU 8
28 28 28 28
NC_5 NC_5 F22_OUTPUT NC_6
29
SDA_DEMOD
29
SDA_DEMOD
29
SDA_DEMOD
29
SDA_DEMOD
NC_3 NC_2 S_CVBS
30 30 30 30
9 9 9 TU_CVBS_TU 9
A1 B1 A1 B1 A1 B1 A1 B1
A1
47
B1 A1
47
B1 A1
47
B1 A1
47
B1
NC_2
SHIELD SHIELD SHIELD SHIELD
10 10
A1 B1 A1 B1 B2[+3.3V]
A1 B1 A1 B1 11 +3.3V_TU 11
47 47 S_ERROR
12 FE_DEMOD1_TS_ERROR 12

TU_GND_B
TU_GND_A

GND_1
SHIELD SHIELD 13 13

TU_GND_A
TU_GND_B
S_MCLK
14 FE_DEMOD1_TS_CLK 14
S_SYNC
15 FE_DEMOD1_TS_SYNC 15
S_VALID
16 FE_DEMOD1_TS_VAL 16
S_DATA
17 FE_DEMOD1_TS_DATA[0] 17
NC_3
18 FE_DEMOD1_TS_DATA[1] 18
NC_4
19 FE_DEMOD1_TS_DATA[2] 19
NC_5
20 FE_DEMOD1_TS_DATA[3] 20
NC_6
21 FE_DEMOD1_TS_DATA[4] 21
NC_7
22 FE_DEMOD1_TS_DATA[5] 22
NC_8
23 FE_DEMOD1_TS_DATA[6] 23
NC_9
24 FE_DEMOD1_TS_DATA[7] 24
S_RESET_DEMOD
25 /TU_RESET1_TU 25
B3[+3.3V]
26 +3.3V_DEMOD_TU 26
SCL_DEMOD
27 I2C_SCL4_TU 27
B4[+1.1V]
28 D_Demod_Core 28
NC_10
29 LNB_TX
29
SDA_DEMOD
30 I2C_SDA4_TU 30

A1 B1
A1 B1
47

SHIELD

TU_GND_A

TU_GND_B
TU_GND_B
TU_GND_A
TU_EU/AJ/JA

TU_EU/AJ/JA
0 R6401

0 R6402

C6401
1000pF
630V
C6402
TU_TW/CO/BR
1000pF
630V
TU_TW/CO/BR/KR/US
Global flag

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS TUNER 2013.07.16
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 564
 /TU_RESET2_TU /TU_RESET2

FE_DEMOD1_TS_ERROR

1. should be guarded by ground

2. No via on both of them
3. Signal Width >= 12mils
close to Tuner Signal to Signal Width = 12mils
+3.3V_TUNER Ground Width >= 24mils

L6500
BLM18PG121SN1D close to TUNER
1 +3.3V_LNA_TU C6501
0.1uF R6507 1K
Global flag
2 RF_SWITCH_CTL_TU RF_SWITCH_CTL
C6504 R6503
0.1uF 10K

R6506 100
3 IF_AGC_TU IF_AGC
C6502 close to Tuner
0.1uF
16V

R6511 mA(MAX)
4 I2C_SCL6_TU I2C_SCL6
C6505 33
47pF
50V R6512 +3.3V_TUNER
5 I2C_SDA6_TU I2C_SDA6 +3.3V_TUNER 1608 perallel +3.3V_NORMAL
C6503 OPT 33 because of derating
47pF
50V
TU_HK TUNER_SIF TU_HK
OPT TU_HK L6502
R6513 0 R6516 R6517 BLM18PG121SN1D
200 200
6 IF_P IF_P
TU_CVBS C6526 C6529
should be guarded by ground,Match GND VIA 0.1uF 22uF
C6530
E 0.1uF
7 IF_N IF_N 16V 10V 16V
TU_HK 85C
B Q6502
8 TU_SIF_TU MMBT3906(NXP)
C

9 TU_CVBS_TU
+3.3V_TUNER T2 : Max 1.7A
L6501 else : Max 0.7A
10 BLM18PG121SN1D

C6510
0.1uF
11 +3.3V_TU TU_DEMOD_CORE Demod_Core

R6520-*1 R6519-*1 R6521-*1

+3.3V_TUNER IC6500

TU_1.1V
close to Tuner AP2132MP-2.5TRG1 [EP]
12 FE_DEMOD1_TS_ERROR
TU_1.2V

18K
FE_DEMOD1_TS_ERROR TU_DEMOD_CORE R6521
20K
14 FE_DEMOD1_TS_CLK FE_DEMOD1_TS_CLK C6516 1 8 1%
R2

TU_1.1V
0.1uF

THERMAL
PG GND

14K
R6519 TU_1.2V
15

9
FE_DEMOD1_TS_SYNC FE_DEMOD1_TS_SYNC 2 7 11K
1%
TU_DEMOD_CORE
EN ADJ R6520 R1
R6518 10K TU_1.2V
10K

TU_1.1V
FE_DEMOD1_TS_VAL FE_DEMOD1_TS_VAL 3 6 1%
16

2K
VIN VOUT

17 FE_DEMOD1_TS_DATA[0] +5V_NORMAL 4 2A 5
VCTRL NC
TU_DEMOD_CORE
FE_DEMOD1_TS_DATA[1] FE_DEMOD1_TS_DATA[0-7] EAN61387601
18 C6518
10uF
FE_DEMOD1_TS_DATA[0] 16V
19 FE_DEMOD1_TS_DATA[2] FE_DEMOD1_TS_DATA[1] TU_DEMOD_CORE
FE_DEMOD1_TS_DATA[2] C6515
1uF
FE_DEMOD1_TS_DATA[3]
20 FE_DEMOD1_TS_DATA[3]

Global F/E Option Name FE_DEMOD1_TS_DATA[4]

1. TU 21 FE_DEMOD1_TS_DATA[4]

2. Tuner Name = TDS’S’,TDS’Q’...

FE_DEMOD1_TS_DATA[5]
FE_DEMOD1_TS_DATA[6]
Vout=0.6*(1+R1/R2)
3. Country Name = T,T2,S2,KR,US,BR ... 22 FE_DEMOD1_TS_DATA[5] FE_DEMOD1_TS_DATA[7]

Example of Option name FE_DEMOD1_TS_DATA[6]

23
TU_Q_T2 = apply TDSQ type tuner and T2 country
TU_M/W = apply TDSM&TDSW Type Tuner
24 FE_DEMOD1_TS_DATA[7]
13’ Tuner Type for Global R6501 +3.3V_TUNER
100 /TU_RESET1
TDS’S’-G501D : T/C Half NIM Horizontal Type 25 /TU_RESET1_TU
C6507 L6503
TDS’Q’-G501D : T/C/S2 Combo Horizontal type 16V BLM18PG121SN1D
DELETE 1.8V POWER
TDS’Q’-G601D : T2/C/S2 Combo Horizontal Type 0.1uF
26 +3.3V_DEMOD_TU
TDS’Q’-G651D : T2/C/S2 Combo Vertical Type C6511
TDS’Q’-G705D : Singapore DVB-T2 (V1.3.1) 0.1uF
R6510 33
TDS’M’-C601D : China NIM with Isolater Type 27 I2C_SCL4_TU I2C_SCL4
L6505
TDS’W’-J551F : Japan Dual NIM BLM18PG121SN1D
Demod_Core OPT
C6513
TDS’W’-B651F : Brazil 2Tuner 28 D_Demod_Core
18pF
TU_DEMOD_CORE
TDS’W’-A651F : Taiwan 2Tuner C6506 50V
0.1uF OPT R6509 33
TDS’W’-K651F : Colombia DVB-T2 2Tuner 29 LNB_TX LNB_TX I2C_SDA4
TU_DEMOD_CORE C6512
18pF
50V
30 I2C_SDA4_TU

31 LNB_OUT LNB_OUT

34 FE_DEMOD2_TS_ERROR FE_DEMOD2_TS_ERROR

36 FE_DEMOD2_TS_SYNC FE_DEMOD2_TS_SYNC

37 FE_DEMOD2_TS_CLK FE_DEMOD2_TS_CLK

38

1.2V_MHL
39 FE_DEMOD2_TS_VAL FE_DEMOD2_TS_VAL
TU_NO_DEMOD_CORE
+3.3V_NORMAL
IC6515
FE_DEMOD2_TS_DATA FE_DEMOD2_TS_DATA AZ1117BH-1.2TRE1
40
R6502
100 /TU_RESET2 IN OUT
R6515

45 /TU_RESET2_TU C6509 GND/ADJ TU_NO_DEMOD_CORE

16V C6508
1

0.1uF 0.1uF
16V
C6514 C6519
10uF 0.1uF
10V 16V
TU_NO_DEMOD_CORE TU_NO_DEMOD_CORE

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS TUNER_CIRCUIT 2013.07.16
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 565
 LVDS LVDS_HD Pin Assign is same as
LVDS_51PIN
LN570B LVDS Cable
P7100
[51Pin LVDS OUTPUT Connector] [30Pin HD 60Hz] (EAD62296501)
FI-RE51S-HF-J-R1500 [41Pin LVDS OUTPUT Connector]
HD
NC 2D/3D_CTL P7102
1 R7100 33
T-CON 10031HR-30
NC LGD_2D/3D_CTRL Pin
2 Assign
LVDS_SEL
NC
3
GND 30 1
NC +3.3V_NORMAL
4 R7105 33 I2C_SDA1
NC 29 2
NC CP_BOX
5 R7106 33 I2C_SCL1
NC 28 3
AUO_65_MIRROR CP_BOX 0 R7109 R7101
6 LVDS_41PIN
3.3K NC 27 4
LVDS_SEL OPT P7101
7 LVDS_SEL_HIGH
FI-RE41S-HF-J-R1500 GND 26 5
NC R7107 33
8 PWM_DIM1 R7102
RD+ 25 6 TXA0N
NC LGD_T-Con_Scanning 10K
9 LVDS_SEL_LOW NC
R7110 33 RD- 24 7 TXA0P
L/DIM_ENABLE 1
10 AUO_L/D_EN NC 2D/3D_CTL
R7108 R7104 33 GND 23 8
GND 33 2
OPC_EN
11 NC AUO_2D/3D_CTRL
OPC_EN RCL+ 22 9 TXA1N
RA0N 3
12 TXA0N NC RCLK- 21 10 TXA1P
RA0P 4
13 TXA0P NC GND 20 11
RA1N 5
14 TXA1N NC RC+ 19 12 TXA2N
RA1P 6
15 TXA1P NC RC- 18 13 TXA2P
RA2N 7
16 TXA2N NC GND 17 14
RA2P 8
17 TXA2P GND RB+ 16 15 TXACLKN
GND 9
18 RC0N RB- 15 16 TXACLKP
RACLKN 10 TXC0N
19 TXACLKN RC0P GND 14 17
RACLKP 11 TXC0P
20 LVDS_SEL
TXACLKP RC1N RA+ 13 18
12 TXA3N
GND TXC1N +3.3V_NORMAL
21 RC1P RA- 12 19 TXA3P
RA3N 13 TXC1P
22 TXA3N RC2N GND 11 20
RA3P 14 TXC2N
23 OPT
TXA3P RC2P NC 10 21 R1109
RA4N 15 TXC2P 3.3K
24 TXA4N GND LVDS SEL 9 22
RA4P 16
PANEL_VCC
25 TXA4P RCCLKN OPT
GND 8 23
GND 17 TXCCLKN R1110
26 RCCLKP 10K
GND 7 24 HD
BIT_SEL BIT_SEL 18 TXCCLKP
27 L1101
GND GND 6 25 120OHM
RB0N 19
28 UBW2012-121F
TXB0N R7103 RC3N GND 5 26
RB0P 10K 20 TXC3N
29 TXB0P BIT_SEL_LOW RC3P VLCD 4 27
RB1N 21 TXC3P
30 TXB1N RC4N VLCD 3 28 HD
RB1P 22 TXC4N
31 TXB1P RC4P C1101
VLCD 2 29
RB2N 23 TXC4P 0.1uF
32 TXB2N GND 16V
VLCD 1 30
RB2P 24
33 TXB2P GND
GND 25 31
34 RD0N
RBCLKN 26 TXD0N
35 TXBCLKN RD0P
RBCLKP 27 TXD0P
36 TXBCLKP RD1N
GND 28 TXD1N
37 RD1P
RB3N 29 TXD1P
38 TXB3N RD2N
RB3P 30 TXD2N
39 TXB3P RD2P
RB4N 31 TXD2P
40 TXB4N GND
RB4P 32
41 TXB4P RDCLKN
GND 33 TXDCLKN
42 RDCLKP
GND 34 TXDCLKP
43 GND
GND 35
44 RD3N
PANEL_VCC 36
GND TXD3N
45 RD3P
GND 37 TXD3P
46 RD4N
L7100 38
NC TXD4N
47 BLM18SG121TN1D RD4P
VLCD LVDS_51PIN 39 TXD4P
48 GND
VLCD 40
49 GND
VLCD 41
50 C7100 C7101 C7102
VLCD 10uF 1000pF 0.1uF
51 16V 50V 50V 42
OPT OPT OPT
GND
52

GND

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LVDS_HIGH_MID 2013.07.16
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 571
Contents of LCD TV Standard Repair Process

No. Error symptom (High

( category)) Error symptom (Mid
( category)) Page Remarks

1 No video/Normal audio 1

2 No video/No audio 2

3 A. Video error Picture broken/ Freezing 3

4 Color error 4

Vertical/Horizontal bar
bar, residual image
image, light spot
spot,
5 5
external device color error
6 No power 6
B. Power error
7 Off when on,, off while viewing,
g, power
p auto on/off 7

8 No audio/Normal video 8
C. Audio error
9 Wrecked audio/discontinuation/noise 9

10 Remote control & Local switch checking 10

D. Function error
11 External device recognition error 11

12 E. Noise Circuit noise, mechanical noise 12

13 F. Exterior error Exterior defect 13

14 APPENDIX Power Off History

Fi t off all,
First ll Ch
Check
k whether
h th ththere iis SVC B
Bulletin
ll ti iin GCSC S
System
t ffor th
these model.
d l

1 / 97
Contents of LCD TV Standard Repair Process Detail Technical Manual
No. Error symptom Content Page Remarks
1 Check LCD back light with naked eye A1
2 LED driver B+ 24V measuring method A2
A. Video error_ No video/Normal audio
3 Check White Balance value A3
4 Power Board voltage measuring method A5
6 TUNER input signal strength checking method A6
A. Video error_ No video/Video lag/stop
7 LCD-TV Version checking method A7
9 LCD TV connection
ti didiagram A8
10 Tuner Checking Part A9
A. Video error_Color error A10 A10 : 32/37/42/47/55
11 Check Link Cable (LVDS) reconnection condition
A11 A11 : 32 AUO
12 Adjustment Test pattern - ADJ Key A12
13 LCD TV connection diagram A8
A. Video error_Vertical/Horizontal bar, A10 A10 : 32/37/42/47/55
14 Check Link Cable ((LVDS)) reconnection condition
residual image
image, light spot A11 A11 : 32 AUO
15 Adjustment Test pattern - ADJ Key A12
16 Exchange T-Con Board (1) A-1/5

17 Exchange T
T-Con
Con Board (2) A 2/5
A-2/5
<Appendix>
Defected Type caused by T-Con/ Inverter/ 55” : driver board
18 Exchange LED driver Board (PSU) A-3/5
Module Other : PSU

19 g Module itself ((1))

Exchange A-4/5
20 Exchange Module itself (2) A-5/5

2 / 97
Standard Repair Process
Established
Error A. Video error d t
date 2014 1 .2
2014. 2
LCD TV symptom
No video/ Normal audio Revised date 1/13

First of all, Check whether all of cables between board is inserted properly or not.
((Main B/D↔ Power B/D,, LVDS Cable,Speaker
, p Cable,IR
, B/D Cable,, ETC…))

☞A1 ☞A4
No video Normal Y Check Back Light Y Check Power Board Normal Y Replace T-con Board
Normal audio On or module
audio On with naked eye 12V,3.5V etc. voltage
And Adjust
j VCOM
N N N ☞A28
Move to No Check Power Board 24V output Repair Power Board
☞A2
video/No audio or parts

Replace Inverter
Normal Y
or module
voltage

End
N
Repair Power
Board or parts

※Precaution ☞A7 & A3

Always check & record S/W Version and White
Replace Main Board Re-enter White Balance value
Balance value before replacing the Main Board

3 / 97
Standard Repair Process
Established
Error A. Video error d t
date 2014 1 .2
2014. 2
LCD TV symptom
No video/ No audio Revised date 2/13

☞A4
Check various voltages
C Check and
Normal Y
No Video/ of Power Board replace
No audio ( 3.5V,12V or 24V…) voltage?
MAIN B/D

N End

Replace Power
Board and repair
parts

4 / 97
Standard Repair Process
Established
Error A. Video error d t
date 2014 1 .2
2014. 2
LCD TV symptom
Picture broken/ Freezing Revised date 3/13

. By using Digital signal level meter

☞ A6
. By using Diagnostics menu on OSD
Check RF Signal level ( Menu → Settings → Support → Signal Test )
- Signal strength (Normal : over 50%)
- Signal Quality (Normal: over 50%)

Y Check whether other equipments have problem or not.

Normal
(By connecting RF Cable at other equipment)
Signal?
→ DVD Player ,Set-Top-Box, Different maker TV etc`

N
☞ A7
Check RF Cable
Normal Y Check SVC N
Connection
1. Reconnection Picture? S/W Version Bulletin?
2. Install Booster
Y
N
S/W Upgrade Check
N Contact with signal distributor
Normal Tuner soldering
Picture? or broadcaster (Cable or Air)
Normal N
Y Picture? Replace
Main B/D
Y
Close
Close

5 / 97
Standard Repair Process
Established
Error A. Video error d t
date 2014 1 .2
2014. 2
LCD TV symptom
Color error Revised date 4/13

☞A8
☞ A10/ A11
※ Check and
Check color by input
replace Link Y
-External Input Y Y
Color Cable Color Color
-COMPONENT Replace Main B/D Replace module
error? (LVDS) and error? error?
-AV
contact
-HDMI/DVI N N N
condition

Check error color End

input mode

☞A12 Check
External Input/ External device Y
external
Check Test pattern Component/ AV /Cable Replace Main B/D
device and
error normal
cable
N

Request repair
for external
device/cable

Check external External device Y

HDMI/DVI
device and /Cable Replace Main B/D
error
cable normal

6 / 97
Standard Repair Process

Error
A. Video error Established
2014 1 .2
2014. 2
d t
date
LCD TV symptom Vertical / Horizontal bar, residual image,
light spot, external device color error Revised date 5/13

Vertical/Horizontal bar, residual image, light spot Replace

Module
☞A8
☞ A10/ A11 N
Check color condition by input Check external ☞ A28
Y Check and
-External Input Screen Y device Screen N Screen
-Component Normal? replace Link Replace Main B/D
normal? connection normal? normal?
-AV Cable (adjust VCOM)
condition
-HDMI/DVI
HDMI/DVI For LGD panel
N N Y
Y
Replace Main B/D
Replace Request repair End End
for external
☞A12 module
device
Check Test pattern
For other panel

External device screen error-Color error

Check screen
condition by input
Check External
Check S/W Version N -External Input Connect other external device
version Input N
-Component and cable Screen
error R l
Replace
-AV (Check normal operation of normal?
-HDMI/DVI External Input, Component, AV Main B/D
Y Component/AV and HDMI/DVI by connecting Jig,
error pattern Generator ,Set-top Box Y
S/W Upgrade
etc.
Request repair for
external device
HDMI/
DVI Connect other external device Y
Normal N and cable Screen N
screen? Replace
(Check normal operation of
External Input, Component, AV
normal? Main B/D
Y and HDMI/DVI by connecting
Jig, pattern Generator ,Set-top
End B etc.
Box t

7 / 97
Standard Repair Process
Established
Error B. Power error d t
date 2014 1 .2
2014. 2
LCD TV symptom
No power Revised date 6/13

☞A17 ☞A19
Y DC Power on N Y Replace
Check Power LED Normal Check Power
by pressing Power Key OK? Power
Power LED On? operation? On ‘”High”
On Remote control B/D
. Stand-By: Red or Logo Light ON N
. Operating : off Y
Check Power cord Replace Main B/D
was inserted properly
☞A4
N Measure voltage of each output of Power B/D
Normal?

Y
Y Y
Normal
※ voltage?
Replace Main B/D
Close Normal
Ch k ST
Check ST-BY
BY 3
3.5V
5V
Y
voltage? N
☞A18 Replace Power B/D
N

Replace Power
B/D

8 / 97
Standard Repair Process
Established
Error B. Power error d t
date 2014 1 .2
2014. 2
LCD TV symptom
Off when on, off while viewing, power auto on/off Revised date 7/13

Check outlet

☞A22
N CPU Y
Check A/C cord Error? Check Power Off Normal? End
Replace Main B/D
Mode Abnormal

N
Check for all 3- phase
power out
p Y Abnormal Replace Power B/D
1

Fix A/C cord & Outlet ☞A19

and check each 3 (If Power Off mode is
phase out not displayed) Normal Y
Replace Main B/D
Check Power B/D g
voltage?
voltage
※ Caution
N
Check and fix exterior
Replace Power B/D
of Power B/D Part

* Please refer to the all cases which can be displayed on power off mode.
Click the below Hyper_link

9 / 97
Standard Repair Process
Established
Error C. Audio error d t
date 2014 1 .2
2014. 2
LCD TV symptom
No audio/ Normal video Revised date 8/13

☞A24 ☞A25
Check user Y Check audio B+ 24V Y
No audio TV Normal
menu > of Power Board
Screen normal Speaker? voltage
Sound Out
N N

Change the TV Speaker Replace Power Board and repair parts

Check Speaker N
Disconnection Replace MAIN Board End
disconnection

Replace Speaker / Cable

10 / 97
Standard Repair Process
Established
Error C. Audio error d t
date 2014 1 2
2014.1.2
LCD TV symptom
Wrecked audio/ discontinuation/noise Revised date 9/13

→ abnormal audio/discontinuation/noise is same after “Check input signal” compared to No audio

☞A25
Wrecked audio/
Check and replace
Discontinuation/ Check audio
speaker and
Noise for B+ Voltage (24V)
connector
Check input all audio
signal Y Y
Signal
-RF
normal? Wrecked audio/
-External Input Normal
signal Discontinuation/
N Replace Main B/D voltage?
Noise only
for D-TV
N
W k d audio/
Wrecked di /
Discontinuation/
Replace Power B/D
Noise only
for Analog
(When RF signal is not
received)
R
Requestt repair
i tto external
t l Wrecked audio/ R l
Replace Main
M i B/D End
cable/ANT provider Discontinuation/
Noise only
(In case of External for External Input
N
Input signal error) Connect and check Normal
Check and fix other external device audio?
external device
Y

Check and fix external device

11 / 97
Standard Repair Process

Error
D. General Function Problem Established
2014 1 2
2014.1.2
d t
date
LCD TV symptom
Remote control & Local switch checking Revised date 10/13

1. Remote control(R/C) operating error Replace

Main B/D
☞A27 ☞A27 ☞A27
Check & Repair N Y Y
Check R/C itself Normal Y Normal Check B+ 3.5V Normal Check IR Normal
operating? Cable connection operating? Voltage? Signal?
Operation On Main B/D Output signal
Connector solder
N
Y N N
☞A4
Check R/C Operating Check & Replace Close Check 3.5v on Power B/D Repair/Replace
When turn off light Baterry of R/C Replace Power B/D or IR B/D
in room Replace Main B/D
(Power B/D don’t have problem)
If R/C operate, Normal
operating? Close
Explain the customer
cause is interference
from light in room. N

Replace
p R/C

12 / 97
Standard Repair Process
Established
Error D. Function error d t
date 2014 1 2
2014.1.2
LCD TV symptom
External device recognition error Revised date 11/13

Y Check technical
Check External Input and
Signal
g information Technical N
inp t
input C
Component t Replace Main B/D
input? - Fix information information?
Recognition error
signal
- S/W Version
N Y

HDMI/
Check and fix DVI, Optical
Fix in Replace Main B/D
external device/cable Recognition error
accordance
with technical
information

13 / 97
Standard Repair Process
Established
Error E. Noise d t
date 2014 1 2
2014.1.2
LCD TV symptom
Circuit noise, mechanical noise Revised date 12/13

Replace PSU(with LED driver)

Identify Circuit Check location
noise type of noise OR
noise
Replace LED driver

Mechanical Check location of

noise noise

※ When the nose is severe, replace the module

※ Mechanical noise is a natural (For models with fix information, upgrade the S/W or
phenomenon, and apply the 1st level provide the description)
description. When the customer does not OR
agree, apply the process by stage. ※ If there is a “Tak Tak” noise from the cabinet,
※ Describe the basis of the description in refer to the KMS fix information and then proceed
“Part related to nose” in the Owner’s Manual. as shown in the solution manual
(For models without any fix information, provide
the description)

14 / 97
Standard Repair Process
Established
Error F. Exterior defect d t
date 2014 1 2
2014.1.2
LCD TV symptom
Exterior defect Revised date 13/13

Zoom part with Module

Replace module Adjust VCOM
exterior damage damage
☞A28

Cabinet
Replace cabinet
damage

Remote
controller Replace remote controller
damage

Stand
Replace stand
dent

15 / 97
Contents of LCD TV Standard Repair Process Detail Technical Manual
Continued from p
previous page
p g

No. Error symptom Content Page Remarks

21 Check front display LED A17

22 Check power input Voltage & ST-BY 3.5V

3 5V A18

23 B. Power error_No power Checking method when power is ON A19

24 POWER BOARD voltage measuring method A5

25
B. Power error_Off when on, off while
26 POWER OFF MODE checking method A22
viewing
B. Power error_Off when on, off while
27 POWER BOARD PIN voltage checking method A19
viewing
Checking method in menu when there is no
28 A24
audio
C. Audio error_No audio/Normal video
Voltage and speaker checking method when
29 A25
there is no audio
C. Audio error_Wrecked Voltage and speaker checking method in case of
30 A25
audio/discontinuation audio error
D. Function error_ No response in remote
31 Remote controller operation checking method A27
controller key error
controller,
32 D. VCOM Adjustment Sequence of the Vcom adjustment A28

16 / 97
Standard Repair Process Detail Technical Manual
Error Established
t
symptom A Video error
A. error_No
No video/Normal audio date
2014 1 2
2014.1.2
LCD TV Revised
Content Check White Balance value A3
date

<ALL MODELS>

Entry
Entry method
method

1. Press
1. Press the
the ADJ
ADJ button
button on
on the
the remote
remote controller
controller for
for adjustment.
adjustment.

2. Enter
2. Enter into
into White
White Balance
Balance of
of item
item 7.
6.

3.
3
3 After
3. After recording
recording the
the R
R,
R, G
R G,
G, B
G B (GAIN
(GAIN,
(GAIN, Cut)
(GAIN Cut) value
value of
of Color
Color Temp
Temp (Cool/Medium/Warm)
(Cool/Medium/Warm),
(Cool/Medium/Warm), re-
(Cool/Medium/Warm) re
re-
enter the value after replacing the MAIN BOARD.
enter the value after replacing the MAIN BOARD.

17 / 97
Standard Repair Process Detail Technical Manual
Error Established
t
symptom A Video error_No
A. error No video/ Audio date
2014 1 2
2014.1.2
LCD TV Revised
Content Power Board voltage measuring method A5
date

Check the DC 24V, 12V, 3.5V.

18 or 24 Pin (Power Board ↔ Main Board) - 공통

SMAW200-H18/24S5 (YEONHO)
1 PWR ON/OFF 2 INV ON
3 3.5V 4 PDIM #1
5 3.5V 6 3.5V
7 GND 8 PDIM #2
9 24V 10 24V
11 GND 12 GND
13 12V 14 12V
15 12V 16 24V or N.C
17 GND 18 GND
19 GND 20 GND
21 GND 22 L/DIMO_VS
23 L/DIMO_MOSI 24 L/DIMO-SCLK

The Wafer,18Pin and 24Pin, is used by operating LocalDimming or not LocalDimming

- 24Pin wafer is applied operating L/D at power and main B/D

- 18Pin wafer is applied not operating L/D at power and main B/D

18 / 97
Standard Repair Process Detail Technical Manual
Error Established
t
symptom A Video error
A. error_Video
Video error
error, video lag/stop date
2014 1 2
2014.1.2
LCD TV Revised
Content TUNER input signal strength checking method A6
date

<ALL MODELS>

MENU -Æ Settings Æ support -Æ signal test

-Æ select channel

When the signal is strong, use the

attenuator (-10dB, -15dB, -20dB etc.)

19 / 97
Standard Repair Process Detail Technical Manual
Error Established
symptom
t A Video error
A. error_Video
Video error
error, video lag/stop date
2014 1 . 6
2014.
LCD TV Revised
Content LCD-TV Version checking method A7
date

<ALL MODELS> 1. Checking method for remote controller for adjustment

Version

Press the IN-START with the remote

controller for adjustment

20 / 97
Standard Repair Process Detail Technical Manual
Error A. Video error _Vertical/Horizontal bar, residual Established
symptom
t 2014 1 2
2014.1.2
LCD TV image, light spot date
Revised
Content LCD TV connection diagram (1) date A8

<ALL MODELS>

As the part connecting to the external input,

check
h k th
the screen condition
diti by
b signal
i l

21 / 97
Standard Repair Process Detail Technical Manual
Error Established
t
symptom
A. Video error_Video
error Video error, video lag/stop 2014 1 .6
2014. 6
LCD TV date
TUNER checking part Revised
Content A9
date

<ALL MODELS>

Checking method:
1. Check the signal
g strength
g or check whether the screen is normal when the external device is connected.
2. After measuring each voltage from power supply, finally replace the MAIN BOARD.( with Main to Power Cable, Speaker Cable and LVDS or EPI Cable)

22 / 97
Standard Repair Process Detail Technical Manual
Error Established
t
symptom
error Color error
A. Video error_Color 2014 1 2
2014.1.2
LCD TV date
Adjustment Test pattern - ADJ Key Revised
Content A12
date

You can view 6 types of patterns using the ADJ Key

Checking item : 1
1. Defective pixel 22. Residual image 33. MODULE error (ADD
(ADD-BAR,SCAN BAR..))
BAR SCAN BAR
4.Video error (Classification of MODULE or Main-B/D!)

23 / 97
Standard Repair Process Detail Technical Manual
Error Established
t
symptom B Power error _No
B. No power date
2014 1 2
2014.1.2
LCD TV Revised
Content Check front display LED A17
date

Front LED control :

Menu Æ Option Æ LG Logo Light
Æ Brightness and Duration

ST-BY condition: Red or Logo

g Light
g ON
Power ON condition: OFF or User Settings

24 / 97
Standard Repair Process Detail Technical Manual
Error Established
t
symptom B Power error _No
B. No power date
2014 1 .6
2014. 6
LCD TV Revised
Content Check power input voltage and ST-BY 3.5V A18
date

For 13’ models, there is no voltage out for st-by purpose.

When st-by
st by, only 3
3.5V
5V is normally on
on.
18 or 24 Pin (Power Board ↔ Main Board) - 공통

FREE LGP-14PL1-IT
Edge LED
1 PWR ON/OFF 2 INV ON
3 3.5V 4 PDIM #1
5 3.5V 6 GND
Edge LED
7 GND 8 PDIM #2
9 24V 10 24V
11 GND 12 GND
13 12V 14 12V
15 12V 16 24V or N.C
17 GND 18 GND
19 GND 20 GND
21 GND 22 L/DIMO_VS
23 L/DIMO_MOSI 24 L/DIMO_SCLK

The Wafer,18Pin and 24Pin, is used by operating LocalDimming or not LocalDimming

- 24Pin wafer is applied operating L/D at power and main B/D

- 18Pin wafer is applied not operating L/D at power and main B/D

25 / 97
Standard Repair Process Detail Technical Manual
Error Established
t
symptom B Power error _No
B. No power date
2014 1 2
2014.1.2
LCD TV Revised
Content Checking method when power is ON A19
date

Check “power on” pin is high

18 or 24 Pin (Power Board ↔ Main Board) - 공통

FREE LGP-14PL1-IT
Edge LED
1 PWR ON/OFF 2 INV ON
3 3.5V 4 PDIM #1
5 3.5V 6 3.5V
Edge LED
7 GND 8 PDIM #2
9 24V 10 24V
11 GND 12 GND
13 12V 14 12V
15 12V 16 24V or N.C
17 GND 18 GND
19 GND 20 GND
21 GND 22 L/DIMO_VS
23 L/DIMO_MOSI 24 L/DIMO_SCLK

The Wafer,18Pin and 24Pin, is used by operating LocalDimming or not LocalDimming

- 24Pin wafer is applied operating L/D at power and main B/D

- 18Pin wafer is applied not operating L/D at power and main B/D

26 / 97
Standard Repair Process Detail Technical Manual
Error Established
t
symptom B. Power error _Off
Off when on,
on off whiling viewing
date
2014 1 6
2014.1.6
LCD TV Revised
Content POWER OFF MODE checking method A22
date

<ALL MODELS>

Entry method

1. Press the IN-START button of the remote controller

for adjustment

2. Check the entry into adjustment item 3

27 / 97
Standard Repair Process Detail Technical Manual
Error Established
t
symptom C. Audio error
error_No
No audio/Normal video 2014 1 2
2014.1.2
LCD TV date
Revised
Content Checking method in menu when there is no audio A24
date

<ALL MODELS>

Checking method
1. Press the MENU button on the remote controller
2. Select the SOUND function of the Menu
3. Select TV Speaker from Others

28 / 97
Standard Repair Process Detail Technical Manual
Error Established
t
symptom C Audio error
C. error_No
No audio/Normal video date
2014 1 .6
2014. 6
LCD TV Revised
Content Voltage and speaker checking method A25
when there is no audio date

<ALL MODELS>
18 or 24 Pin (Power Board ↔ Main Board) - 공
①
통
② FREE LGP-14PL1-IT
1 PWR ON/OFF 2 INV ON
3 3.5V 4 PDIM #1
5 3.5V 6 3.5V
7 GND 8 PDIM #2
② 9 24V 10 24V
11 GND 12 GND
13 12V 14 12V
15 12V 16 24V or N.C
17 GND 18 GND
19 GND 20 GND ③
21 GND 22 L/DIMO_VS
23 L/DIMO_MOSI 24 L/DIMO_SCLK

The Wafer,18Pin and 24Pin, is used by operating LocalDimming or not

LocalDimming
Checking order when there is no audio
- 24Pin
24Pi wafer
f isi applied
li d operating
i L/D/D at power and
d main
i B/D
① Check the contact condition of or 24V connector of Main Board - 18Pin wafer is applied not operating L/D at power and main B/D

② Measure the 24V input voltage supplied from Power Board

(If there is no input voltage, remove and check the connector)
③ Connect
C the
h tester RX1 to the
h speakerk terminal
i l and
d if you h
hear the
h “Chik Chik” sound
d when
h you touch
h the
h GND
and output terminal, the speaker is normal.

29 / 97
Standard Repair Process Detail Technical Manual
Error D. Function error_ No response in remote controller, Established
t
symptom k error
key 2014 1 .6
2014. 6
LCD TV date
Revised
Content Remote controller operation checking method A27
date

<ALL MODELS>
P4102
1 GND
2 KEY1
3 KEY2
③ 4 +3.5V_ST
5 GND
6 LOGO/LED_R
④ 7 IR
8 GND
9 EYE SCL
EYE_SCL
10 EYE_SDA

②
①

Checking
g order
1, 2. Check IR cable condition between IR & Main board.
3. Check the st-by 3.5V on the terminal 6.
4. When checking the Pre-Amp when the power is in ON condition, it is normal when the Analog
Tester needle moves slowly, and defective when it does not move at all.

30 / 97
Standard Repair Process Detail Technical Manual
Error Established
t
symptom D VCOM Adjustment
D. date
2014 1 2
2014.1.2
LCD TV Revised
Content Sequence of the Vcom adjustment A28
date

1. Case
■ LCD module
d l change
h
■ T-Con board change

2. Equipment
■ Service Remote controller

3. Adjust sequence
■ Press the ‘adj’ key
■ select V-COM
■ AsA pushing
hi th
the right
i ht or th
the lleft
ft b
button
tt on th
the remote
t controller,
t ll And A d fifind
d th
the V
V-COM
COM value
l Which
Whi h iis no or
minimized the Flicker.
(If there is no flicker at default value, Press the exit key and finish the VCOM adjustment.)
■ Push the OK key to store the value. Then the message “Saving OK” is pop.
■ Press the exit keyy to finish V-COM adjustment.
j

31 / 97
Appendix : Power OFF History

Status Power off List Explanation

POWER_OFF_BY_REMOTE KEY POWER_OFF_BY_REMOTE CONTROL

POWER_OFF_BY_OFF_TIMER POWER_OFF_BY_OFF TIMER

POWER_OFF_BY_SLEEP_TIMER POWER_OFF_BY_SLEEP TIMER

POWER_OFF_BY_TS_END POWER_OFF_BY_REMOTE or LOCAL KEY While recording

POWER_OFF_BY_INSTOP_KEY POWER_OFF_BY_INSTOP KEY

POWER_OFF_BY_AUTO_OFF POWER_OFF_BY_AUTO OFF

POWER_OFF_BY_ON_TIMER POWER_OFF_BY_ON TIMER

POWER_OFF_BY_RS232C POWER_OFF_BY_RS232C
Normal
POWER_OFF_BY_RESREC POWER_OFF_BY_Reservated Record

POWER_OFF_BY_RECEND POWER_OFF_BY_End of Recording

POWER_OFF_BY_SWDOWN POWER_OFF_BY_S/W Download

POWER_OFF_BY_LOCAL_KEY POWER_OFF_BY_LOCAL KEY

POWER_OFF_BY_OTA POWER_OFF_BY_End of OTA

POWER_OFF_BY_SIGNAL_DETECT POWER_OFF_BY_Another MICOM (Only OLED)

POWER_OFF_BY_RESET POWER_OFF_BY_Factory Reset

POWER_OFF_BY_UNKNOWN POWER_OFF_BY_unknown status except listed case

POWER_OFF_BY_ABN POWER_OFF_BY_abnormal Panel status

POWER_OFF_BY_KEY_TIMEOUT POWER_OFF_BY_abnormal Power Off Key At Warm/Hot status

POWER_OFF_BY_ACDET POWER_OFF_BY_AC OFF

Abnormal POWER_OFF_BY_5VMNT POWER_OFF_BY_AC DETECT

POWER_OFF_BY_NO_POLLING POWER_OFF_BY_MCU Abnormal for 15 sec.

POWER_OFF_BY_1SEC_POWER_OFF POWER_OFF_BY_MCU Abnormal status with Power Off Key

POWER_OFF_BY_20VMNT POWER_OFF_BY_abnormal Panel status (Only OLED)

32 / 97
Appendix : Exchange T-Con Board (1)

Solder defect, CNT Broken Solder defect, CNT Broken Solder defect, CNT Broken

Solder defect, CNT Broken T-Con

T-Con Defect,
Defect,
Solder
T-Con CNT
CNT
defect,CNT
Defect, CNTBroken
Broken
Broken
Broken Abnormal Power Section

Solder defect, Short/Crack Abnormal Power Section Solder defect, Short/Crack

33 / 97
Appendix : Exchange T-Con Board (2)

Abnormal Power Section Abnormal Power Section Solder defect, Short/Crack

Solder defect,
defect Short/Crack Fuse Open
Open, Abnormal power section Abnormal Display
p y

GRADATION Noise GRADATION

34 / 97
Appendix : Exchange PSU(LED driver)

No Light Dim Light

Dim Light Dim Light

No picture/Sound Ok

35 / 97
Appendix : Exchange the Module (1)

Panel Mura, Light leakage Panel Mura, Light leakage Press damage

Crosstalk Press damage Crosstalk

Un-repairable Cases
In this case please exchange the module.

Press damage

36 / 97
Appendix : Exchange the Module (2)

Vertical Block Vertical Line Vertical Block

Source TAB IC Defect Source TAB IC Defect Source TAB IC Defect

Horizontal Block Horizontal Block Horizontal line

Gate TAB IC Defect Gate TAB IC Defect
Gate TAB IC Defect Gate TAB IC Defect Gate TAB IC Defect

Un-repairable Cases
In this case please exchange the module.

Horizontal Block
Gate TAB IC Defect
Gate TAB IC Defect

37 / 97
 Datasheet

LED Drivers for LCD Backlights

1ch Boost up type

White LED Driver for large LCD
BD9486F
1.1 General Description Key Specifications
BD9486F is a high efficiency driver for white LEDs and is  Operating power supply voltage range:9.0V to 18.0V
designed for large LCDs. BD9486F has a boost DCDC  Oscillator frequency of DCDC: 150kHz (RT=100kΩ)
converter that employs an array of LEDs as the light  Operating Current: 2.6mA(Typ.)
source.  Operating temperature range: -40°C to +85°C
BD9486F has some protect functions against fault
conditions, such as over-voltage protection (OVP), over 1.2 Package(s) W(Typ) x D(Typ) x H(Max)
current limit protection of DCDC (OCP), LED OCP SOP16 10.00mm x 6.20mm x 1.71mm
protection, and Over boost protection (FBMAX). Pin pitch 1.27mm
Therefore it is available for the fail-safe design over a
wide range output voltage.

Features
 DCDC converter with current mode
 VOUT discharge function at shutdown
 LED protection circuit (Over boost protection, LED
OCP protection)
 Over-voltage protection (OVP) for the output voltage
Vout
 Adjustable soft start
 Adjustable oscillation frequency of DCDC
 Wide range of analog dimming 0.2V to 3.0V Figure 1. SOP16
 UVLO detection for the input voltage of the power
stage

Applications
 TV, Computer Display, LCD Backlighting

1.3 Typical Application Circuit(s)

Figure 2. Typical Application Circuit

○Product structure：Silicon monolithic integrated circuit ○This product has not designed protection against radioactive rays
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●1.4 Absolute Maximum Ratings (Ta=25°C)

Parameter Symbol Ratings Unit
Power Supply Voltage Vccmax 20 V
STB, OVP, UVLO, PWM, ADIM STB, OVP, UVLO,
20 V
Terminal Voltage PWM, ADIM
SS, RT, ISENSE, FB, CS, CP, SS, RT, ISENSE, FB, CS,
7 V
REG50 Terminal Voltage CP, REG50
DIMOUT, GATE Terminal
DIMOUT, GATE VCC V
Voltage
Power Dissipation Pd 625 (*1) mW
Operating Temperature Range Topr -40 to +85 °C
Junction Temperature Tjmax 150 °C
Storage Temperature Range Tstg -55 to +150 °C
*1 In the case of mounting 1 layer glass epoxy base-plate of 70mm×70mm×1.6mm,
derate by 5.0mW/°C when operating above Ta=25°C.

●1.5 Operating Ratings

Parameter Symbol Range Unit
Power Supply Voltage VCC 9.0 to 18.0 V
DC/DC Oscillation Frequency fsw 50 to 800 kHz
Effective Range of ADIM Signal VADIM 0.2 to 3.0 V
PWM Input Frequency FPWM 90 to 2000 Hz

●1.6 Pin Configuration ●1.7 Physical Dimension and Marking Diagram

12v

2.98V
BD9486F

0.2V-2.60V Lot No.

Figure 3. Pin Configuration Figure4. Physical Dimension and Marking Diagram of SOP16

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●1.8 Electrical Characteristics (Unless otherwise specified, Ta=25°C，VCC=12V)

Limit
Parameter Symbol Unit Condition
Min. Typ. Max.
【Total Current Consumption】
VSTB=3.0V, PWM=3.0V,
Circuit Current Icc － 2.6 5.2 mA
GATE=L,IREG50=0mA
Circuit Current (standby) IST － 40 80 μA VSTB=0V
【UVLO Block】
Operation Voltage（VCC） VUVLO_VCC 6.5 7.5 8.5 V VCC=SWEEP UP
Hysteresis Voltage（VCC） VUHYS_VCC 150 300 600 mV VCC=SWEEP DOWN
UVLO Release Voltage VUVLO 2.88 3.00 3.12 V VUVLO=SWEEP UP
UVLO Hysteresis Voltage VUHYS 250 300 350 mV VUVLO=SWEEP DOWN
UVLO Pin Leak Current UVLO_LK -2 0 2 μA VUVLO=4.0V
【DC/DC Block】
ISENSE Threshold Voltage 1 VLED1 0.225 0.233 0.242 V VADIM=0.7V
ISENSE Threshold Voltage 2 VLED2 0.656 0.667 0.677 V VADIM=2.0V
ISENSE Threshold Voltage 3 VLED3 0.988 1.000 1.012 V VADIM=3.0V
VADIM=3.3V
ISENSE Clamp Voltage VLED4 0.989 1.015 1.040 V
(at masked analog dimming)
Oscillation Frequency FCT 142.5 150 157.5 KHz RT=100kΩ
VRT
RT Short Protection Range RT_DET -0.3 - ×90%
V RT=SWEEP DOWN
RT Terminal Voltage VRT 1.6 2.0 2.4 V RT=100kΩ
RT Pin ON Resistance at OFF RRT_L - 2.0 4.0 kΩ At latch off
GATE Pin MAX DUTY Output MAX_DUTY 90 95 99 % RT=100kΩ
GATE Pin ON Resistance
RONSO 2.5 5.0 10.0 Ω
(as source)
GATE Pin ON Resistance
RONSI 2.0 4.0 8.0 Ω
(as sink)
SS Pin Source Current ISSSO -3.75 -3.0 -2.25 μA VSS=2.0V
SS Pin ON Resistance at OFF RSS_L - 3.0 5.0 kΩ
Soft Start Ended Voltage VSS_END 3.52 3.70 3.88 V SS=SWEEP UP
VISENSE=0.2V, VADIM=3.0V,
FB Source Current IFBSO -115 -100 -85 μA
VFB=1.0V
VISENSE=2.0V, VADIM=3.0V,
FB Sink Current IFBSI 85 100 115 μA
VFB=1.0V
OCP Detect Voltage VCS 360 400 440 mV CS=SWEEP UP
OCP Latch Off Detect Voltage VCS 0.85 1.00 1.15 V CS=SWEEP UP
【DC/DC Protection Block】
OVP Detect Voltage VOVP 2.88 3.00 3.12 V VOVP SWEEP UP
OVP Detect Hysteresis VOVP_HYS 150 200 250 mV VOVP SWEEP DOWN
OVP Pin Leak Current OVP_LK -2 0 2 μA VOVP=4.0V, VSTB=3.0V

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●1.8 Electrical Characteristics (Unless otherwise specified, Ta=25°C，VCC=12V)

Limit
Parameter Symbol Unit Condition
Min. Typ. Max.
【LED Protection Block】
LED OCP Detect Voltage VLEDOCP 2.88 3.0 3.12 V VISENSE=SWEEP UP
Over Boost Detection Voltage VFBH 3.84 4.00 4.16 V VFB=SWEEP UP
【Dimming Block】
ADIM Pin Leak Current ILADIM -2 0 2 μA VADIM=2.0V
ISENSE Pin Leak Current IL_ISENSE -2 0 2 μA VISENSE=4.0V
DIMOUT Source ON
RONSO 5.0 10 20 Ω
Resistance
DIMOUT Sink ON Resistance RONSI 4.0 8.0 16 Ω
【REG50 Block】
REG50 Output Voltage 1 REG50_1 4.95 5.00 5.05 V IO=0mA
REG50 Output Voltage 2 REG50_2 4.925 5.00 5.075 V IO=-5mA
REG50 Available Current | IREG50 | 5 - - mA
VREG50=SWEEP DOWN
REG50_UVLO Detect Voltage REG50_TH 2.0 2.3 2.6 V
VSTB=0V
STB=ON->OFF, REG50=4.0V,
REG50 Discharge Current REG50_DIS 3.0 5.0 7.0 μA
PWM=L
【STB Block】
STB Pin HIGH Voltage STBH 2.0 - 18 V
STB Pin LOW Voltage STBL -0.3 - 0.8 V
STB Pull Down Resistance RSTB 600 1000 1400 kΩ VSTB=3.0V
【PWM Block】
PWM Pin HIGH Voltage PWM_H 1.5 - 18 V
PWM Pin LOW Voltage PWM_L -0.3 - 0.8 V
PWM Pin Pull Down Resistance RPWM 600 1000 1400 kΩ VPWM=3.0V
【FAIL Block 】
CP Detect Voltage VCP 2.85 3.0 3.15 V VCP=SWEEP UP
CP Charge Current ICP 2.7 3.0 3.3 μA

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●2.1 Pin Function

Pin
No. IN/OUT Function Rating [V]
Name
5.0V output voltage pin and shutdown
1 REG50 Out -0.3 to 7
timer pin
2 STB In IC ON/OFF pin -0.3 to 20
3 OVP In Over voltage protection detection pin -0.3 to 20
4 UVLO In Under voltage lock out detection pin -0.3 to 20
5 SS Out Slow start setting pin -0.3 to 7
6 PWM In External PWM dimming signal input pin -0.3 to 20
7 CP Out Charge timer for abnormal state -0.3 to 7
8 ADIM In ADIM signal input pin -0.3 to 20
9 RT Out DC/DC switching frequency setting pin -0.3 to 7
10 FB Out Error amplifier output pin -0.3 to 7
11 ISENSE In LED current detection input pin -0.3 to 7
12 GND - -
13 DIMOUT Out Dimming signal output for NMOS -0.3 to VCC
14 GATE Out DC/DC switching output pin -0.3 to VCC
DC/DC output current detect pin,
15 CS In -0.3 to 7
OCP input pin
16 VCC In Power supply pin -0.3 to 20

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BD9486F Datasheet

●2.2 Pin ESD Type

OVP UVLO SS

UVLO
50k

5V

RT REG50 CP

REG50

ADIM FB DIMOUT / VCC

VCC

ADIM
20k

DIMOUT
5V

100k
VCC GND

GATE / VCC / CS PWM / STB ISENSE

VCC

PWM
100k

GATE
5V
1M

STB
100k 100k
VCC GND

5V
CS 1M

Figure 5. Pin ESD Type

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●2.3 Block Diagram

Figure 6. Block Diagram

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●2.4 Typical Performance Curves (Reference data)

Figure 7. Circuit current (active) Figure 8. Fsw vs RT characteristic

Figure 9. FB sink current vs FB voltage characteristic Figure 10. FB source current vs FB voltage characteristic

Figure 11. ISENSE feedback voltage vs ADIM voltage characteristic

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●2.5 Pin Description

○Pin 1: REG50
This is the 5.0V(typ.) output pin. Available current is 5mA (min).
And this terminal is also used as timer for discharging DCDC output capacitor.
Please refer to section“3.2.2 Shutdown Method and REG50 Capacitance Setting”, for detailed explanation.

○Pin 2: STB
This is the ON/OFF setting terminal of the IC. Input reset-signal to this terminal to reset IC from latch-off.
At startup, internal bias starts at high level, and then PWM DCDC boost starts after PWM rise edge inputs.
Note: IC status (IC ON/OFF) transits depending on the voltage inputted to STB terminal. Avoid the use of intermediate
level (from 0.8V to 2.0V).
In order to discharge output voltage while STB=L and REG50UVLO=H, DIMOUT can assert High, depending on PWM
logic. About discharge behavior at end, please refer to section “3.5.3 Timing Chart” or section “3.2.2 Shutdown Method
and REG50 Capacitance Setting”.

○Pin 3: OVP
The OVP terminal is the input for over-voltage protection. If OVP is more than 3.0V(typ), the over-voltage protection
(OVP) will work. At the moment of these detections, it sets GATE=L, DIMOUT=L and starts to count up the abnormal
interval. If OVP detection continued to count four GATE clocks, IC reaches latch off. (Please refer to “3.5.5 Timing Chart”)
The OVP pin is high impedance, because the internal resistance is not connected to a certain bias.
Even if OVP function is not used, pin bias is still required because the open connection of this pin is not a fixed potential.
The setting example is separately described in the section ”3.2.7 OVP Setting”.
As PWM=L interval, IC operates to keep the OVP pin voltage therefore the output voltage. Please refer the section “TBD
the Retaining Function of The Output Voltage”.

○Pin 4: UVLO
Under Voltage Lock Out pin is the input voltage of the power stage. , IC starts the boost operation if UVLO is more than
3.0V(typ) and stops if lower than 2.7V(typ).
The UVLO pin is high impedance, because the internal resistance is not connected to a certain bias.
Even if UVLO function is not used, pin bias is still required because the open connection of this pin is not a fixed
potential.
The setting example is separately described in the section ”3.2.6 UVLO Setting”

○Pin 5: SS
This is the pin which sets the soft start interval of DC/DC converter. It performs the constant current charge of 3.0 μA to
external capacitance Css. The switching duty of GATE output will be limited during 0V to 3.7V of the SS voltage.
So the soft start interval Tss can be expressed as follows
6
Tss = 1.23*10 *Css Css: the external capacitance of the SS pin.

The logic of SS pin asserts low is defined as the latch-off state or PWM is not input high level after STB reset release.
When SS capacitance is under 1nF, take note if the in-rush current during startup is too large, or if over boost detection
(FBMAXI) mask timing is too short.
Please refer to soft start behavior in the section “3.5.4 Timing Chart ”.

○Pin 6: PWM
This is the PWM dimming signal input terminal. The high / low level of PWM pins are the following.

State PWM input voltage

PWM=H PWM=1.5V to 18.0V
PWM=L PWM=‐0.3V to 0.8V

○Pin 7: CP
Timer pin for counting the abnormal state of the over boost protection (FBMAX). If the abnormal state is detected, the CP
pin starts charging the external capacitance by 3μA. As the CP voltage reaches 3.0V, IC will be latched off. (GATE=L,
DIMOUT=L).
Please refer to section“3.2.8 Interval Until Latch Off Setting”, for detailed explanation.

○Pin 8: ADIM
This is the input pin for analog dimming signal. The ISENSE feedback point is set as 1/3 of this pin bias. If more than 3.0V
is input, ISENSE feedback voltage is clamped to limit to flow LED large current. In this condition, the input current is
caused. Please refer to <ISENSE> terminal explanation.

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○Pin 9: RT
This is the DC/DC switching frequency setting pin. DCDC frequency is decided
by connected resistor.
○The relationship between the frequency and RT resistance value (ideal)

15000
R RT  [k  ]
fSW [kHz ]
The oscillation setting ranges from 50kHz to 800kHz.
The setting example is separately described in the section ”3.2.5 DCDC
Oscillation Frequency Setting” Figure 12. RT terminal circuit example

The fail logic indicating the abnormal state can be obtained by using the right
circuit example. The gate capacitor is limited to 200pF. We recommend
RE1C001VN for M1.The RT pin output the 2.0V(typ.) in the normal state and CH1:
drops to 0V in the latch off state. When REG50 reaches to 0V,there is a point STB
that FAIL output voltage is unstable, if this is a problem, please add C1 capacitor. CH2:
Please refer to section “2.7 Behavior List of the Protect Functions” or “3.5 Timing REG50
Chart”.
CH3:
FAIL
○Pin 10: FB
This is the output terminal of error amplifier.
FB pin rises with the same slope as the SS pin during the soft-start period.
After soft -start completion (SS>3.7V), it operates as follows.

When PWM=H, it detects ISENSE terminal voltage and outputs error signal compared to analog dimming signal (ADIM).

It detects over boost (FBMAX) over FB=4.0V(typ). After the SS completion, if FB>4.0V and PWM=H continues 4clk GATE,
the CP charge starts. After that, only the FB>4.0V is monitored, if CP charge continues to the CP=3.0V, IC will be latched
off. (Please refer to section “3.5.6 Timing Chart”.)

The loop compensation setting is described in section "3.4 Loop Compensation".

○Pin 11: ISENSE

This is the input terminal for the current detection. Error amplifier compares the
lower one among 1/3 of the voltage terminal ADIM analog dimming and 1.0V(typ).
And it detects abnormal LED overcurrent at ISENSE=3.0V(typ) over. If GATE
terminal continues during four CLKs (equivalent to 40μs at fosc = 100kHz), it
becomes latch-off. (Please refer to section “3.5.7 Timing Chart”.)
Error amp Vth[V]

1.015V
1.0V
Gain=1/3

67mV

0 0.2 3.0 3.3 ADIM[V]

Figure 13. Relationship of the feedback voltage and ADIM Figure 14. ISENSE terminal circuit example

○Pin 12: GND

This is the GND pin of the IC.

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○Pin 13: DIMOUT

This is the output pin for external dimming NMOS. The table below shows the rough output
logic of each operation state, and the output H level is VCC. Please refer to “3.5 Timing Chart”
for detailed explanations, because DIMOUT logic has an exceptional behavior. Please insert
the resistor RDIM between the dimming MOS gate to improve the over shoot of LED current, as
PWM turns from low to high.

Status DIMOUT output

Normal Same logic to PWM
Abnormal GND Level

Figure 15. DIMOUT terminal circuit example

○Pin 14: GATE
This is the output terminal for driving the gate of the boost MOSFET. The high level is VCC. Frequency can be set by the
resistor connected to RT. Refer to <RT> pin description for the frequency setting.

○Pin 15: CS
The CS pin has two functions.

1. DC / DC current mode Feedback terminal

The inductor current is converted to the CS pin voltage by the sense resistor
RCS. This voltage compared to the voltage set by error amplifier controls the
output pulse.

2. Inductor current limit (OCP) terminal

The CS terminal also has an over current protection (OCP). If the voltage is
more than 0.4V(typ.), the switching operation will be stopped compulsorily. And
the next boost pulse will be restarted to normal frequency.
In addition, the CS voltage is more than 1.0V(typ.) during four GATE clocks, IC
will be latch off. As above OCP operation, if the current continues to flow
nevertheless GATE=L because of the destruction of the boost MOS, IC will
stops the operation completely.

Both of the above functions are enabled after 300ns (typ) when GATE pin Figure 16. CS terminal circuit example
asserts high, because the Leading Edge Blanking function (LEB) is included
into this IC to prevent the effect of noise.
Please refer to section “3.3.1 OCP Setting / Calculation Method for the Current Rating of DCDC Parts”, for detailed
explanation.
If the capacitance Cs in the right figure is increased to a micro order, please be careful that the limited value of NMOS
drain current Id is more than the simple calculation. Because the current Id flows not only through Rcs but also through
Cs, as the CS pin voltage moves according to Id.

○Pin 16: VCC

This is the power supply pin of the IC. Input range is from 9V to 18V.
The operation starts at more than 7.5V(typ) and shuts down at less than 7.2V(typ)

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●2.6 Detection Condition List of the Protect Functions (TYP Condition)

Detect Condition
Detection Release Timer
Protect Function Detection Protection Type
Pin SS Condition Operation
Condition PWM

FBMAX FB FB > 4.0V H(4clk) SS>3.7V FB < 4.0V CP charge Latch off

LED OCP ISENSE ISENSE > 3.0V - - ISENSE < 3.0V 4clk Latch off

Release
RT GND SHORT RT RT<VRT×90% - - NO Restart by release
RT=GND
UVLO UVLO UVLO<2.7V - - UVLO>3.0V NO Restart by release
REG50UVLO REG50 REG50<2.3V - - REG50>2.6V NO Restart by release
VCC UVLO VCC VCC<7.2V - - VCC>7.5V NO Restart by release
OVP OVP OVP>3.0V - - OVP<2.8V 4clk Latch off
OCP CS CS>0.4V - - - NO Pulse by Pulse
OCP LATCH CS CS>1.0V - - CS<1.0V 4clk Latch off
To reset the latch type protection, please set STB logic to ‘L’ once. Otherwise the detection of VCCUVLO, REG50UVLO is
required.

The clock number of timer operation corresponds to the boost pulse clock.

●2.7 Behavior List of the Protect Function

Operation of the Protect Function
Protect Function DC/DC Gate Dimming Transistor RT pin
SS Pin
Output (DIMOUT) Logic (FAILB logic)
FBMAX Stops after latch L after latch discharge after latch L after latch
LED OCP Stops immediately H immediately, L after latch discharge after latch L after latch
RT GND SHORT Stops immediately immediately L Not discharge -
L after REG50UVLO L after REG50UVLO
STB Stops immediately discharge immediately
detects detects
UVLO Stops immediately immediately L discharge immediately H (2.0V)
REG50UVLO Stops immediately immediately L discharge immediately H (2.0V)
VCC UVLO Stops immediately immediately L discharge immediately H (2.0V)
OVP Stops immediately immediately L discharge after latch L after latch
OCP Stops immediately Normal operation Not discharge H (2.0V)
OCP LATCH Stops after latch L after latch discharge after latch L after latch
Please refer to section “3.5 Timing Chart” for details.

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●3.1 Application Circuit Example

Introduce an example application using the BD9486F.
3.1.1 Basic Application Example

Vout
VCC VIN

VCC UVLO OVP

REG50
STB
GATE
RT
CS
SS
CP
PWM DIMOUT

ADIM ISENSE
FB Rs

GND

Figure 17. Basic application example

・3.1.2 Analog Dimming or PWM Dimming Examples

Vout
Vout
VCC VIN
VCC VIN

VCC UVLO VCC UVLO OVP

OVP
REG50 REG50

STB STB
GATE GATE
RT RT
CS CS
SS SS

CP CP
REG50 DIMOUT OPEN PWM DIMOUT
REG50
PWM
ADIM ADIM ISENSE
ISENSE
FB FB Rs
Rs

GND
GND

Figure 18. Example circuit for analog dimming Figure 19. Example circuit for PWM dimming

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●3.2 External Components Selection

●3.2.1 Start Up Operation and Soft Start External Capacitance Setting
The below explanation is the start up sequence of this IC
1
SS 5V VOUT
STB SLOPE
FB

OSC SS
COMP
GATE
Css
OSC DRIVER
SS=FB CS
Circuit
PWM

GATE 2 LED_OK
DIMOUT
FB
VOUT ISENSE

3
ILED
PWM
LED_OK 4
6
5

Figure 20. Startup waveform Figure 21. Circuit behavior at startup

○Explanation of start up sequence

1. Reference voltage REF50 starts by STB=H.
2. SS starts to charge at the time of first PWM=H. At this moment, the SS voltage of slow-start starts to equal FB
voltage,and the circuit becomes FB=SS regardless of PWM logic.
3. When FB=SS reaches the lower point of internal sawtooth waveform, GATE terminal outputs pulse and starts to boost
VOUT.
4. It boosts VOUT and VOUT reaches the voltage to be able to flow LED current.
5. If LED current flows over decided level, FB=SS circuit disconnects and startup behavior completes.
6. Then it works normal operation by feedback of ISENSE terminal. If LED current doesn't flow when SS becomes over
3.7V, SS=FF circuit completes forcibly and FBMAX protection starts.

○Method of setting SS external capacitance

According to the sequence described above, start time Tss that startup completes with FB=SS condition is the time that
FB voltage reaches the feedback point.
The capacitance of SS terminal is defined as Css and the feedback voltage of FB terminal is defined as VFB. The
equality on TFB is as follows.
Css [μF]  VFB[ V]
Tss  [sec]
3 [μA]

If Css is set to a very small value, rush current flows into the inductor at startup.
On the contrary, if Css is enlarged too much, LED will light up gradually.
Since Css differs in the constant set up with the characteristic searched for and differs also by factors, such as a voltage
rise ratio, an output capacitance, DCDC frequency, and LED current, please confirm with the system.

【Setting example】
When Css=0.1μF,Iss=3μA,and startup completes at VFB=3.7V, SS setting time is as follows.

0.1  106 [F]  3.7 [ V]

Tss   0.123 [sec]
3  106 [ A]

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●3.2.2 Shutdown Method and REG50 Capacitance Setting

When this IC shuts down, VOUT discharge function works. Indicated below is the sequence.

Figure 22. The waveform and diagram at shutdown

○Sequence explanation of shutdown

1. When STB=L, GATE and REG50 stop.
2. While STB=L and REG50UVLO=H, DIMOUT asserts the same logic of PWM. And VOUT is discharged until
REG50=5.0V reaches 2.3V by -5μA(typ.).
3. When VOUT is discharged enough by ILED, ILED doesn’t get to flow.
4. When REG50 voltage reaches under 2.3V(typ), whole system is shutdown.

○Setting method of REG50 capacitance

When REG50 terminal capacitance is defined as CREG , shutdown time TOFF is decided by the following equation.
C REG [F ]  (5.0  2.3) [V ]
TOFF  [sec]
5 [A]
When discharge function is used, PWM signal must be continuously inputted after STB=L.
VOUT discharge time is longest when PWM is set on mininum DUTY.
Please set CREG capacitance value with margin so that the system is shutdown after VOUT is discharged enough.

●3.2.3 VCC Series Resistance Setting

Here are the following effects of inserting series resistor Rvcc into VCC
line.
(i) In order to drop the voltage VCC, it is possible to suppress the heat
generation of the IC.
(ii) It can limit the inflow current to VCC line.
However, if resistance RVCC is set bigger, VCC voltage becomes under
minimum operation voltage (VCC<9V). RVCC must be set to an
appropriate series resistance.

IC’s inflow current line I_IN has the following inflow lines.
・IC’s circuit current…ICC
・Current of RREG connected to REG50…IREG
・Current to drive FET’s Gate…I_GATE
These decide the voltage ΔV at RVCC.
VCC terminal voltage at that time can be expressed as follows.

VCC[V]  VIN[ V]  ICC[ A]  IDCDC[ A]  IREG[ A]   RVCC[Ω]  9 [ V]

Figure 23. VCC series resistance
circuit example
Here, judgement is the 9V minimum operation voltage.
Please consider a sufficient margin when setting the series resistor of VCC.

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【setting example】
Above equation is translated as follows.
VIN[ V]  9 [ V]
RVCC[Ω] 
ICC[ A]  IDCDC[ A]  IREG[ A]

When VIN=12V, ICC=2.0mA, RREG=10kΩand IDCDC=2mA, RVCC’s value is calculated as follows.

12[ V]  9 [ V]
RVCC[]   667[]
0.002[ A]  0.002[ A]  5.0 [ V] 10000[]

(ICC is 2.6mA(typ.)) . Please set each values with tolerance and margin.

●3.2.4 LED current setting

LED current can be adjusted by setting the resistance RS [Ω] which connects to ISENSE pin and ADIM[V].

Relationship between RS and ILED current

With DC dimming (ADIM<3.0V)

1 ADIM[ V ]
RISENSE   [Ω]
3 ILED [ A ]
Without DC dimming (ADIM>3.0V)
1.015[ V ]
RISENSE  [Ω]
ILED [ A ]

【setting example】
If ILED current is 200mA and ADIM is 2.0V, we can calculate RISENSE as below.
1 ADIM[ V ] 1 2.0[ V ]
RISENSE     3.33[Ω]
3 ILED [ A ] 3 0.2[ A ]

Figure 24. LED current setting example

●3.2.5 DCDC Oscillation Frequency Setting

RRT which connects to RT pin sets the oscillation frequency fSW of DCDC.
○Relationship between frequency fSW and RT resistance (ideal)

15000
R RT  [k  ]
fSW [kHz ]
【setting example】
When DCDC frequency fsw is set to 200kHz, RRT is as follows.

15000 15000
RRT    75 [k]
fsw [kHz ] 200[kHz ]

Figure 25. RT terminal setting example

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●3.2.6 UVLO Setting

Under Voltage Lock Out pin is the input voltage of the power stage. IC starts boost operation if UVLO is more than
3.0V(typ.) and stops if lower than 2.7V(typ.).
The UVLO pin is high impedance, because the internal resistance is not connected to a certain bias.
So, the bias by the external components is required, because the open connection of this pin is not a fixed potential.

Detection voltage is set by dividing resistors R1 and R2. The resistor values can be calculated by the formula below.

○UVLO detection equation

As VIN decreases, R1 and R2 values are set in the following formula by the VINDET that UVLO detects.
( VINDET[ V]  2.7[ V])
R1  R2[kΩ]  [kΩ]
2.7[ V]

○UVLO release equation

R1 and R2 setting is decided by the equation above. The equation of UVLO
release voltage is as follows.

(R1[kΩ]  R2[kΩ])
VINCAN  3.0V  [ V]
R2[kΩ]

【setting example】
If the normal input voltage, VIN is 24V, the detect voltage of UVLO is 18V, R2 is Figure 26. UVLO setting example
30kΩ, R1 is calculated as follows.

( VINDET [ V]  2.7[ V]) (18[ V]  2.7[ V])

R1  R2[k]   30[k]   170.0 [k]
2.7[ V] 2.7[ V]

By using these R1 and R2, the release voltage of UVLO, VINCAN, can be calculated too as follows.

(R1[k]  R2[k]) 170[k]  30[k]

VINCAN  3.0[ V]   3.0[ V]  [ V]  20.0 [ V]
R2[k] 30[k]

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●3.2.7 OVP Setting

The OVP terminal is the input for over-voltage protection of output voltage.
The OVP pin is high impedance, because the internal resistance is not connected to a certain bias.

Detection voltage of VOUT is set by dividing resistors R1 and R2. The resistor values can be calculated by the formula
below.

○OVP detection equation

If VOUT is boosted abnormally, VOVPDET, the detect
voltage of OVP, R1, R2 can be expressed by the following formula.
( VOVPDET[ V]  3.0[ V])
R1  R2[k]  [k]
3.0[ V]
○OVP release equation
By using R1 and R2 in the above equation, the release voltage of
OVP, VOVPCAN can be expressed as follows.

(R1[k]  R2[k])
VOVPCAN  2.8V  [ V]
R2[k]
Figure 27. OVP setting example
【setting example】
If the normal output voltage, VOUT is 40V, the detect voltage of OVP is 48V, R2 is 10k ohm, R1 is calculated as follows.
( VOVPDET[ V]  3.0[ V]) (48[ V]  3[ V])
R1  R2[k]   10[k]   150[k]
3.0[ V] 3[ V]
By using these R1 and R2, the release voltage of OVP, VOVPCAN can be calculated as follows.

(R1[k]  R2[k]) 10[k]  150[k]

VOVPCAN  2.8[ V]   2.8[ V]  [ V]  44.8[ V]
R2[k] 10[k]

●3.2.8 Interval Until Latch Off Setting

About over boost protection (FBMAX), the capacitance value of CP terminal can set the time of latch-off. About the
behavior from abnormal detection to latch-off, please refer to the section “3.5.6 Timing Chart”.

The condition FB>4.0V(typ.) and PWM=H continues more than four GATE clocks, the CP terminal charge is started by
3μA. After that, only the FB voltage is monitored. As the CP voltage reaches to 3.0V(typ.), IC will be latched off.
The time LATCHTIME to reach to latch-off is set by CP terminal capacitance as follows.

CCP [F]  3.0 [ V]

LATCHTIME  [sec]
3.0 [A]
【setting example】
If the capacitor of CP pin is 0.47μF, the timer latch interval is as follows.

0.47 [F]  3.0 [ V]

LATCHTIME   470[m sec]
3.0 [A]

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●3.3 DCDC Parts Selection

3.3.1. OCP Setting / Calculation Method for the Current Rating of DCDC Parts
OCP detection stops the switching when the CS pin voltage is more than 0.4V. The resistor value of CS pin, RCS needs to
be considered by the coil L current. And the current rating of DCDC external parts is required more than the peak current
of the coil.
Shown below are the calculation method of the coil peak current, the selection method of Rcs (the resistor value of CS
pin) and the current rating of the external DCDC parts at Continuous Current Mode.

（the calculation method of the coil peak current, Ipeak at Continuous Current Mode）
At first, since the ripple voltage at CS pin depends on the application
condition of DCDC, the following variables are used.
Vout voltage=VOUT[V]
LED total current=IOUT[A]
DCDC input voltage of the power stage =VIN[V]
Efficiency of DCDC =η[%]
And then, the average input current IIN is calculated by the following
equation.
VOUT [ V]  IOUT [ A]
IIN  [ A]
VIN [ V]  [%]

And the ripple current of the inductor L (ΔIL[A]) can be calculated by using
DCDC the switching frequency, fsw, as follows.

( VOUT [ V ]  VIN [ V ])  VIN [ V ]

Δ IL  [A]
L[H]  VOUT [ V ]  fSW [Hz ]

On the other hand, the peak current of the inductor Ipeak can be expressed
as follows.

IL [ A ]
Ipeak  IIN [ A ]  … (1) N[V]
[A ]
2
Therefore, the bottom of the ripple current Imin is
IL [ A ]
Im in  IIN [ A ]  or 0
2

If Imin>0, the operation mode is CCM (Continuous Current Mode),

IL[A]

otherwise the mode is DCM (Discontinuous Current Mode).

(the selection method of Rcs at Continuous Current Mode)

Ipeak flows into Rcs and that causes the voltage signal to CS pin. (Please
refer to the timing chart at the right)
Peak voltage VCSpeak is as follows.
VCS[V]

VCS peak  Rcs  Ipeak [ V ]

As this VCSpeak reaches 0.4V, the DCDC output stops the switching.
Therefore, Rcs value is necessary to meet the condition below.
Rcs  Ipeak [ V ]  0.4[ V ]
Figure 28. Coil current waveform
(the current rating of the external DCDC parts)
The peak current as the CS voltage reaches OCP level (0.4V) is defined as Ipeak_det.
0.4[ V ]
Ipeak _ det  [A ] … (2)
Rcs [ ]

The relationship among Ipeak (equation (1)), Ipeak_det (equation (2)) and the current rating of parts is required to meet
the following
Ipeak  Ipeak _ det  The current rating of parts

Please make the selection of the external parts such as FET, Inductor, diode meet the above condition.

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[setting example]
Output voltage = VOUT [V] = 40V
LED total current = IOUT [A] = 0.48V
DCDC input voltage of the power stage = VIN [V] = 24V
Efficiency of DCDC =η[%] = 90%
Averaged input current IIN is calculated as follows.

VOUT [ V]  IOUT [ A] 40[ V]  0.48[ A]

IIN[ A]    0.89 [ A]
VIN[ V]  [%] 24[ V]  90[%]

If the switching frequency, fSW = 200kHz, and the inductor, L=100μH, the ripple current of the inductor L (ΔIL[A]) can be
calculated as follows.

( VOUT [ V ]  VIN [ V ])  VIN [ V ] ( 40[ V ]  24[ V ])  24[ V ]

Δ IL    0.48 [A ]
L[H]  VOUT [ V ]  fSW [Hz ] 100  10  6 [H]  40[ V ]  200  10 3 [Hz ]

Therefore the inductor peak current, Ipeak is

IL [ A ] 0.48[ A ]
Ipeak  IIN [ A ]  [ A ]  0.89[ A ]   1.13 [ A ] …calculation result of the peak current
2 2

If Rcs is assumed to be 0.3Ω

VCS peak  Rcs  Ipeak  0.3[  ]  1.13[ A ]  0.339 [ V ]  0.4 V …Rcs value confirmation

The above condition is met.

And Ipeak_det, the current OCP works, is
0.4[ V ]
Ipeak _ det   1.33 [A]
0.3[  ]

If the current rating of the used parts is 2A,

Ipeak  Ipeak _ det  The current rating  1.13[ A ]  1.33[ A ]  2.0[ A ] …current rating confirmation
of DCDC parts

This inequality meets the above relationship. The parts selection is proper.
And IMIN, the bottom of the IL ripple current, can be calculated as follows.

IL [ A ]
IMIN  IIN [ A ]  [ A ]  1.13[ A ]  0.48[ A ]  0.65[ A ]  0
2
This inequality implies that the operation is continuous current mode.

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3.3.2. Inductor Selection

The inductor value affects the input ripple current. As shown in section 3.3.1,

( VOUT [ V ]  VIN [ V ])  VIN [ V ]

Δ IL  [A]
L[H]  VOUT [ V ]  fSW [Hz ]
ΔIL
VOUT [ V]  IOUT [ A]
IIN  [ A]
VIN [ V]  [%]

IL [ A ]
Ipeak  IIN [ A ]  [A ]
2
Where
L: coil inductance [H] VOUT: DCDC output voltage [V]
VIN: input voltage [V]
IOUT: output load current (the summation of LED current) [A]
IIN: input current [A] fSW: oscillation frequency [Hz]

Figure 29. Inductor current waveform and diagram

In continuous current mode, ⊿IL is set to 30% to 50% of the output load current in many cases.
In using smaller inductor, the boost is operated by the discontinuous current mode in which the coil current returns to
zero at every period.

*The current exceeding the rated current value of inductor flown through the coil causes magnetic saturation, results in
decreasing in efficiency. Inductor needs to be selected to have such adequate margin that peak current does not
exceed the rated current value of the inductor.
*To reduce inductor loss and improve efficiency, inductor with low resistance components (DCR, ACR) needs to be
selected

3.3.3. Output Capacitance Cout Selection

VIN Output capacitor needs to be selected in consideration of equivalent series resistance
required to even the stable area of output voltage or ripple voltage. Be aware that set
IL
L
LED current may not be flown due to decrease in LED terminal voltage if output ripple

VOUT component is high.

Output ripple voltage VOUT is determined by Equation (4):

RESR ΔVout  ΔIL  RESR [ V ] ・・・・・ (4)

RCS COUT When the coil current is charged to the output capacitor as MOS turns off, much output
ripple is caused. Much ripple voltage of the output capacitor may cause the LED current

Figure 30. Output capacitor diagram ripple.

* Rating of capacitor needs to be selected to have adequate margin against output voltage.
*To use an electrolytic capacitor, adequate margin against allowable current is also necessary. Be aware that the LED
current is larger than the set value transitionally in case that LED is provided with PWM dimming especially.

3.3.4. MOSFET Selection

There is no problem if the absolute maximum rating is larger than the rated current of the inductor L, or is larger than
the sum of the tolerance voltage of COUT and the rectifying diode VF. The product with small gate capacitance (injected
charge) needs to be selected to achieve high-speed switching.
* One with over current protection setting or higher is recommended.
* The selection of one with small on resistance results in high efficiency.

3.3.5. Rectifying Diode Selection

A schottky barrier diode which has current ability higher than the rated current of L, reverse voltage larger than the
tolerance voltage of COUT, and low forward voltage VF especially needs to be selected.

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●3.4.Loop Compensation
A current mode DCDC converter has each one pole (phase lag) fp due to CR filter composed of the output capacitor and
the output resistance (= LED current) and zero (phase lead) fZ by the output capacitor and the ESR of the capacitor.
Moreover, a step-up DCDC converter has RHP zero (right-half plane zero point) fZRHP which is unique with the boost
converter. This zero may cause the unstable feedback. To avoid this by RHP zero, the loop compensation that the
cross-over frequency fc, set as follows, is suggested.
fc = fZRHP /5 (fZRHP: RHP zero frequency)
Considering the response speed, the calculated constant below is not always optimized completely. It needs to be
adequately verified with an actual device.

Figure 31. Output stage and error amplifier diagram

i. Calculate the pole frequency fp and the RHP zero frequency fZRHP of DC/DC converter
ILED VOUT  (1  D)2
fp  [Hz] fZRHP  [Hz]
2  VOUT  COUT 2  L  ILED
VOUT  VIN (Continuous Current Mode)
Where ILED = the summation of LED current, D
VOUT
ii. Calculate the phase compensation of the error amp output (fc = fZRHP/5)
fRHZP  RCS  ILED
RFB1  []
5  fp  gm  VOUT  (1  D)

1 5
CFB1   [F]
2π  RFB1  fc 2π  RFB1  fZRHP

gm  4.0  104 [S]

Above equation is described for lighting LED without the oscillation. The value may cause much error if the quick
response for the abrupt change of dimming signal is required.
To improve the transient response, RFB1 needs to be increased, and CFB1 needs to be decreased. It needs to be
adequately verified with an actual device in consideration of variation from parts to parts since phase margin is
decreased.

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●3.5.Timing Chart
3.5.1 PWM Start up 1 (Input PWM Signal After Input STB Signal)

VCC 7.5V

STB

PWM

REG50 2.6V

3.7V

SS 0.4V 0.4V

GATE

2.0V
RT

STATE OFF STANDBY SS Normal STANDBY SS

(*1) (*2) (*3) (*4) (*5) (*6)

Figure 32. PWM Start up 1 (Input PWM Signal After Input STB Signal)

(*1)…REG50 starts up when STB is changed from Low to High. In the state where the PWM signal is not inputted, SS terminal
is not charged and DCDC doesn’t start to boost, either.
(*2)…When REG50 is more than 2.6V, the reset signal is released.
(*3)…The charge of the pin SS starts at the positive edge of PWM=L to H, and the soft start starts. The GATE pulse outputs only
during the corresponding PWM=H. And while the SS is less than 0.4V, the pulse does not output. The pin SS continues
charging in spite of the assertion of PWM or OVP level.
(*4)…The soft start interval will end if the voltage of the pin SS, Vss reaches 3.7V. By this time, it boosts VOUT to the voltage
where the set LED current flows. The abnormal detection of FBMAX starts to be monitored.
(*5)…As STB=L, the boost operation is stopped instantaneously. (Discharge operation continues in the state of STB=L and
REGUVLO=L. Please refer to section 3.5.3)
(*6)…In this diagram, before the charge period is completed, STB is changed to High again. As STB=H again, the boost
operation restarts the next PWM=H. It is the same operation as the timing of (*2). (For capacitance setting of SS terminal,
please refer to section 3.2.1.

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3.5.2 PWM Start Up 2 (Input STB Signal after Inputted PWM Signal)

Figure 33. PWM Start Up 2 (Input STB Signal after Inputted PWM Signal)

(*1)…REG50 starts up when STB=H.

(*2)…When REG50UVLO releases or PWM is inputted to the edge of PWM=L→H, SS charge starts and soft start period is
started. The GATE pulse outputs only during the corresponding PWM=H. And while the SS is less than 0.4V, the pulse
does not output. The pin SS continues charging in spite of the assertion of PWM or OVP level.
(*3)…The soft start interval will end if the voltage of the pin SS, Vss reaches 3.7V. By this time, it boosts VOUT to the point where
the set LED current flows. The abnormal detection of FBMAX starts to be monitored.
(*4)…As STB=L, the boost operation is stopped instantaneously (GATE=L, SS=L). (Discharge operation works in the state of
STB=L and REG50UVLO=H. Please refer to section 3.5.3)
(*5)…In this diagram, before the discharge period is completed, STB is changed to High again. As STB=H again, operation will
be the same as the timing of (*1).

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3.5.3 Turn Off

STB

PWM

REG50 2.3V

REG50UVLO

DIMOUT

GATE

Vout

SS

RT 2.0V

STATE ON Dischange OFF

(*1) (*2)

Figure 34. Turn Off

(*1)…As STB=H→L、boost operation stops and REG50 starts to discharge.

(*2)…While STB=L, REG50UVLO=H, DIMOUT becomes same as PWM. REG50=5.0V is discharged by -5μA until
REG50=2.3V,and then IC becomes OFF state. REG50 is discharged rapidly and RT becomes 0V at the same time. VOUT is
discharged completely until this time. It should be set to avoid a sudden brightness.
About capacitance value setting of REG50, please refer to the section 3.2.2.

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3.5.4 Soft Start Function

STB

PWM

UVLO 2.7V 3.0V

VCCUVLO 7.2V 7.5V

REG50UVLO 2.3V 2.6V

3.0V 2.8V
OVP

4clk

RT 2.0V

SS

(*1) (*2)(*3) (*4) (*5) (*6) (*7)

Figure 35. Soft Start Function

(*1)…The SS pin charge does not start by just STB=H. PWM=H is required to start the soft start. In the low SS voltage, the
GATE pin duty depends on the SS voltage. And while the SS is less than 0.4V, the pulse does not output.
(*2)…By the time STB=L, the SS pin is discharged immediately. As REG50UVLO=H, RT is still High.
(*3)…As the STB recovered to STB=H, The SS charge starts immediately by the logic PWM=H in this chart.
(*4)…The SS pin is discharged immediately by the UVLO=L.
(*5)…The SS pin is discharged immediately by the VCCUVLO=L.
(*6)…The SS pin is discharged immediately by the REG50UVLO=L.
(*7)…The SS pin is not discharged by the abnormal detection of the latch off type such as OVP until the latch off.

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3.5.5 OVP Detection

Figure 36. OVP Detection

(*1)…As OVP is detected, the output GATE=L, DIMOUT=L, and the abnormal counter starts.
(*2)…If OVP is released within 4 clocks of abnormal counter of the GATE pin frequency, the boost operation restarts.
(*3)…As the OVP is detected again, the boost operation is stopped.
(*4)…As the OVP detection continues up to 4 count by the abnormal counter, IC will be latched off.
(*5)… Once IC is latched off, the boost operation doesn't restart even if OVP is released.
(*6)…The STB=L input can make IC reset.
(*7)…It normally starts as STB turns Low to High.
(*8)…The operation of the OVP detection is not related to the logic of PWM.

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3.5.6 FBMAX Detection

STB

PWM

REG50

4.0V 4.0V
FB

GATE ・・・・・ ・・・・・

① ② ③ ④

3.0V
CP

SS 3.7V

RT 2.0V

STATE STANDBY SS NORMAL CP COUNTOR STANDBY SS

latch
off
(*1) (*2) (*3) (*4) (*5) (*6) (*7)

Figure 37. FBMAX Detection

(*2)…During the soft start, it is not judged to the abnormal state even if the FB=H(FB>4.0V).
(*3)…When the PWM=H and FB=H, the abnormal counter doesn’t start immediately.
(*4)…The CP charge will start if the PWM=H and the FB=H detection continues up to 4 clocks of the GATE frequency. Once the
count starts, only FB level is monitored.
(*5)…When the FBMAX detection continues till the CP charge reaches 3.0V, IC will be latched off. The latch off interval can be
calculated by the external capacitance of CP pin. (Please refer to section 3.2.8.)
(*6)…The latch off state can be reset by the STB=L.
(*7)…It is normally started by PWM=L to H, in this figure.

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3.5.7 LED OCP Detection

STB

PWM

REG50

ISENSE 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V

RESET
START

START

START
Abnormal

END
END
COUNTOR Smaller than 4count 4count
4count

SS 0.4V

GATE

DIMOUT

RT 2.0V

STATE NORMAL LEDOCP NORMAL LEDOCP Latch off Reset NORMAL LEDOCP Latch off

abnormal abnormal (OFF) abnormal

(*1) (*2) (*3) (*4) (*5) (*6) (*7) (*8)

Figure 38. LED OCP Detection

(*1)…If ISENSE>3.0V, LEDOCP is detected, and GATE becomes L. To detect LEDOCP continuously, The DIMOUT is
compulsorily high, regardless of the PWM dimming signal.
(*2)…When the LEDOCP releases within 4 counts of the GATE frequency, the boost operation restarts.
(*3) …As the LEDOCP is detected again, the boost operation is stopped.
(*4)…If the LEDOCP detection continues up to 4 counts of GATE frequency. IC will be latched off.
(*5)…Once IC is latched off, the boost operation doesn't restart even if the LEDOCP releases.
(*6)…The latch off state can be reset by the STB=L.
(*7)…It normally starts by STB=L to H.
(*8)…The operation of the LEDOCP detection is not related to the logic of the PWM.

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BD9486F Datasheet

Operational Notes

1. Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply terminals.

2. Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.

3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.

4. Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5. Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. The absolute maximum rating of the Pd stated in this specification is when
the IC is mounted on a 70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum
rating, increase the board size and copper area to prevent exceeding the Pd rating.

6. Recommended Operating Conditions

These conditions represent a range within which the expected characteristics of the IC can be approximately obtained.
The electrical characteristics are guaranteed under the conditions of each parameter.

7. Rush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush
current may flow instantaneously due to the internal powering sequence and delays, especially if the IC
has more than one power supply. Therefore, give special consideration to power coupling capacitance,
power wiring, width of ground wiring, and routing of connections.

8. Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.

9. Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.

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Operational Notes – continued

10. Unused Input Terminals

Input terminals of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance
and extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input terminals should be connected to
the power supply or ground line.

11. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should
be avoided.

Figure 39. Example of monolithic IC structure

12. Ceramic Capacitor

When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.

13. Area of Safe Operation (ASO)

Operate the IC such that the output voltage, output current, and power dissipation are all within the Area of Safe
Operation (ASO).

14. Thermal Shutdown Circuit(TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below
the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.

15. Over Current Protection Circuit (OCP)

This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.

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BD9486F Datasheet

Ordering Information

B D 9 4 8 6 F - E2

Part Number Package Packaging and forming specification

F:SOP16 E2: Embossed tape and reel

Marking Diagrams

SOP16 (TOP VIEW)

Part Number Marking

BD9486F
LOT Number

1PIN MARK

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Physical Dimension, Tape and Reel Information

Package Name SOP16

(Max 10.35 (include.BURR))

(UNIT : mm)
PKG : SOP16
Drawing No. : EX114-5001

<Tape and Reel information>

Tape Embossed carrier tape
Quantity 2500pcs
E2
Direction
The direction is the 1pin of product is at the upper left when you hold
of feed ( reel on the left hand and you pull out the tape on the right hand )

1pin Direction of feed

Reel ∗ Order quantity needs to be multiple of the minimum quantity.

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Revision History

Date Revision Changes

12.Jul.2013 001 New Release
p.4 delete REG50_UVLO_Hysteresis item
09.Sep.2013 002 p.4 modify REG50 Discharge Current limits
Min. 4.95uA -> 3.0uA Typ. 5.00uA -> 5.0uA Max. 5.05uA -> 7.0uA
p.3 Circuit Current (Icc) add condition GATE=L,IREG50=0mA
p.6 2.2 Pin ESD Type add REG50 schematic (PWM sch. Is moved to STB sch.)
19.Nev.2013 003 p.10 Pin Description Pin11 ISENSE sentence ADIM analog dimming and 3.0V(typ)
→ADIM analog dimming and 1.0V(typ)
Figure.13 modify schematic (add ADIM=3.3V)
p.11 Modify DIMOUT explanation to ” the output H level is VCC”.
13.Feb.2014 004 Modify GATE explanation to ” The high level is VCC”.
Modify the figure.15 of DIMOUT terminal circuit example.

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 Datasheet

Notice
Precaution on using ROHM Products
1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
(Note 1)
intend to use our Products in devices requiring extremely high reliability (such as medical equipment , transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN USA EU CHINA
CLASSⅢ CLASSⅡb
CLASSⅢ CLASSⅢ
CLASSⅣ CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.

7. De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.

2. In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice - GE Rev.002
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 Datasheet

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.

Precaution for Product Label

QR code printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act,
please consult with ROHM representative in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data. ROHM shall not be in any way responsible or liable
for infringement of any intellectual property rights or other damages arising from use of such information or data.:

2. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the information contained in this document.

Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.

Notice - GE Rev.002
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 Datasheet

General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.

2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.

3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.

Notice – WE Rev.001
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