Lesson: Sequential Logic

SEQUENTIAL LOGIC CIRCUITS

Sequential Logic Circuits use flip-flops as memory elements and in which their output is dependent on
the input state

Unlike Combinational Logic circuits that change state depending upon the actual signals
being applied to their inputs at that time, Sequential Logic circuits have some form of
inherent “Memory” built in.

This means that sequential logic circuits are able to take into account their previous input
state as well as those actually present, a sort of “before” and “after” effect is involved
with sequential circuits.

In other words, the output state of a “sequential logic circuit” is a function of the
following three states, the “present input”, the “past input” and/or the “past output”.
Sequential Logic circuits remember these conditions and stay fixed in their current state
until the next clock signal changes one of the states, giving sequential logic circuits
“Memory”.

Sequential logic circuits are generally termed as two state or Bistable devices which can
have their output or outputs set in one of two basic states, a logic level “1” or a logic
level “0” and will remain “latched” (hence the name latch) indefinitely in this current
state or condition until some other input trigger pulse or signal is applied which will
cause the bistable to change its state once again.

The word “Sequential” means that things happen in a “sequence”, one after another and
in Sequential Logic circuits, the actual clock signal determines when things will happen
 next. Simple sequential logic circuits can be constructed from standard Bistable circuits
such as: Flip-flops, Latches and Counters and which themselves can be made by simply
connecting together universal NAND Gates and/or NOR Gates in a particular
combinational way to produce the required sequential circuit.

Classification of Sequential Logic

As standard logic gates are the building blocks of combinational circuits, bistable latches and
flip-flops are the basic building blocks of sequential logic circuits. Sequential logic circuits can
be constructed to produce either simple edge-triggered flip-flops or more complex sequential
circuits such as storage registers, shift registers, memory devices or counters. Either way
sequential logic circuits can be divided into the following three main categories:

 1. Event Driven – asynchronous circuits that change state immediately when enabled.
 2. Clock Driven – synchronous circuits that are synchronised to a specific clock signal.
 3. Pulse Driven – which is a combination of the two that responds to triggering pulses.

As well as the two logic states mentioned above logic level “1” and logic level “0”, a third
element is introduced that separates sequential logic circuits from their combinational logic
counterparts, namely TIME. Sequential logic circuits return back to their original steady state
once reset and sequential circuits with loops or feedback paths are said to be “cyclic” in nature.

LATCHES

Latches are basic storage elements that operate with signal levels (rather than signal transitions).
Latches controlled by a clock transition are flip-flops. Latches are level-sensitive devices. Latches are
useful for the design of the asynchronous sequential circuit.

SR (Set-Reset) Latch – SR Latch is a circuit with:

(i) 2 cross-coupled NOR gate or 2 cross-coupled NAND gate.
(ii) 2 input S for SET and R for RESET.
(iii) 2 output Q, Q’.

Under normal conditions, both the input remains 0.

The following is the RS Latch with NAND gates:
 Q Q’ STATE
1 0 Set
0 1 Reset

Case-1: S’=R’=1 (S=R=0) –

If Q = 1, Q and R’ inputs for 2nd NAND gate are both 1.
If Q = 0, Q and R’ inputs for 2nd NAND gate are 0 and 1 respectively.

Case-2: S’=0, R’=1 (S=1, R=0) –

As S’=0, the output of 1st NAND gate, Q = 1(SET state). In 2nd NAND gate,
as Q and R’ inputs are 1, Q’=0.

Case-3: S’= 1, R’= 0 (S=0, R=1) –

As R’=0, the output of 2nd NAND gate, Q’ = 1. In 1st NAND gate,
as Q and S’ inputs are 1, Q=0(RESET state).
 Case-4: S’= R’= 0 (S=R=1) –
When S=R=1, both Q and Q’ becomes 1 which is not allowed.
So, the input condition is prohibited.

FLIP FLOP

Flip flops are actually an application of logic gates. With the help of Boolean logic you
can create memory with them. Flip flops can also be considered as the most basic idea
of a Random Access Memory [RAM]. When a certain input value is given to them, they
will be remembered and executed, if the logic gates are designed correctly. A higher
application of flip flops is helpful in designing better electronic circuits.

The most commonly used application of flip flops is in the implementation of a feedback
circuit. As a memory relies on the feedback concept, flip flops can be used to design it.

There are mainly four types of flip flops that are used in electronic circuits. They are

1. The basic Flip Flop or S-R Flip Flop

2. Delay Flip Flop [D Flip Flop]
3. J-K Flip Flop
4. T Flip Flop

1. S-R Flip Flop

The SET-RESET flip flop is designed with the help of two NOR gates and also two NAND gates.
These flip flops are also called S-R Latch.

 S-R Flip Flop using NOR Gate

The design of such a flip flop includes two inputs, called the SET [S] and RESET [R]. There
are also two outputs, Q and Q’. The diagram and truth table is shown below.

S-R Flip Flop using NOR Gate

From the diagram it is evident that the flip flop has mainly four states. They are

S=1, R=0—Q=1, Q’=0

This state is also called the SET state.

S=0, R=1—Q=0, Q’=1

This state is known as the RESET state.

In both the states you can see that the outputs are just compliments of each other and
that the value of Q follows the value of S.

S=0, R=0—Q & Q’ = Remember

If both the values of S and R are switched to 0, then the circuit remembers the value of S
and R in their previous state.
 S=1, R=1—Q=0, Q’=0 [Invalid]

This is an invalid state because the values of both Q and Q’ are 0. They are supposed to be
compliments of each other. Normally, this state must be avoided.

S-R Flip Flop using NAND Gate

The circuit of the S-R flip flop using NAND Gate and its truth table is shown below.

S-R Flip Flop using NAND Gate

Like the NOR Gate S-R flip flop, this one also has four states. They are

S=1, R=0—Q=0, Q’=1

This state is also called the SET state.

S=0, R=1—Q=1, Q’=0

This state is known as the RESET state.

 In both the states you can see that the outputs are just compliments of each other and
that the value of Q follows the compliment value of S.

S=0, R=0—Q=1, & Q’ =1 [Invalid]

If both the values of S and R are switched to 0 it is an invalid state because the values
of both Q and Q’ are 1. They are supposed to be compliments of each other. Normally,
this state must be avoided.

S=1, R=1—Q & Q’= Remember

If both the values of S and R are switched to 1, then the circuit remembers the value of S
and R in their previous state.

Clocked S-R Flip Flop

It is also called a Gated S-R flip flop.

The problems with S-R flip flops using NOR and NAND gate is the invalid state. This
problem can be overcome by using a bistable SR flip-flop that can change outputs when
certain invalid states are met, regardless of the condition of either the Set or the Reset
inputs. For this, a clocked S-R flip flop is designed by adding two AND gates to a basic NOR
Gate flip flop. The circuit diagram and truth table is shown below.
 Clocked S-R Flip Flop

A clock pulse [CP] is given to the inputs of the AND Gate. When the value of the clock
pulse is ‘0’, the outputs of both the AND Gates remain ‘0’. As soon as a pulse is given
the value of CP turns ‘1’. This makes the values at S and R to pass through the NOR
Gate flip flop. But when the values of both S and R values turn ‘1’, the HIGH value of
CP causes both of them to turn to ‘0’ for a short moment. As soon as the pulse is
removed, the flip flop state becomes intermediate. Thus either of the two states may
be caused, and it depends on whether the set or reset input of the flip-flop remains a
‘1’ longer than the transition to ‘0’ at the end of the pulse. Thus the invalid states can
be eliminated.

2. D Flip Flop

The circuit diagram and truth table is given below.

 Clocked D Flip Flop

D flip flop is actually a slight modification of the above explained clocked SR flip-flop.
From the figure you can see that the D input is connected to the S input and the
complement of the D input is connected to the R input. The D input is passed on to the
flip flop when the value of CP is ‘1’. When CP is HIGH, the flip flop moves to the SET state.
If it is ‘0’, the flip flop switches to the CLEAR state.

3. J-K Flip Flop

The circuit diagram and truth-table of a J-K flip flop is shown below.
 Clocked J-K Flip Flop

A J-K flip flop can also be defined as a modification of the S-R flip flop. The only
difference is that the intermediate state is more refined and precise than that of a S-R
flip flop.

The behavior of inputs J and K is same as the S and R inputs of the S-R flip flop. The letter
J stands for SET and the letter K stands for CLEAR.

When both the inputs J and K have a HIGH state, the flip-flop switch to the complement
state. So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to
Q=1.

The circuit includes two 3-input AND gates. The output Q of the flip flop is returned back
as a feedback to the input of the AND along with other inputs like K and clock pulse [CP].
So, if the value of CP is ‘1’, the flip flop gets a CLEAR signal and with the condition that
the value of Q was earlier 1. Similarly output Q’ of the flip flop is given as a feedback to
the input of the AND along with other inputs like J and clock pulse [CP]. So the output
becomes SET when the value of CP is 1 only if the value of Q’ was earlier 1.
The output may be repeated in transitions once they have been complimented for J=K=1
because of the feedback connection in the JK flip-flop. This can be avoided by setting a
time duration lesser than the propagation delay through the flip-flop. The restriction on
the pulse width can be eliminated with a master-slave or edge-triggered construction.

Clocked T Flip Flop

Summary:

Difference between Flip-flop and Latch

Flip-Flop :
Flip-flop is a basic digital memory circuit, which stores one bit of information.Flip flops
are the fundamental blocks of most sequential circuits. It is also known as a bistable
multivibrator or a binary or one-bit memory. Flip-flops are used as memory elements in
sequential circuit.

The output is obtained in a sequential circuit from combinational circuit or flip-flop or

both. The state of flip-flop changes at active state of clock pulses and remains unaffected
when the clock pulse is not active. In particular, clocked flip flops serve as memory
elements in synchronous sequential Circuits and unclocked flip-flops (i.e., latches) serve
as memory elements in asynchronous sequential circuits.

Latch
Latch is an electronic device, which changes its output immediately based on the applied
input. It is used to store either 1 or 0 at any specified time. It consists of two inputs
namely “SET” and RESET and two outputs, which are complement to each other.
Difference between Flip-flop and Latch :

SNO Flip-flop Latch

Flip-flop is a bistable device i.e., it has two stable Latch is also a bistable device whose states
1
states that are represented as 0 and 1. are also represented as 0 and 1.
It checks the inputs but changes the output only at It checks the inputs continuously and
2 times defined by the clock signal or any other responds to the changes in inputs
control signal. immediately.
3 It is a edge triggered device. It is a level triggered device.
Gates like NOR, NOT, AND, NAND are building
4 These are also made up of gates.
blocks of flip flops.
They are classified into asynchronous or
5 There is no such classification in latches.
synchronous flipflops.
These can be used for the designing of
It forms the building blocks of many sequential
6 sequential circuits but are not generally
circuits like counters.
preferred.
7 a, Flip-flop always have a clock signal latche doesn’t have a clock signal
8 Flip-flop can be build from Latches Latches can’t build from gates
9 ex:D Flip-flop, JK Flip-flop ex:SR Latch, D Latch