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Lecture 4(2024)

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9 views17 pages

Lecture 4(2024)

Uploaded by

alyaamohammed251
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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LOGIC II

Counters & Register


Lecture 4

Dr. Marwa Gamal


❑ Displaying the contents
❑ Connecting the output of each FF to a small
indicator LED
❑The indicator LED method becomes
inconvenient as the size (number of bits) of the
counter increases because it is much harder to
decode the displayed results mentally.
❑ Electronically decoding is preferable method
Active-HIGH Decoding
❑ A MOD-X counter has X different states
❑ A decoding network is a logic circuit that
generates X different outputs.

❑ Using AND Gates for decoding


❑To Decode a MOD-8 Counter
(produce pulse at specific count)

Active-LOW Decoding
❑ Using NAND Gates for decoding
Active-HIGH Decoding
▪ How many AND gates are required to decode
completely all of the states of a MOD-32 binary
counter?

• What are the inputs to the gate that decodes for


the count of 21 (that is,101012)?
by predicting the FF control inputs for
each state of the counter

Steps of Analysis process

1) write the logic expression for each FF control


input.
2) Assume a PRESENT state for the counter
3) Apply that combination of bits (PRESENT state
) to the control logic expressions.
4) The outputs from the control expressions will
allow us to predict NEXT state
5) Repeat the analysis process until the entire
count sequence is determined.
EXAMPLE:

1) Control expression

2) Assume a PRESENT state = 0000


3 & 4 ) Apply PRESENT state and find NEXT
state
Steps of design

1) Determine the desired


number of bits (FFs) and the
desired counting

2) Draw the state transition


diagram showing all possible
states, including those that
are not part of the desired
3) Use the state transition
diagram to set up a table
that lists all PRESENT
states and their NEXT
states.
4) Add a column for each JK input (or other
inputs). Indicate the level required at each J
and K in order to produce transition to the
NEXT state.
5) Implement the final expressions (obtained from the K
map).
6) Design the logic circuits needed to generate the levels
required at each J and K input..
Steps of design
1) Determine the desired number of bits (FFs) and
the desired counting
2) Draw the state transition diagram showing all
possible states, including those that are not part
of the desired
3) Use the state transition diagram to set up a
table that lists all PRESENT states and their
NEXT states.
4) Add a column for each JK input in order to
produce transition to the NEXT state.
5) Implement the final expressions (obtained from
the K map).
6) Design the logic circuits needed to generate
the levels required at each J and K input..
Example:
MOD-5 Counter Using D-type Flip-Flops
Example:
MOD-5 Counter Using D-type Flip-Flops
Thank you!!!
Lecture 4
Ends!!!

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