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29 views6 pages

Sheet 3

Uploaded by

alyaamohammed251
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Electrical department

Logic Circuits (2)

Sheet (3)
1. Draw the gates necessary to decode all of the states of a MOD-16 counter using active-
LOW outputs.
Solution:

2. Analyze the synchronous counter in Figure 2. Draw its timing diagram and determine the
counter’s modulus.

3. Analyze the synchronous counter in Figure 3. Draw its timing diagram and determine the
counter’s modulus.
Electrical department
Logic Circuits (2)

Solution (2):
JA=KA=1 JB=KB=A JC=KC=A*B JD=KD=A*B*C CLR=A*C*D

J K CLK Q
0 0 ↑ No change
0 1 ↑ 1
1 0 ↑ 0
1 1 ↑ Toggles

Present State Control Inputs Next State


D C B A JD KD JC KC JB KB JA KA D C B A
0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1
0 0 0 1 0 0 0 0 1 1 1 1 0 0 1 0
0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 1
0 0 1 1 0 0 1 1 1 1 1 1 0 1 0 0
0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 1
0 1 0 1 0 0 0 0 1 1 1 1 0 1 1 0
0 1 1 0 0 0 0 0 0 0 1 1 0 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1
1 0 0 1 0 0 0 0 1 1 1 1 1 0 1 0
1 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1
1 0 1 1 0 0 1 1 1 1 1 1 1 1 0 0
1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1
1 1 0 1 0 0 0 0 1 1 1 1 1 1 1 0
1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0

MOD-13 (Count from 0000 to 1100)


Electrical department
Logic Circuits (2)

Solution (3):
JA=KA=1 JB= KB=𝐴̅ JC= KC=𝐴̅𝐵̅ JD=KD=𝐴̅𝐵̅ 𝐶̅

J K CLK Q
0 0 ↑ No change
0 1 ↑ 1
1 0 ↑ 0
1 1 ↑ Toggles

Present State Control Inputs Next State


D C B A 𝐶̅ 𝐵̅ 𝐴̅ JD KD JC KC JB KB JA KA D C B A
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0
0 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 1
0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1
0 1 0 1 0 1 0 0 0 0 0 0 0 1 1 0 1 0 0
0 1 1 0 0 0 1 0 0 0 0 1 1 1 1 0 1 0 1
0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0
1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
1 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0
1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 1 0 0 1
1 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 0
1 1 0 0 0 1 1 0 0 1 1 1 1 1 1 1 0 1 1
1 1 0 1 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0
1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 1
1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0

M0D-10 (Count from 1001 to 0000)


Electrical department
Logic Circuits (2)

4. Design a synchronous counter using J-K FFs that has the following sequence: 000, 010,
101, 110, and repeat. The undesired (unused) states 001, 011, 100, and 111 must always
go to 000 on the next clock pulse.

Solution (4):

Present State Next State J K


0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0

Present State Next Sate Control Inputs


C B A C B A JC KC JB KB JA KA
0 0 0 0 1 0 0 x 1 x 0 x
0 0 1 0 0 0 0 x 0 x x 1
0 1 0 1 0 1 1 x x 1 1 x
0 1 1 0 0 0 0 x x 1 x 1
1 0 0 0 0 0 x 1 0 x 0 x
1 0 1 1 1 0 x 0 1 x x 1
1 1 0 0 0 0 x 1 x 1 0 x
1 1 1 0 0 0 x 1 x 1 x 1

JC : JB: JA:
A’ A A’ A A’ A
C’B’ 0 0 C’B’ 1 0 C’B’ 0 x
C’B 1 0 C’B x x C’B 1 x
CB x x CB x x CB 0 x
CB’ x x CB’ 0 1 CB’ 0 x
JC=A’B JB= C’A’+CA JA=C’B

KC: KB : KA:
A’ A A’ A A’ A
C’B’ x x C’B’ x x C’B’ x 1
C’B x x C’B 1 1 C’B x 1
CB 1 1 CB 1 1 CB x 1
CB’ 1 0 CB’ x x CB’ x 1
KC= A’+B KB=1 KA= 1
Electrical department
Logic Circuits (2)

5. Redesign the counter of question 4 without any requirement on the unused states; that is,
their NEXT states can be don’t cares. Compare with the design from (4)

Solution (5):

Present State Next State J K


0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0

Present State Next Sate Control Inputs


C B A C B A JC KC JB KB JA KA
0 0 0 0 1 0 0 x 1 x 0 x
0 0 1 x x x x x x x x x
0 1 0 1 0 1 1 x x 1 1 x
0 1 1 x x x x x x x x x
1 0 0 x x x x x x x x x
1 0 1 1 1 0 x 0 1 x x 1
1 1 0 0 0 0 x 1 x 1 0 x
1 1 1 x x x x 1 x x x x

JC : JB: JA:
A’ A A’ A A’ A
C’B’ 0 x C’B’ 1 x C’B’ 0 x
C’B 1 x C’B x x C’B 1 x
CB x x CB x x CB 0 x
CB’ x x CB’ x 1 CB’ x x
JC=B JB=1 JA=C’B

KC: KB : KA:
A’ A A’ A A’ A
C’B’ x x C’B’ x x C’B’ x x
C’B x x C’B x x C’B x x
CB 1 1 CB x 1 CB x x
CB’ x 0 CB’ x x CB’ x 1
KC=B KB = 1 KA= 1
Electrical department
Logic Circuits (2)

6. How many clock pulses Will be needed to completely load eight bits of serial data into a
74ALS166? How does this relate to the number of flip-flops contained in the register?
Solution (6):
8 clock pulses, 8FFs.

7. Complete the timing diagram in Figure for a 74HC174. How does the timing diagram
show that the master reset is asynchronous?

Solution (7):

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