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key differences between DDR Wrapper and DDR2 Wrapper

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21 views2 pages

key differences between DDR Wrapper and DDR2 Wrapper

Uploaded by

chandrashekarhm19
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DDR SDRAM VS DDR2 SDRAM

● On-Chip Termination (OCT):

The Challenge: Signal Reflection and Crosstalk

In Double Data Rate (DDR) SDRAM, multiple chips (memory modules) share the same data, address,
and control bus. This shared environment creates two potential issues:

Signal Reflection: When a signal travels along a transmission line (DDR wrapper to DDR
controller), it can encounter impedance mismatches at the end, causing part of the signal to bounce
back (reflect) in the opposite direction. This reflected signal can distort the original signal, leading to
data errors.
Crosstalk: When multiple signals travel close together on the same bus, they can capacitively couple
with each other, inducing unwanted voltages on adjacent signals. This crosstalk can also corrupt data.

○ DDR: Relies on external termination resistors for signal integrity.


○ DDR2: Integrates termination resistors directly onto the memory chip (OCT), reducing signal
noise and allowing for higher data transfer speeds.
● Number of Banks:
○ DDR: Typically has 4 banks.
○ DDR2: Increased the number of banks to either 4 or 8, allowing for potentially greater
parallelism in memory access and improved performance.
● RDQS Signal (DDR2 only):
○ Introduced in DDR2, this is a complementary version of the DQS (Data Strobe) signal used for
data synchronisation during read operations. It can improve noise immunity and relax timing
margins, but also adds complexity and requires an extra pin.

Other Points of Differentiation:


● Version and Transfer Rates:
○ DDR: Common versions include DDR200, DDR266, DDR333 (names indicate memory clock
speed in MHz, transfer rate is typically double).
○ DDR2: Common versions include DDR2-333, DDR2-533, etc. (names indicate memory clock
speed, transfer rate is clock x 2).
● Clock Frequencies:
○ DDR: Memory clock between prefetch buffer and sense amplifier , and I/O bus frequency are
same having same values
○ DDR2: I/O bus frequency is double than memory clock frequency, allowing for faster data
transfer.
● Prefetch Buffer Depth:
○ DDR: Typically uses a 2n or 4n prefetch buffer.
○ DDR2: Uses a 4n or 8n prefetch buffer, potentially improving performance by pre-fetching more
data for the processor to work on, but with a slight latency increase.
● Mode Registers:
○ All generations (SDRAM, DDR, DDR2): SDRAM have 1 mode register,DDR one DDR2 having
three
○ Burst Length:
○ DDR: Typically supports burst lengths of 2, 4, or 8.
○ DDR2: Supports burst lengths of 4 or 8, aligned with its prefetch depth of 4n for optimal
efficiency.(not 2n)
● Voltage:
○ DDR: Operates at 2.5 V.
○ DDR2: Operates at a lower voltage (1.8 V), contributing to a significant decrease in power
consumption (around 52%).
○ Power reduction (proportional) = 1 - (New Voltage / Old Voltage)^2
● DDR: Uses a single-ended DQS signal.
● DDR2: Introduces a differential DQS (DQS#) signal.Impact on Data Alignment (Proper
Sampling) and Noise Immunity

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