IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 59, NO.

7, JULY 2024 2121

A Low-Complexity FM-UWB Transmitter With

Digital Reuse and Analog Stacking
Bo Zhou , Yifan Li , Zuhang Wang , Chen Wang , Woogeun Rhee , Fellow, IEEE,
and Zhihua Wang , Fellow, IEEE

Abstract— A frequency-modulated ultrawideband (FM-UWB)

transmitter (TX) is fabricated in 65-nm CMOS, only consisting of
simplified digital reuse modules and a radio frequency front-end
(RFFE) stacking unit. All-digital reuse scheme of subcarrier gen-
eration and frequency calibration is proposed with a reuse ratio
of more than 50%, to relax TX design complexity and eliminate
the traditional dual calibration loops and high-frequency clock.
The RFFE employs the current stacking of a dual-path ring
digital-controlled oscillator (DCO) and a wideband push–pull
power amplifier (PA), to achieve a significant RF power saving
of 30%. The experimental results show that the 3.5–4.0-GHz TX
generates a UWB signal and has an energy efficiency of 4.6 nJ/bit,
with an active area of 0.13 mm2 , a power dissipation of 0.46 mW,
and a data rate (DR) of 100 kb/s, and achieves the transmitted
power of –14.3 dBm and the phase noise (PN) of –86.2 dBc/Hz at
the 1-MHz offset frequency. Compared to the reported literature,
the prototype FM-UWB TX presents both digital unit reuse and
analog module stacking schemes.
Index Terms— Digital reuse, frequency-modulated ultrawide-
band (FM-UWB), low complexity, low power consumption, radio Fig. 1. Conventional FM-UWB TX structures. (a) TX-I and (b) TX-II.
frequency front-end (RFFE) stacking, transmitter (TX).
oscillator (LO) or RF carrier synchronization, meaning short
I. I NTRODUCTION synchronization slot and low design complexity [6], [7], [8],

U LTRAWIDEBAND (UWB) technique has been widely

used in short-range wireless transmission and ranging in
recent years, due to its high energy efficiency, low radiated
[9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19],
[20], [21], [22], [23], [24], [25], [26], [27]. Besides, the
antenna design of the FM-UWB system is greatly relaxed,
power, good interference resilience, high penetration capa- due to avoiding a high peak-to-average transmit power ratio
bility, and high range resolution [1], [2], [3], [4], [5], [6], and having a well-controlled RF band [7], when compared
[7], [8], [9]. Frequency-modulated UWB (FM-UWB) systems to impulse radio UWB (IR-UWB) [1], [2], [3], [4], [5]. FM-
generate a constant-envelope UWB signal with wideband UWB has the low phase noise (PN) requirement (−80 dBc/Hz
frequency modulation (FM) and achieve a flat in-band power at 1-MHz offset frequency) to allow for a 20-dB stronger
spectral density (PSD) and a steep spectral roll-off property, FM-UWB interferer [16], which simplifies the design of the
which enables a well-defined radio frequency (RF) bandwidth current-starving RF oscillators (OSCs) [8], [9], [10], [11], [12],
and high robustness by avoiding narrowband interferers [6], [13], [14], [15], [16].
[7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], The conventional FM-UWB transmitter (TX) architectures
[18], [19], [20], [21], [22], [23], [24], [25], [26], [27]. The [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18] are
FM-UWB performs FM demodulation without an RF local shown in Fig. 1. The TX-I employs a dual-FM scheme: a
frequency shift keying (FSK)-modulated triangular subcarrier
Manuscript received 23 August 2023; revised 1 November 2023;
accepted 29 November 2023. Date of publication 18 December 2023; date generated by a relaxation OSC where triangular frequency f 0
of current version 28 June 2024. This article was approved by Associate represents data 0 and f 1 represents 1, followed by RF FM for
Editor Pui-In Mak. This work was supported by the Beijing Natural Science UWB signal generation by using an RF OSC. The TX-I needs
Foundation under Grant 4222076. (Corresponding author: Bo Zhou.)
Bo Zhou, Yifan Li, and Chen Wang are with the School of Integrated two additional frequency-locked loops (FLLs) or phase-locked
Circuits and Electronics, Beijing Institute of Technology, Beijing 100081, loops (PLLs): one for carrier center frequency and the other
China (e-mail: [email protected]). for subcarrier center frequency, while in TX-II, a direct digital
Zuhang Wang is with the Beijing Microelectronics Technology Institute,
Beijing 100076, China. frequency synthesis (DDFS) followed by a digital-to-analog
Woogeun Rhee and Zhihua Wang are with the Institute of Microelectronics, converter (DAC) conducts the 2-FSK triangular subcarrier
Tsinghua University, Beijing 100084, China. and an RF OSC performs UWB RF FM. TX-II requires a
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/JSSC.2023.3340890. high-frequency external clock (HFEC) FOSR for subcarrier
Digital Object Identifier 10.1109/JSSC.2023.3340890 generation and also needs an FLL or PLL for carrier frequency
0018-9200 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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2122 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 59, NO. 7, JULY 2024

calibration. Without current reuse scheme, the traditional RF

front-end (RFFE) modules are power-hungry, considering that
the RF OSC is always cascaded by the power amplifier (PA).
The existing TXs [15], [16] utilize an LC-tank voltage-
controlled oscillator (VCO) for RF FM and a PLL for carrier
frequency calibration, which degrades the silicon cost. The
presented circuits [8], [9] optimize the PA and OSC designs,
while the embedded dual loops (PLL + FLL or PLL +
PLL) for subcarrier and carrier frequency calibration are not
attractive in hardware complexity. The presented prototypes Fig. 2. Block diagram of digital subcarrier generator.
[17], [18] using the DDFS as subcarrier generation require
a high oversampling ratio clock for the embedded phase
accumulator, which inversely limits the data rate (DR). The
existing structures [7], [8], [9], [19] with high subcarrier
frequency to benefit high DR and thus good energy effi-
ciency not only have low RF modulation index βRF , which
inversely degrades the UWB spectrum, but also have large
subcarrier modulation index βsub , which is not in favor of
the receiver performance. The reported TX [7] utilizing a
high-robust relaxation OSC for subcarrier generation and a
semi-digital quasi-continuous FLL for frequency calibration Fig. 3. LPF design considerations.
has a large power dissipation up to 5 mW. The existing
designs [11], [12], [13], [14] are regarded as ultralow-power
II. P ROPOSED TX A RCHITECTURE
implementations, by employing a relaxation OSC, a current-
controlled ring OSC, and a successive approximation register A. Digital Subcarrier Generator
(SAR)-based FLL, to perform subcarrier generation, RF FM, The traditional FM-UWB TXs use continuous or analog
and frequency calibration, while multistage push–pull PA triangular waves, generated by a relaxation OSC or got from
needs further optimization. The reported work [10] utilizes a a DDFS, as the 2-FSK subcarriers. However, a discrete step
class-C PA to minimize the overall power consumption, while wave followed by a low-pass filter (LPF) is also equivalent
dual PLLs are used for frequency calibration. The existing to a continuous triangular wave in function, which is shown
TX [20] employs current stacking technology to reduce the in Fig. 2 and is clearly clarified in the Appendix using a
system power consumption, but it relies on external control mathematical model. Theoretical analysis verifies that discrete
words for dual-frequency calibration. The reported work [26] step wave filtered by an LPF can replace continuous triangular
uses an SAR-based automatic frequency control (AFC) loop wave in subcarrier generation, that is, digital-type subcarrier
to alternatively calibrate carrier and subcarrier and adopts generation is feasible.
single-stage push–pull architecture for the PA, but power An up-down counter (CNT) under the counting clock FCK is
consumption needs further optimization. for k-level discrete step wave. To achieve 2-FSK modulation,
In conclusion, the conventional frequency calibration uses FCK is generated from the carrier frequency component of the
either semi-digital PLL or quasi-continuous FLL, or all- RF OSC, via a dual-modulus divider (DMD) that has a divider
digital SAR-FLL or SAR-AFC, where the SAR-based digital ratio of N1 for data 1 and N2 for data 0. Both LPF and RF
calibration scheme is dominant. The main-stream RF OSC OSC are combined as the digital-controlled oscillator (DCO).
employs low-cost ring structures. The popular PA utilizes As a result, the digital subcarrier STRI is generated, where the
multi- or single-stage push–pull architecture. In addition, frequency f 0 represents data 0 and f 1 is for data 1.
the existing TXs either need two groups of frequency cal- The LPF not only performs the DAC function from digital
ibration loops or require a high-frequency clock, or lack discrete subcarrier to analog continuous one but eliminates
of effective power-saving methods in RFFE. All these the inverse effect of high-speed instantaneous f DCO frequency
degrade the silicon area, power dissipation, and hardware deviation (±250 MHz during the subcarrier half-period) on
complexity. both subcarrier frequency robustness and RF FM linearity.
The prototype presented in this article digitally imple- For subcarrier generation, using f DCO as the reference clock
ments subcarrier generation and frequency calibration with will not affect the modulation linearity and frequency stability
a high unit-reuse ratio and employs a current stacking and and avoids the conventional HFEC. Once the DCO center
digital dual-tuning scheme in RFFE modules, which benefits frequency ( f DCO ) is determined, the subcarrier frequencies
semi-digital TX structure, single-loop synchronous calibration, ( f 0 and f 1 ) conforming to (1) are also fixed. Here, k = 64,
and low-cost low-power features. This article is organized as N1 = 32, and N2 = 36
follows. Section II gives the proposed TX architecture, and
Section III presents the detailed circuit implementations of f 0 = f DCO /(N2 × k × 2), f 1 = f DCO /(N1 × k × 2). (1)
digital reuse and analog stacking, followed by experimental As shown in Fig. 3, second-order LPF is chosen to consider
results in Section IV and conclusion in Section V. design complexity, silicon size, and harmonic interference

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ZHOU et al.: LOW-COMPLEXITY FM-UWB TRANSMITTER WITH DIGITAL REUSE AND ANALOG STACKING 2123

Fig. 4. FM-UWB TX architectures. (a) Without digital reuse. (b) Proposed digital reuse.

since third-order one needs a larger component size, while The LPF to eliminate inverse effects of high-frequency
first-order one has poor interference suppression. The LPF (harmonic) components in the digital subcarrier is integrated
with 5-MHz cutoff frequency makes a tradeoff between sub- to the modulation path of the dual-tuning DCO. The ring
carrier frequencies (0.814 and 0.916 MHz) and harmonic DCO shown in Fig. 4(a) has dual digital inputs: SDCO setting
(around 111 MHz) suppression, that is, useful subcarrier com- the discrete calibration current for f DCO deviation and STRI
ponents are not affected by the LPF, but the useless harmonics controlling the continuous modulation current, together with
are attenuated by more than 54 (= 40log10 (111/5)) dB. the embedded LPF, for RF FM, that is, both carrier and
subcarrier center frequencies are tuned by SDCO and UWB
bandwidth is controlled by STRI .
B. Single-Loop Synchronous Calibration and Dual-Tuning
DCO
C. Digital Reuse and Analog Stacking
The SAR-AFC loop given in Fig. 4(a), consisting of a true-
single-phase-clock (TSPC) divider-by-N2 , an IF divider-by-32, As shown in Fig. 4(a), based on dividers and counters,
a counter-based frequency discriminator (FD), an SAR logic frequency calibration and subcarrier generation are all-digital
with a reference counting value (NCAL ), and an odd–even and work alternately under the control of S M signal, which
unit [28] based on a divider-by-2, generates a digital control means that both can be reused (or shared) in digital units. The
word (DCW) SDCO to calibrate the center frequency ( f DCO ) of 8-bit CNT-based FD and 6-bit up-down CNT-based subcarrier
ring DCO to follow the following equation: generation are co-design, which is called a dual-mode counter
(DMC). TSPC-based RF DMD and divider-by-N2 are also
f DCO = NCAL × N2 ×32 × f FD integrated, that is, critical digital units (DMC and DMD) are
= NCAL × N2 ×32 × f REF /2. (2) highly shared between subcarrier generation (S M = 1) and
frequency synchronous calibration (S M = 0).
The digital 2-FSK subcarrier generator given in Fig. 4(a), Among the digital modules, the high-frequency DMC and
comprised of an up-down CNT and a TSPC DMD, gets the DMD occupy the majority of power dissipation and silicon
DCW STRI for FM. By using f DCO as the reference clock, the area. The rest of the IF digital units (including an SAR
subcarrier frequencies meeting (1) are related to the carrier logic, a divider-by-32, and a divider-by-2) are not dominant
center frequency. in hardware cost. Therefore, more than 50% reuse ratio is
When the DCO center frequency is calibrated, the subcarrier achieved, by estimating the active area and power dissipation
frequency f Sub centered at ( f 0 + f 1 )/2 is also certain. Both car- percentages of both DMC and DMD in the whole digital units.
rier and subcarrier center frequencies are tuned by SDCO , that The dual-path ring DCO conducts linear RF FM to get the
is, the all-digital SAR-AFC loop conducts the synchronous cal- UWB signal and has two groups of oscillation currents: the
ibration for both carrier and subcarrier frequencies. Compared small and varying one (I M ) for UWB FM, and the other
to the existing designs, the proposed scheme simplifies the large and stable one (IC ) for frequency calibration. The single-
traditional dual loops (for subcarrier and carrier frequencies) stage push–pull PA with an external LC network for wideband
to single one. transmission shares the RF current IC with the dual-path DCO,

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2124 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 59, NO. 7, JULY 2024

which benefits the RFFE module stacking to save TX power

consumption.
Based on the clarifications above, we propose the low-
power low-complexity FM-UWB TX based on digital reuse
and analog stacking given in Fig. 4(b). When S M = 1, the
DMD, DMC, and the DCO with the embedded LPF form
the digital subcarrier generator, controlled by TXData , while
under S M = 0, the DCO, DMD, divider-by-32, DMC, and SAR
logic conduct the frequency synchronous calibration for both
carrier and subcarrier. A three-wire serial peripheral interface
(SPI) provides the DCW NCAL with a typical value of 104 for
the frequency calibration, and a pseudorandom bit source
(PRBS) with a bit length of 227 – 1 generates the transmitted
data TXData under a DR of 100 kb/s. A clock generator gets
100-kHz FDR for the PRBS and 62.5-kHz FREF for the SAR-
AFC, from the external 500-kHz FIN clock. A square wave
signal (Sub) containing the subcarrier frequency information
is obtained through an output inverter and is used for chip test.
In conclusion, the proposed TX shown in Fig. 4(b) benefits
digital reuse, synchronous calibration, and current stacking,
to eliminate both dual calibration loops and HFEC, which are
different from the existing designs.

D. Dual Work Modes

As shown in Fig. 5, the presented TX controlled by the
mode word S M has dual work modes: calibration and modula-
tion. In the modulation mode (S M = 1), f DCO with an average
value of 3.75 GHz is divided by N1 = 32 for data 1 or by
N2 = 36 for data 0, via the TSPC DMD under the control
of TXData . As a result, the 2-FSK signal (FCK ) is got as the
clock of DMC, and thus, the digital subcarrier (discrete step
wave) STRI is generated, where the frequency f 0 represents
data 0 and f 1 is for data 1, as shown in (1). The DCO outputs Fig. 5. TX work modes. (a) Calibration and (b) modulation.
the constant-envelope UWB signal with a frequency range
from 3.5 to 4.0 GHz under the control of STRI .
During the calibration mode (S M = 0), by counting the externally, considering the f OSC temperature drift of RF DCO
rising-edge number (Y ) of IF clock FCK during a reference and according to the minimum calibration time depicted in the
clock period (FFD ), the DMC compares the frequency devi- following equation:
ation between fDCO /(32 × N2 ) and NCAL f FD , to control the 2×6−1 11
tCAL,min = = = 352µs. (3)
SAR logic to set/clear each bit from MSB to LSB and get the f REF /2 31.25kHz
desired 6-bit DCW SDCO , which inversely tunes the switched-
current (SC) array of the ring DCO to offset f DCO deviation. III. D ESIGN I MPLEMENTATION
Once all 6 bits are generated, the SAR output SDCO is held The proposed TX is mainly composed of digital reuse units
by a control signal (Trig), and the DCO center frequency and an RFFE stacking module, which is considered as semi-
following (2) is fixed to 3.75 GHz until the next calibration digital low-cost implementation.
period arrives. When the DCO center frequency is fixed,
the subcarrier frequency f Sub centered at ( f 0 + f 1 )/2 =
0.865 MHz is also determined, that is, the TX conducts A. Digital Reuse
the synchronous calibration for both carrier and subcarrier The proposed all-digital reuse of subcarrier generation and
frequencies. A divider-by-2 based odd–even unit generates two frequency calibration is given in Fig. 6, where S M = 0 is for
quadrature clocks (FFD and FSAR ) to make the DMC work synchronous frequency calibration and S M = 1 supports digital
in odd calibration clock periods and SAR logic operates in subcarrier generation. A DMC is used as an 8-bit accumulator
even ones, for high f DCO calibration accuracy since DCO for the FD of the SAR-AFC and a 6-bit up-down counter for
needs enough settling time, that is, both DMC and SAR the step-wave subcarrier. A TSPC RF DMD has two groups of
logic work alternatively with on and lock statuses, during the division ratios: N1 = 32 is for data and N2 = 36 is for data 0
calibration period. The loop works in an intermittent operation and frequency calibration. Both DMD and DMC are critical
scheme with an ultralow duty cycle of the control signal S M . and high-frequency modules, which are fully shared between
The calibration operation frequency is low and can be set the subcarrier generator and SAR-AFC loop. The presented

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ZHOU et al.: LOW-COMPLEXITY FM-UWB TRANSMITTER WITH DIGITAL REUSE AND ANALOG STACKING 2125

Fig. 6. Proposed all-digital reuse of subcarrier generation and frequency

calibration.

design has more than a 50% reuse ratio in digital units since
the other low-complexity low-frequency modules (SAR logic,
divider-by-32, and divider-by-2) are not dominant in hardware
cost.
During the calibration mode shown in Fig. 5(a), the DMC
and SAR logic work alternately, under the quadrature clocks
of FFD /FSAR and with the enable signals of Trig/ENSAR .
The DMC works in odd calibration clock (FFD ) periods and
the SAR logic works in even ones (FSAR ), and thus, the
calibration time slot follows (3) and lasts 11 calibration periods
after the mode swapping. After all 6 bits are generated, the
SAR output SDCO is held until the next calibration period
arrives, and finally, f DCO approaches the desired 3.75 GHz.
In the modulation mode shown in Fig. 4(b), the DCO output
VDCO used as the high-frequency clock, together with the
DMD controlled by the transmitted data, generates the 2-FSK Fig. 7. Proposed digital core units. (a) DMC and (b) DMD.
counting clock FCK for the DMC to get the subcarrier STRI .
As the core module for digital reuse, the proposed DMC
circuit is shown in Fig. 7(a), consisting of an 8-bit accumulator the CK rising edges. When both CK and D are high, the
(CNT), an 8-bit latch, a polarity selector, a mode-swapping node Y is floating and discharged due to the leakage current,
logic, and an SAR-logic trigger. In the modulation mode which makes the TSPC DFF only work under high-frequency
(S M = 1), the 8-bit accumulator with the 2-FSK clock FCK conditions.
is always activated to generate D7∼0 , and the 6-bit polarity
selector controlled by D6 gets STRI from D5∼0 . In the calibra-
B. RFFE Stacking
tion mode (S M = 0), the 8-bit accumulator is activated to get
the counting value of FCK rising edges during the odd FFD The proposed RFFE module based on current stacking and
clock periods and stops counting when D = 255 or Trig = 1. digital dual-tuning scheme is shown in Fig. 8(a). For RF ring
During the even FFD clock periods, the 8-bit accumulator is OSC, a three-stage cascaded configuration contributes to low
reset to zero, and the 8-bit latch is enabled to hold the counting power consumption, low cost, high oscillation frequency, and
value Y , which is sent to the SAR logic for comparison accepted PN [29], [30], [31]. With two groups of SC arrays, the
to NCAL . The mode-swapping logic controlled by S M makes ring DCO has dual digital inputs: SDCO setting the discrete cali-
DMC work as the subcarrier generator or the FD of SAR-AFC. bration current IC for ±20% f DCO deviation, with a calibration
The SAR-logic trigger makes ENSAR low or high during the gain of 23.4 MHz/LSB; and STRI controlling the continuous
odd/even FFD clock periods, respectively. modulation current I M , together with the embedded LPF, for
The presented DMD shown in Fig. 7(b) consists of 500-MHz RF FM, with a modulation gain of 7.8 MHz/LSB.
two-stage cascaded RF dividers: the fixed divider-by-4 Three-stage cascaded inverters (M6 –M8 and M10 –M12 ) with
using two TSPC-type D flip-flops (DFFs) with low-voltage- each-stage parasitic-capacitor Cunit form the DCO core with
threshold (LVT) transistors, followed by the 8/9 DMD using two groups of oscillation currents I M and IC for f DCO tuning,
five TSPC-type DFFs and two OR gates with regular- as shown in (4). Here, VOV = 80 mV is the transistor over-drive
voltage-threshold (RVT) transistors. The TSPC DFF with voltage. Strict current matching among M14−17 and MPA1−4
low-level-effective reset function is also shown in Fig. 7(b). is necessary for dual-path tuning. Two groups of SC arrays
With the node Y pre-charged to high, when the clock CK with different ON/OFF schemes imposed on the drain and gate
is low, the DFF has a fast response to make Q = D at terminals of current mirrors aim at high-speed STRI data and

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2126 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 59, NO. 7, JULY 2024

Class-AB PA achieves a tradeoff between power efficiency,

design complexity, driving requirement, and good linearity,
which is widely applied in the constant-envelope FM-UWB
systems [11], [12], [13], [14]. To avoid using a harmonic res-
onator network or an RF chock inductor that exists in Class-C
PA [10], push–pull configuration is employed to minimize die
area [9]. Therefore, the presented PA adopts the single-stage
push–pull class-AB architecture. Matching design between
the diode-connected dc biasing transistors MPA3 and MPA4
and the push–pull power transistors MPA1 and MPA2 ensures
that the latter have the conduction angles of 180◦ –360◦ .
The resistors R2 and R3 and capacitors C2 and C3 , together
with the push–pull transistors and the load network, form a
band-pass filter for the UWB signal amplification. The PA is
followed by a two-stage L-type wideband matching network,
composed of an external inductor L EX of 2.5 nH, two external
capacitors CC of 2 pF and CEX of 0.5 pF, a bonding-wire
inductor L bond of 2 nH, and a pad parasitic capacitor Cpad
of 90 fF. The external LC network considers the adverse effects
of parasitic packaging inductance and capacitance, ensures
process/voltage/temperature (PVT) robustness on impedance
matching, and saves chip area.
The PA is designed to match a 50- antenna load with
a current dissipation of about 0.21 mA. The PA also has an
output power of −14.3 dBm, which conforms to the following
equation and meets BRF = 500-MHz RF bandwidth, to be
Fig. 8. Proposed RFFE. (a) Module circuit and (b) stacking scheme.
compatible with the indoor FCC spectral mask with a PSD of
−41.3 dBm/MHz [12], [13], [14]:
low-frequency SDCO stream, respectively, BRF
POUT = −41.3dBm/MHz + 10log10 . (5)
I M + IC 1MHz
f DCO =
. (4)
9Cunit VDD − VSG,PA2 − VGS,PA1 − VOV,M17 Fig. 8(b) clarifies the analog stacking scheme for PA and
DCO with RF current sharing. IC is only controlled by SDCO
To generate a Federal Communications Commission (FCC)- with the strict current match between M14 /MPA3 /MPA4 and
compliant UWB signal, the FM-UWB system requires that the M17 /MPA1 /MPA2 . When the frequency calibration is done, IC
PN is −80 dBc/Hz at 1-MHz offset frequency and the FM is fixed and Vac is thus a certain value. DCO clamped between
nonlinearity is less than 10% [21]. As shown in (4), when the Vac and ground has the fixed IC and varying I M currents,
DCO frequency calibration is done, IC is fixed and f DCO is and PA working between 1.3 V and Vac has the fixed IC
thus directly proportional to I M or STRI , considering that VGS current. Considering that IC (0.21 mA) is large and constant,
of MPA1,2 and VOV of M17 are certain values. Therefore, strict while I M (0.07 mA) is small and varying, DCO and PA
current matching among M14−17 , MPA1−4 , and STRI SC array are stacked up and down to share IC , respectively. M9 and
ensures the high modulation linearity, together with the LPF M13 play the role of isolation buffer to ensure that the DCO
for harmonic suppression. drives both PA and DMD well. The capacitor CB1 plays a
The PN of ring OSC is affected by the number of delay role as an alternating-current (ac) bypass to ensure that the
inverters and the flicker and thermal noises of devices, accord- PA has the same ac ground as the DCO. All these avoid the
ing to Hajimiri models [30]. The symmetric output waveform dynamic interacting between the DCO and PA. The proposed
from the delay inverters benefits low noise, and the size stacking scheme achieves 30% RF power saving according
ratio of the inverter PMOS/NMOS deserves to be treated to the following equation under dual power supplies of 1.0
carefully. Larger size PMOS current mirror rather than NMOS and 1.3 V:
one is applied to optimize the 1/ f noise, considering that
0.21 × 1.3 + 0.07 × 1.0
the 1/f noise is inversely proportional to the device size. ηP = 1 − = 30%. (6)
In addition, PMOS current mirror with VSB = 0 will not (0.21 + 0.07) × 1.0 + 0.21 × 1.0
cause the substrate noise for the DCO core. Dual-path current Fig. 9 gives the proposed second-order Butterworth LPF
mirrors introduce noise and bias disturbance to the DCO core. based on active RC architecture, with a cutoff frequency of
In addition, the large proportion of IC in the DCO total current 5.0 MHz and a slew rate higher than 6.25 V/µs, to suppress
(I M + IC ) contributes to low PN. Therefore, low-pass filtering high-frequency components of the subcarrier signal centered
components (R1 , C1 , CB1 , and CB2 ), p-type current mirrors, at 0.865 MHz. The LPF is low cost and low power, with a
an LPF, and the high ratio of IC over I M are introduced to simple and traditional fold-cascode [operational transconduc-
optimize PN. tance amplifier (OTA)]. The LPF transfer function G LPF (s)

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ZHOU et al.: LOW-COMPLEXITY FM-UWB TRANSMITTER WITH DIGITAL REUSE AND ANALOG STACKING 2127

Fig. 9. Proposed second-order Butterworth LPF.

Fig. 11. TX breakdowns. (a) Cost optimization and (b) power dissipation.

Fig. 10. Chip micrograph in 65-nm CMOS.

is shown in (7), which shows that the cutoff frequency is

inversely proportional to the RC time constant. Here, R A = Fig. 12. TX chip test bench.
R B = R = 10 k, C A = 2C = 4.5 pF, and C B = C = 2.25 pF
1
G LPF (s) = TX power consumption is 0.606 or 0.456 mW, without or with
R A R B C A C B s 2 + (R A + R B )C B s + 1
analog stacking architecture. Namely, power optimizations of
1±i 1
⇒ s1,2 = , ωcutoff = √ . (7) RFFE and TX are 30% and 25%, respectively. In addition,
2RC 2RC DMC and DMD with the area and dissipation of 0.015 mm2
and 0.1 mW occupy 56.6% and 88.5% in the total area
IV. E XPERIMENTAL R ESULTS (0.0265 mm2 ) and consumption (0.113 mW) of digital units,
The proposed TX is fabricated in 65-nm CMOS, with dual respectively, That is, digital reuse scheme achieves more than
supply voltages of 1.3 V for the TX RFFE and 1.0 V for the 50% reuse ratio, from hardware cost.
rest of the modules. Fig. 10 shows the chip micrograph with a Fig. 12 gives the TX chip test bench. A field-programmable
total area of 1.3 mm2 and an active area of 0.13 mm2 , where gate array (FPGA) board provides the three-wire data for
all the TX modules are clearly demonstrated. Fig. 11 gives the on-chip SPI module with online DCW setting. By using
TX breakdowns in power dissipation and active area, where an Agilent E8363B Vector Network Analyzer to observe S-
the detailed cost of each module is clearly listed. The chip parameters, the PA output impendence is loaded to the 50-
has the measured power dissipation of 0.46 and 0.44 mW instrument port, with the external LC network. A data catcher
in modulation and calibration modes, respectively. Under is employed to store the measured results from the out-of-date
100-kb/s DR, the TX achieves an energy efficiency of Agilent E4407B spectrum analyzer, getting the TX spectra and
4.6 nJ/bit. the PNs. A signal generator provides the external 500-kHz
The active area of digital modules is 0.0415 or 0.0265 mm2 , clock for the TX chip, and a Tektronix MDO3054 oscilloscope
and the TX silicon area is 0.1435 or 0.1285 mm2 , without is used to observe the signal transient waveforms and the
(w/o) or with (w/i) digital reuse scheme, that is, area savings subcarrier spectrum. A printed circuit board (PCB) is designed
of digital units and the TX are 36% and 10.5%, respectively. to generate the biasing currents and supply voltages for the
The RFFE power dissipation is 0.493 or 0.343 mW, and the measured chip and is supplied by a dc power.

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2128 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 59, NO. 7, JULY 2024

Fig. 14. Measured carrier PN of TX RFFE.

Fig. 15. Simulated modulation linearity for RF FM.

of 3.0–4.5 GHz with SDCO controlled by the SAR logic. The

measured RF PN of the RFFE (ring DCO and PA) centered
Fig. 13. Measured subcarrier performances. (a) Spectrum, (b) transient
behavior, and (c) PN. at 3.75 GHz is –86.2 dBc/Hz at 1-MHz offset frequency,
which is given in Fig. 14 and meets the PN requirement
(−80 dBc/Hz at 1-MHz offset frequency) of the FM-UWB
Fig. 13 shows the measured subcarrier performances. The system.
subcarrier frequencies of 814 and 916 kHz represent data Fig. 15 shows the simulated DCO transient behaviors. The
0 and 1, respectively, to verify 2-FSK modulation well with DCO instantaneous frequency varies between 3.5 and 4.0 GHz
a βsub of 1.02. The spectrum sidelobes below −55 dBm and is directly proportional to the digital subcarrier STRI with
and located at the offset frequencies equal to the DR the frequency of 916 kHz and the amplitude of 0–63. The
harmonics are also observed, which have less effects on modulation-gain nonlinearity of less than 1% of the ring DCO
the 2-FSK modulation. The 2-FSK subcarrier signal cen- is also observed, which meets the linearity requirement of the
tered at 0.865 MHz simply follows the PRBS data pattern, FM-UWB system.
where the series of about nine square waveforms represents As shown in Fig. 16, the measured and simulated PA
data 1 and the sequence of about eight square waveforms output reflection coefficients (S22 ) are less than –12.6 and
is for data 0, during each bit period under 100-kb/s DR. –15.2 dB, respectively, with a 50- impedance match, within
The measured subcarrier PN is –90.6 dBc/Hz at the desired the desired 3.5–4.0-GHz frequency band. The PA achieves
100-kHz offset frequency, considering that the subcarrier has the simulated –8.2-dBm input and –6.2-dBm output 1-dB
a frequency deviation of 102 (=916 − 814) kHz shown compression point (P1dB) with 3-dB power gain. With a two-
in Fig. 13(a). tone (3.75 and 3.74 GHz) input, PA has the simulated –3-dBm
The dual-path ring DCO achieves the measured FM input third-order intercept point (IIP3), to show that the PA
range of 3.5–4.0 GHz with STRI generated by the has good linearity within the desired input- and output-power
DMC and gets the measured frequency calibration range levels. The PA also has –14.3-dBm output power to

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ZHOU et al.: LOW-COMPLEXITY FM-UWB TRANSMITTER WITH DIGITAL REUSE AND ANALOG STACKING 2129

Fig. 17. Measured TX output spectra. (a) 500-MHz UWB and (b) tunable
RF band with different NCAL settings.
Fig. 16. Measured and simulated PA performances. (a) S22 and (b) P1dB,
IIP3, and PAE.
TABLE I
TX P ERFORMANCE S UMMARY AND C OMPARISON

ensure 500-MHz RF bandwidth, with the simulated

power-added efficiency (PAE) of about 8.1%.
Fig. 17 gives the measured TX output spectra, centered at
3.75 GHz with the –10-dB RF bandwidth of about 500 MHz,
and satisfying the FCC mask. Un-modulated carrier spectrum
showing the RF output power of –14.3 dBm is also given as a
comparison, to clearly clarify that the FM-UWB is a wideband
spread-spectrum system that converts the narrow-bandwidth
carrier signal to the 500-MHz UWB one, with βRF of 289.
The measured f DCO calibration performance with different
NCAL setting is also shown in Fig. 17, demonstrating that
the center frequency of RF carrier or IF subcarrier is effec-
tively controlled by NCAL from the SPI. The 1-LSB change
in the word NCAL causes the UWB frequency band shift of
about 36 MHz as expected, which conforms to (2), that is, the
center frequencies of both subcarrier and carrier signals are
digitally reconfigurable.
The TX performances are summarized and compared to Table II shows the detailed architecture comparison. With
the existing designs in Table I. The presented work has dual calibration loops/HFEC/ultralow reuse ratio, the exist-
obvious advantages in power consumption, silicon size, and ing designs using multiple FSK (M-FSK) or duty cycle or
PN, in comparison to the existing literature. A higher tripler power-saving schemes have low βRF and high βsub to
DR (400 kb/s) could be achieved, by adjusting the digi- degrade UWB spectrum and receiver performance. The pro-
tal DMD with a division ratio from 32/36 to 8/9, which posed structure with high βRF and low βsub has obvious merits
significantly improves the energy efficiency but does not in frequency synchronous calibration to reduce 50% loop
degrade hardware cost and will be considered as a future number, module reuse scheme with 36% digital area saving
work. and more than 50% reuse ratio, digital subcarrier generation to

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2130 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 59, NO. 7, JULY 2024

TABLE II
TX A RCHITECTURE C OMPARISON AND M ERITS

Fig. 18. Subcarrier time- and frequency-domain analyses.

k
X
F(ω) = Fi (ω)
i=1
2A sin (k + 1)TCK ω/2 sin(kTCK ω/2)
 
= . (10)
ω sin(TCK ω/2)
eliminate the HFEC, and in RFFE stacking with 25% TX After the LPF with a cutoff frequency of 5 MHz, TCK ω/2 is
power optimization. small and less than 0.14, and thus, sin(TCK ω/2) is simplified
to TCK ω/2. As a result, Fourier transform is simplified to (11)
and its time-domain signal meeting (12) is analog triangular
V. C ONCLUSION wave with a period of 2kTCK and an amplitude of kA
A 3.5–4.0-GHz FM-UWB TX is fabricated in 65-nm
CMOS, with 0.46-mW power consumption and 4.6-nJ/bit FSub (ω) ≈ Ak 2 TCK sinc2 (kTCK ω/2). (11)
(
energy efficiency under 100-kb/s DR. The presented design k A − A|t|/TCK , |t| ≤ kTCK
generates an FCC-compliant UWB signal, with the active area f Sub (t) = (12)
0, |t| > kTCK .
of 0.13 mm2 , the transmitted power of –14.3 dBm, and the
PN of –86.2 dBc/Hz at the 1-MHz offset frequency. The TX Theoretical analysis verifies that discrete step wave fil-
achieves a digital-module reuse ratio of more than 50% and tered by an LPF can replace continuous triangular waves in
an RFFE power saving of 30%. subcarrier generation, that is, digital-type 2-FSK subcarrier
The proposed work has the following merits: 1) semi-digital generation is feasible.
TX structure with several digital units and an RFFE module to
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Jun. 1999.

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2132 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 59, NO. 7, JULY 2024

Woogeun Rhee (Fellow, IEEE) received the Zhihua Wang (Fellow, IEEE) received the B.S.,
B.S. degree in electronics engineering from Seoul M.S., and Ph.D. degrees in electronic engineering
National University, Seoul, South Korea, in 1991, the from Tsinghua University, Beijing, China, in 1983,
M.S. degree in electrical engineering from the Uni- 1985, and 1990, respectively.
versity of California at Los Angeles, Los Angeles, He has served as a Full Professor and the
CA, USA, in 1993, and the Ph.D. degree in elec- Deputy Director of the Institute of Microelec-
trical and computer engineering from the University tronics, Tsinghua University, since 1997 and
of Illinois at Urbana–Champaign, Champaign, IL, 2000, respectively. He was a Visiting Scholar
USA, in 2001. at CMU from 1992 to 1993 and KU Leuven
From 1997 to 2001, he was with Conex- from 1993 to 1994, and a Visiting Professor at
ant Systems, Newport Beach, CA, USA, where HKUST from September 2014 to March 2015.
he was the Principal Engineer and developed low-power and low-cost He has coauthored 12 books/chapters, over 183 (480) papers in international
fractional-N synthesizers. From 2001 to 2006, he was with the IBM journals (conferences), and over 244 (29) papers in Chinese journals (con-
Thomas J. Watson Research Center, Yorktown Heights, NY, USA, and worked ferences). He holds 123 Chinese and eight U.S. patents. His current research
on clocking area for high-speed I/O serial links, including low-jitter phase- mainly focuses on CMOS radio frequency integrated circuits and biomedical
locked loops, clock-and-data recovery circuits, and on-chip testability circuits. applications, involving radio frequency identification, phase-locked loop, low-
In August 2006, he joined the Faculty of the School of Integrated Circuits power wireless transceivers, and smart clinic equipment combined with
(formerly, the Department of Microelectronics and Nanoelectronics, Institute leading-edge radio frequency integrated circuits (RFIC) and digital image
of Microelectronics), Tsinghua University, Beijing, China, as an Associate processing techniques.
Professor and became a Professor in December 2011. He has published more Dr. Wang has served as an AdCom Member for IEEE SSCS from 2016 to
than 150 IEEE articles and holds 24 U.S. patents. His current research interests 2019 and a Technology Program Committee Member for IEEE ISSCC
include short-range low-power radios for next-generation wireless systems and from 2005 to 2011 and has been a Steering Committee Member of IEEE
clock/frequency generation circuits for wireline and wireless communications. A-SSCC since 2005. He also served as the Chairperson for the IEEE
Dr. Rhee is an Ex-Officio AdCom Member of the Solid-State Circuits Solid-State Circuits Society (SSCS) Beijing Chapter from 1999 to 2009,
Society from 2020 to 2021 and an IEEE Distinguished Lecturer from 2016 to the Technical Program Chair for A-SSCC 2013, a Guest Editor for Spe-
2017 and has been an SSCS Chapters Steering Committee Member since cial Issues of IEEE J OURNAL OF S OLID -S TATE C IRCUITS in December
2021. He has served on the Technical Program Committee of several IEEE 2006, December 2009, and November 2014, an Associate Editor for IEEE
conferences, including ISSCC, CICC, and A-SSCC. He is the TPC Chair of T RANSACTIONS ON C IRCUITS AND S YSTEMS—I: R EGULAR PAPERS, IEEE
A-SSCC 2021. He currently serves as an Associate Editor for IEEE Open T RANSACTIONS ON C IRCUITS AND S YSTEMS —II: E XPRESS B RIEFS, and
Journal of the Solid-State Circuits Society. He was an Associate Editor IEEE T RANSACTIONS ON B IOMEDICAL C IRCUITS AND S YSTEMS, and
of IEEE J OURNAL OF S OLID -S TATE C IRCUITS from 2012 to 2018 and other administrative/expert committee positions in China’s national science
IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS —II: E XPRESS B RIEFS and technology projects.
from 2008 to 2009 and a Guest Editor for the Special Issue of IEEE J OURNAL
OF S OLID -S TATE C IRCUITS in November 2012 and November 2013.

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