Learning objectives

● Getting started with Proteus design Suite 

● First PROTEUS 8 Schematic 
● LED & Switch animation 
PROTEUS ● Digital to Analogue Conversion 
Logic Gates ● Logic Gates
Dr Diarmuid Ó Briain ● Digital Logic
● Digital logic, Flip-Flops
● Analogue Signals
● Graphs
Topic 2.5 – Logic Gates Topic 2.5 – Logic Gates 2

Logic Gate Families TTL

● Classified according to the semiconductor ● Transistors perform both the logic function
technology used in their manufacture. and the amplifying function.
● Metal Oxide Semiconductor (CMOS) and ● The Texas Instruments 7400 family
Transistor-Transistor-Logic (TTL) became an industry standard.
– CMOS: 4000 Series ● Sub-Categories
– TTL: 74 Series – 74LS: Low-power Schottky
– 74HC: family has High-speed CMOS circuitry
– 74HCT: family is a special version of 74HC
with 74LS TTL compatible inputs so 74HCT
can be safely mixed with 74LS in the same
system.
Topic 2.5 – Logic Gates 3 Topic 2.5 – Logic Gates 4
TTL MOSFET
● Operate with a 5-volt power 7400 s g d
Silicon di Oxide
supply between Voltage Insulation
1 14
Common Collector (VCC) and +5V
GND. N N
Drain
● A TTL input signal is defined P
as:
– "low" when between 0V s g d
and 0.8V with respect to Gate
earth.
Source
– "high" when between 2V N N
and the VCC (5V) 7 8 N-Channel
P
n-channel

Topic 2.5 – Logic Gates 5 Topic 2.5 – Logic Gates 6

CMOS CMOS (4000 Series)

● Complementary Metal Oxide Semiconductor ● Operates over a wide supply 4011
(CMOS) is a type of MOSFET fabrication process voltage range, typically +3 to
1 14
that uses complementary and symmetrical pairs +15V 3-15V
of p-channel and n-channel MOSFETs for logic ● The operating speed of CMOS
functions. drops as supply voltage
● Used for: drops.
– Constructing ICs, including microprocessors, ● The best supply voltage for
microcontrollers, memory chips, and other digital CMOS is usually +5 or +9V.
logic circuits. ● The supply voltage for CMOS
– Analogue circuits such as image sensors, data is referred to as VDD and the
converters, RF circuits, and highly integrated ground connection is
transceivers for many types of communication. 7 8
sometimes referred to as VSS
● Preferred to TTL for most applications. or GND.
Topic 2.5 – Logic Gates 7 Topic 2.5 – Logic Gates 8
–
CMOS (4000 Series) CMOS (4000 Series)
● CMOS inputs have a high ● These ICs are sensitive to
impedance and are easy to drive, 4011 4011
1
static electricity and are 1
inputs draw little current and don't 14 14
3-15V easily damaged. Use anti- 3-15V
"load down" devices providing
input signals to them. static precautions when
handling CMOS ICs.
● CMOS outputs have superior fan-
out capabilities compared to TTL; ● The 74HC and 74HCT are
in some cases, CMOS can drive equally sensitive.
five times as many other inputs
as a comparable TTL device.
● CMOS devices can tolerate
variations in the power supply
voltage much better than TTL 7 8 7 8
devices.

Topic 2.5 – Logic Gates 9 Topic 2.5 – Logic Gates 10

IC Properties Logic Gate Symbols

ANSI/IEEE 91 IEC 60617 BS 3939
Property 4000 Series 74 Series 74HC 74 Series 74HCT 74 Series 74LS
Technology CMOS High-speed High-speed CMOS TTL Low-power
CMOS TTL compatible Schottky Buffer
Power Supply 3 to 15V 2 to 6V 5V ±0.5V 5V ±0.25V
Inputs Very high Z. Unused connected to +Vdd or 0V. 'Float' high to if NOT
unconnected.
Outputs Can sink and Can sink and source about 20mA Can sink up to
source about 5mA 16mA but source AND
(10mA with 9V only about 2mA
supply)
Fan-out One output can One output can drive up to 50 CMOS, One output can NAND
drive up to 50 74HC or 74HCT inputs, but only 10 drive up to 10 74LS
CMOS, 74HC or 74LS inputs. inputs or 50 74HCT
74HCT inputs, but inputs. OR
only one 74LS
input.
NOR
Maximum about 1MHz about 25MHz about 25MHz about 35MHz
Frequency
Power A few µW. A few µW. A few µW. A few mW. XOR
consumption
of the IC itself
XNOR
Topic 2.5 – Logic Gates 11 Topic 2.5 – Logic Gates 12
Logic Circuits – N/OT (Inverter) Logic Circuits - AND

Truth table
Truth table
A X | A X A B X | A.B
F T F F F
T F F T F X
A A B
T F F
Binary Truth table T T T
A X |A 390Ω Binary Truth table
0 1 6V A B X | A.B 390Ω
1 0 0 0 0 6V
0 1 0
● Bulb lit when switch is not pressed. ● Bulb will only light if “A” AND “B” are
1 0 0 depressed together.
A means N/OT A ● Bulb is not lit when switch is pressed.
1 1 1
● “X” is the opposite state to “A”.
A.B means “A” AND “B”
Topic 2.5 – Logic Gates 13 Topic 2.5 – Logic Gates 14

Logic Circuits - NAND Logic Circuits - OR

Truth table Truth table X

A B X | A.B A B X | A+B
F F T F F F
X
F T T F T T
T F T T F T B
T T F A B
T T T
Binary Truth table
A
Binary Truth table
A B X | A.B A B X | A+B
390Ω 390Ω
0 0 1 0 0 0
6V 6V
0 1 1
0 1 1
1 0 1 ● Bulb will always light unless “A” AND “B” are ● Bulb will light if either “A” OR “B” are
depressed together. 1 0 1
1 1 0 depressed.
1 1 1
A.B means N/OT “A” AND “B” A+B means “A” OR “B”
Topic 2.5 – Logic Gates 15 Topic 2.5 – Logic Gates 16
Logic Circuits - NOR Logic Circuits - XOR

A
Truth table X Truth table 100Ω
A B X | A+B A B X|
F F T F F F X
F T F A F T T B
T F F T F T 100Ω
T T F B T T F
Binary Truth table Binary Truth table
A B X | A+B A B X| 6V
390Ω
0 0 1 0 0 0
6V
0 1 0 0 1 1 ● Bulb will light if either “A” OR “B” are
Bulb will light unless either “A” or “B” or depressed.
1 0 0 ● 1 0 1
both are depressed.
1 1 0 1 1 0
A+B means “A” N/OR “B” means “A” XOR “B”
Topic 2.5 – Logic Gates 17 Topic 2.5 – Logic Gates 18

N/OT gates using NAND gates N/OT gates using NAND gates
N/OT N/OT
A 1 A A A A 1 A A A

A & A A A A & A A A

AND

Binary Truth table

A B X | A.B
0 0 0
0 1 0
1 0 0
1 1 1

Topic 2.5 – Logic Gates 19 Topic 2.5 – Logic Gates 20

N/OT gates using NAND gates N/OT gates using NAND gates
N/OT N/OT
A 1 A A A A 1 A A A

A & A A A A & A A A

AND AND
I II III IV V I II III IV V
Binary Truth table Binary Truth table

A B X | A.B I II III IV V A B X | A.B I II III IV V

0 0 0 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0
1 0 0 1 1 0 0 1 1
1 1 1 1 1 1 1 1 1

Topic 2.5 – Logic Gates 21 Topic 2.5 – Logic Gates 22

N/OT gates using NAND gates N/OT gates using NAND gates
N/OT N/OT
A 1 A A A A 1 A A A

A & A A A A & A A A

AND AND
I II III IV V I II III IV V
Binary Truth table Binary Truth table

A B X | A.B I II III IV V A B X | A.B I II III IV V

0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 1 0 0 0 0 0
1 0 0 1 1 1 1 0 0 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1

Topic 2.5 – Logic Gates 23 Topic 2.5 – Logic Gates 24

N/OT gates using NAND gates N/OT gates using NAND gates
N/OT
A 1 A A A

A & A A A

AND
I II III IV V
I II III IV V
Binary Truth table A X | A I II III IV V
A B X | A.B I II III IV V 0 1 0 0 0 0 1
0 0 0 0 0 0 0 1 1 0 0 0 0 0 1
0 1 0 0 0 0 0 1 1 1 1 1 0
1 0 0 1 1 1 1 0 1 1 1 1 0
1 1 1 1 1 1 1 0

Topic 2.5 – Logic Gates 25 Topic 2.5 – Logic Gates 26

AND gates using NAND gates AND gates using NAND gates

AND AND from NAND gates AND AND from NAND gates
A A
B A.B A.B B A.B A.B
A & & A & &
A.B A.B
B B
A B A.B A B A.B
A A.B A A.B
0 0 0 B A.B 0 0 0 B A.B

0 1 0 0 1 0
I I
1 0 0 II III
1 0 0 II III
1 1 1 1 1 1
A B I II III A.B A B I II III A.B
0 0 0 0 0
0 1 0 1 0
1 0 1 0 0
1 1 1 1 1

Topic 2.5 – Logic Gates 27 Topic 2.5 – Logic Gates 28

AND gates using NAND gates AND gates using NAND gates

AND AND from NAND gates AND AND from NAND gates
A A
B A.B A.B B A.B A.B
A & & A & &
A.B A.B
B B
A B A.B A B A.B
A A.B A A.B
0 0 0 B A.B 0 0 0 B A.B

0 1 0 0 1 0
I I
1 0 0 II III
1 0 0 II III
1 1 1 1 1 1
A B I II III A.B A B I II III A.B
0 0 0 1 0 0 0 1 1
0 1 0 1 0 1 0 1 1
1 0 0 1 1 0 0 1 1
1 1 1 0 1 1 1 0 0

Topic 2.5 – Logic Gates 29 Topic 2.5 – Logic Gates 30

AND gates using NAND gates OR gates using NAND gates

AND AND from NAND gates OR OR from NAND gates

A & A
A A.B A
A.B A.B B
B A & & & A+B
A.B
B &
A B A.B B
A B A.B B I
A A.B
0 0 0 B A.B 0 0 0 A
A
0 1 0 0 1 1
A+B
I 1 0 1
1 0 0 II III B
B
1 1 1 1 1 1
II III
A B I II III A.B
0 0 0 1 1 0 A I A B II B III A+B

0 1 0 1 1 0 0 0

1 0 0 1 1 0 0 1

1 1 1 0 0 1 1 0
1 1

Topic 2.5 – Logic Gates 31 Topic 2.5 – Logic Gates 32

OR gates using NAND gates OR gates using NAND gates

OR OR from NAND gates OR OR from NAND gates

A & A A & A
A.B A A.B A
B & B &
A+B A+B
B & B &
A B A.B B I A B A.B B I
0 0 0 A
0 0 0 A
A A
0 1 1 0 1 1
A+B A+B
1 0 1 B 1 0 1 B
B B
1 1 1 1 1 1
II III II III

A I A B II B III A+B A I A B II B III A+B

0 0 1 0 0 0 1 0 0 1
0 0 1 1 0 0 1 1 1 0
1 1 0 0 1 1 0 0 0 1
1 1 0 1 1 1 0 1 1 0

Topic 2.5 – Logic Gates 33 Topic 2.5 – Logic Gates 34

OR gates using NAND gates OR gates using NAND gates

OR OR from NAND gates OR OR from NAND gates

A & A A & A
A.B A A.B A
B & B &
A+B A+B
B & B &
A B A.B B I A B A.B B I
0 0 0 A
0 0 0 A
A A
0 1 1 0 1 1
A+B A+B
1 0 1 B 1 0 1 B
B B
1 1 1 1 1 1
II III II III

A I A B II B III A+B A I A B II B III A+B

0 0 1 0 0 1 1 0 0 1 0 0 1 1 0
0 0 1 1 1 0 0 0 0 1 1 1 0 0 1
1 1 0 0 0 1 0 1 1 0 0 0 1 0 1
1 1 0 1 1 0 0 1 1 0 1 1 0 0 1

Topic 2.5 – Logic Gates 35 Topic 2.5 – Logic Gates 36

 Logic Gate Laboratory

Laboratory

Logic Gates

Topic 2.5 – Logic Gates 38

Learning objectives
Bóthar Chill Chainnigh, Ceatharlach

● Getting started with Proteus design Suite  Suiomh Gréasáin: www.itcarlow.ie

Guthán: (059) 917 5000

● First PROTEUS 8 Schematic  R-phost: [email protected]

● LED & Switch animation  EUR ING Dr Diarmuid Ó Briain

● Digital to Analogue Conversion  Innealtóir Cairte

● Logic Gates  Léachtóir

engcore
● Digital Logic
● Digital logic, Flip-Flops
● Analogue Signals
● Graphs advancing technology 40
Topic 2.5 – Logic Gates 39 40