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Real time FPGA implementation of induction machine model - a novel

approach

Conference Paper · October 2007

DOI: 10.1109/ACEMP.2007.4510576 · Source: IEEE Xplore

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 Real Time FPGA Implementation of Induction
Machine Model – A Novel Approach
Erkan DUMAN (a) Hayrettin CAN (b) Erhan AKIN (c)
(a)
Firat University, Department of Computer Engineering, 23119-Elazig-TURKEY, [email protected]
(b)
Firat University, Department of Computer Engineering, 23119-Elazig-TURKEY, [email protected]
(c)
Firat University, Department of Computer Engineering, 23119-Elazig-TURKEY, [email protected]

Abstract- This paper presents the real-time hardware utilized Quartus-II environment to develop and simulate FPGA
implementation of three-phase induction motor modelling, designs and then download these design files into our
using a Field Programmable Gate Array (FPGA) device, in development kit.
order to use in real-time simulations. The proposed model runs To develop a simulation of a complex and large dynamic
directly in hardware by using FPGA technology and it allows a
system, we must begin by developing mathematical models of the
remarkable speed up in comparison with conventional models
which based only software. Such a model was developed with system components and their interactions [2]. Depending on the
the aim of meeting the real-time simulations needs while system to be modeled, development of a representative set of
solving the limitations of traditional solutions, in particular for mathematical models may be an easy task or it may require a great
hardware-in-the-loop simulation of electrical machines and deal of work. In cases where the system’s dynamics are not
systems. In the previous studies, this technology had been only simple, it will be necessary for the developers to find alternative
used to implement I/O processes of simulations due to solutions or to decrease the degree of accuracy of the system [8].
insufficient devices having the constraints about the size and Here, we propose FPGA-based a novel approach for modelling
the number of the general purposed ports. However in more dynamic and large systems and it can be applied to any complex
recent times, higher densities, higher speed and cost
system which consists of matrix equations. We chose the system
advantages have enabled the use of such devices in a wider
variety of applications. In this paper, we defined the three- as a three-phase induction motor and it was suitable to
phase induction motor by state-space representation which demonstrate the straightness and performance of our method. In
models a system as a set of differential equations using matrix this paper, we defined the three-phase induction motor by state-
form. Therefore our system was transformed into an space representation which models a system as a set of differential
application of real-time matrix multiplication in FPGA using equations using matrix forms. Therefore our system was
floating point number system. We utilized Quartus-II transformed into an application of real-time matrix multiplication
environment to develop FPGA designs and then download in FPGA using floating point number system in single-precision
these design files into our development kit. and this title had been studied in details [1]. Shortly, due to
limited range in the fixed-point format, we preferred to work with
I. INTRODUCTION the floating-point in order to represent real values in binary
number system [6, 11].
The variety of application areas of FPGAs has been The proposed model runs directly in hardware by using FPGA
increased especially in last decade due to new products have technology so it allows a remarkable speed up in comparison with
nearly a few million gates with clock rates approaching to conventional techniques which based only software. Such a model
the level of GHz. The basic topics used this technology can was developed with the aim of meeting the real-time simulations
be sorted as following: Digital Signal Processing (DSP), needs while solving the limitations of traditional solutions, in
image processing, multimedia applications, high-speed particular for hardware-in-the-loop simulation of electrical
communications and networking equipment such as routers machines and systems [9, 10]. In the previous studies, this
and switches, the implementation of bus protocols such as technology had been only used to implement I/O processes of
peripheral component interconnect (PCI), microprocessor simulations due to insufficient devices having the constraints
glue logic, co-processors and micro-peripheral controllers about the size and the number of the general purposed ports.
[4]. However in more recent times, higher densities, higher speed and
In addition to enhancements about the size and cost advantages have enabled the use of such devices in a wider
performance of new FPGA devices, they have new features variety of applications [3].
and hardware components such as high-speed multipliers The rest of the paper is organized as follows. Section II
and accumulators for intensive DSP applications. Moreover, describes the structure of proposed technique with hardware
the developers can obtain the additional software tools modules and demonstrates the experimental results obtained from
including high-level compilers, graphical environments to Quartus-II environment. The last section includes the conclusions.
design and test of their applications. For instance; we

1-4244-0891-1/07/$20.00 2007 IEEE

 II. FPGA IMPLEMENTATION OF INDUCTION MOTOR We used single precision floating point numbers in the model
so the input and output bit-widths of this block are 32 bits. The
A three-phase induction motor can be modeled in the simulation results of fpMAC are presented in Figure 1.b. It is
dX shown that five pairs of numbers are multiplied and the products
form of = AX + BU where the variables of X and U are accumulated in time interval of 800 ns with 100 Mhz system-
dt
indicate state and input variables respectively [5, 7]. The clock.
gain matrices of A and B determine the motor specific Fig. 2 shows the architecture of the two dimensional systolic
parameters. Therefore this model is actually consisting of array for matrix multiplication. In such an array, all elements are
floating-point matrix multiplication and then accumulation. designed for intensive local communication and parallelism. Each
However, it requires a very high computation power to fpMAC block communicates with its nearest neighbour. The
implement these arithmetic processes especially in real-time input data, as well as partial outputs flow through the array. This
applications. The aim of this study is to develop a FPGA schematic was built for the modelling of induction motor so that
based model of an electrical machine in form of matrix the size of this array is 4x1, suitable for the number of the input
multiplication so as to use in real-time simulation. matrices. The row input values indicate the motor parameters and
As shown in Fig. 1.a, we defined the basic building block also they can be stored in a memory instead of applying by an
of the proposed architecture which used to compute the input port. This storage unit should be triggered by a counter
result of the product process of a row of one matrix with a block in order to get address value. However, the state variables
column of another if their dimensions are appropriate. We (the values of the current or flux) and input variables (the values
shortened it as fpMAC (floating-point Multiple- of voltages) changes in each step of process during the simulation.
Accumulate). The fpMAC receives a series of floating-point Therefore these inputs should be entered into to model via a
number pairs, multiplies the pairs and accumulates these column input port in serial. The new values of each state variable
products in sequence. Fig.1.a shows the schematic design of are flowed through the entire column by enabling input pin of shift
fpMAC in Quartus-II environment. It consists of a floating- and finally the elements of final matrix are occurred in output port
point multiplier and adder from this environment’s built-in of C_out in sequence. The outputs ripple out through the bottom-
library and they are activated by setting the input pins of edge elements of the array.
clocken_fpmul and clocken_fpadd. The input port C_in is
used to flow final results of fpMACs through an array.

Fig. 1: FPGA design of floating-point Multiplication-Accumulate (fpMAC) and its simulation results.
 The latency involved the proposed architecture is We defined the timing constraint of calculation loop for motor
dependent on the computation time and bandwidth model less then 1 µs because the real-time simulation with good
properties of the fpMAC block. For real time applications, accuracy requires such a small latency. The parameters for array
the rate of output should be synchronous to the input. The size and bit-widths for number system can be modified for any
accuracy of the computations also depends on the output required application. Moreover, the proposed architecture can be
arrive time relative to the input. easily extended for computing the greater size matrices.

Fig. 2: FPGA implementation of induction motor as a systolic array for multiplication of two matrices with the sizes of 4xn and nx1.
 The developed design was synthesized on Altera researchers can easily implement these designs in Quartus-II or
PCI2C35N development kit including 2C35F672C6 FPGA any other development environment.
chip and the desired performance was obtained by own
maximum achievable clock speed 100 MHz. The required
area size and the number of I/O pins for the proposed REFERENCES
induction motor model are about ten and fourteen percent
respectively. In addition to this, the design utilized fourteen 1 S. Prakhya, “Real-time matrix multiplication in FPGA”, Madras
dedicated embedded multiplier 9-bit multipliers. University, India, 2005
2 Jim Ledin, “Simulation Engineering”, CMP Books, 2001
In each time step of a simulation, the B-column input is
3 J.O. Hamblen, T.S. Hall, M.D. Furman, “Rapid prototyping of
applied to the top edge of the array as shown in Fig. 2. For digital systems”, Springer, 2006
example, the values of fluxes (denoted by X) 4 Z. Navabi, “Embedded core design with FPGAs”, McGraw-Hill,
ψ qs ,ψ ds ,ψ qr ,ψ dr are sent as pulses to the input port 2007
5 H.B. Ertan, M.Y. Üçtuğ, R. Colyer, A. Consoli, “Modern
B_input. Similarly, the corresponding row elements of gain Electrical Drives”, Kluwer Academic Publishers, 2000
matrix A are sent as pulses to the input port A_input. Since 6 P. Belanovic, “Library of Parameterized Hardware Modules for
Floating-Point Arithmetic with An Example Application”,
the design is systolic, all fpMACs receive the same input Northeastern University, Boston, Massachusetts, 2002
data stream. 7 B. Ozpineci, L. M. Tolbert, “Simulink Implementation of
After the pairs of input elements arrives the all fpMACs, Induction Machine Model-A Modular Approach”, IEEE
the product of them are computed and then loaded into International, IEMDC’03, 2003
8 C. Dufour, S. Abourida, J. Belanger , “Real-time simulation of
accumulator. Subsequent pairs are multiplied and induction motor IGBT drive on a PC-cluster”, IPST 2003, New
accumulated until the entire row and column elements are Orleans, 2003
loaded. At the time all computations finished, the results are 9 S. Vamsidhar, B.G. Fernandes, “Hardware-in-the-loop simulation
sent through the bottom edge of the array, output port based design and experimental evaluation of DTC strategies”, 35th
Annual IEEE PESC, Aachen, Germany, 2004
C_out. The elements of product matrix are rippled out 10 F. Ricci, H. Le-Huy, “Modeling and simulation of FPGA-based
through this port by setting pin shift, one at a time. In n-1 variable speed drives using Simulink”, Mathematics and
clock cycles, all elements of the product matrix are flushed Computers in Simulation 63, 183-195, 2003
out of the array. 11 J. Liang, R. Tessier, O. Mencer, “Floating Point Unit Generation
and Evaluation for FPGAs”, 11th Annual IEEE FCCM’03, 2003

III. CONCLUSION

In this paper, we presented a low level FPGA

implementation of three-phase induction machine model in
order to use in real-time simulations. Our proposed model
requires a very small latency in comparison with the
previous studies that it is less than 1 µs. Such a model was
developed with the aim of meeting the real-time simulations
needs while solving the limitations of traditional solutions,
in particular for hardware-in-the-loop simulation of
electrical machines and systems. In this paper, we defined
the three-phase induction motor by state-space
representation which models a system as a set of differential
equations using matrix forms. Therefore our system was
transformed into an application of real-time matrix
multiplication in FPGA.
We utilized a PCI form FPGA development kit from
Altera so the developed design can be run in a PC-based
simulation environment. Moreover, we chose Quartus-II
environment to develop FPGA designs and then download
these design files into our development kit.
In the next study, our proposed design can be tested in a
PC-based simulation environment. Here, we only
emphasized that our original low level hardware modules
could be used to model the behavior of three-phase
induction machine. Moreover, our proposed hardware
modules were explained in detail in this study so the

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