The 33rd International Symposium on

Power Semiconductor Devices and ICs (ISPSD)

May 30 - June 3, 2021, Nagoya Full Virtual Conference

SiC-P7
Avalanche Reliability of Planar-gate SiC MOSFET
with Varied JFET Region Width and Its Balance
with Characteristic Performance
Zhengyun Zhu1, Na Ren1,2, Hongyi Xu1, Li Liu1 and Kuang Sheng1,2
1
Electrical Engineering Department, Zhejiang University, Hangzhou, China
2
Hangzhou Innovation Center, Zhejiang University, Hangzhou, China
E-mail: [email protected]

Abstract—In this work, the influence of JFET region width TCAD simulation. Finally, a feasible range of JFET region
on 1200V SiC MOSFET’s avalanche reliability is studied with width is concluded from an integrated FOM which takes
unclamped inductive switching (UIS) test. It is revealed that both the DUTs’ performance and reliability into account.
the highest avalanche capability is achieved with a JFET
region width of 4μm. As presented in TCAD silmulation,
locallized heat accumulation arising from high channel current II. DEVICE FABRICATION AND UIS TEST SETUP
density proves to be the failure mechanism. Furthermore, the 1200V/2A planar-gate SiC MOSFETs, with an active
balance between device performance and reliability with region of 0.58mm2, are fabricated on the same 4-inch SiC
different JFET region width design is discussed by considering
epitaxial wafer. The cell structure is shown in Fig. 1. After
the device’s figure of merits (FOM).
dicing and packaging, five species of devices named DUT
Keywords—SiC MOSFET, avalanche reliability, UIS, FOM A~E are studied in this work. The only difference between
the DUTs is the variation of JFET region width (WJFET)
I. INTRODUCTION which ranges from 2μm to 5μm.

Silicon carbide (SiC) MOSFET features fast switching Source

ILD
speed, low power loss and high working temperature [1]. In Gate
Gate Oxide
recent years, the third generations of SiC MOSFET products N+ N+
P+ P+
have become available in the market. Compared with formal P well
JFET Region
P well
generations, the cell pitch of the third-generation planar-gate Width DUT A:WJFET=2μm
DUT B:WJFET=2.5μm
SiC MOSFET is significantly narrowed via optimized (WJFET) DUT C:WJFET=3μm
N- dirft DUT D:WJFET=4μm
design of JFET region and drift layer [2]. By shrinking the DUT E:WJFET=5μm
cell pitch and reducing the device resistance, the device N+ Substrate
Drain
power density is enhanced, and simultaneously the Fig. 1. The cell structure of fabricated 1200V/2A SiC planar-gate
production cost is reduced [3]. MOSFET studied in this work.
According to the market report [4], the most promising The UIS test circuit, with 50V bus voltage and 1mH
application for SiC MOSFET is with electric vehicles (EV). /0.5mH inductor, is set up as show in Fig. 2. To control the
As a critical obstacle towards application, the reliability circuit and protect the DUT simultaneously, a switching
issues of SiC MOSFET receive much attention. Compared MOSFET, whose blocking voltage is higher than that of
with SiC trench-gate MOSFET, SiC planar-gate MOSFET DUT, is paralleled to the DUT. During the test, the gate and
can achieve higher robustness as the gate oxide is shielded source terminal of the DUT are shorted. The UIS test is
from the high electric field by the underneath P-well regions processed by gradually increasing the inductor current until
in blocking state [5,6]. The electric field shielding effect is the failure. To increase the inductor current in small step, the
greatly enhanced when the distance between the two pulse width of the single pulse gate signal is modulated in
adjacent P well regions (usually named as JFET region microsecond scale.
width) is reduced. However, this can aggravate the
conduction performance of SiC MOSFET as the narrow
JFET region contributes a large proportion of device
L
resistance in conduction mode [7]. In a word, the design of Switching
JFET region influences both the device’s characteristic and MOSFET DUT
C
reliability. Therefore, the width of JFET region is generally VDD
recognized as an important structure parameter. Several
works have focused on the influence of JFET region design
Vsignal
on device resistance or short-circuit reliability [8,9].
However, the influence of JFET region design on device’s
avalanche reliability is seldom studied. Fig. 2. UIS test circuit.

In this work, the influence of JFET region width in SiC III. EXPERIMENTAL RESULTS OF UIS TEST
MOSFET on avalanche reliability is discussed. First, UIS
test is carried out to examine the avalanche reliability of the Each DUT is stressed till failure. Fig. 3(a) shows the
DUTs. Then, the failure mechanism is analysed through typical drain current wavform and drain-source voltage

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waveform when the device (DUT D) survives from the simulation results presented in this work are extracted at the
largest avalanche current of 10.18A before breakdown. And same time instant after the DUTs enter the avalanche mode.
as shown in Fig. 3(b), the device fails when the avalanche
The distribution of electric field in DUTs is shown in Fig.
current increases to 10.20A.
5, and the distribution of electric field at cutline Y=0.9μm in
12 Fig. 5 is shown in Fig. 6(a). Extracted from Fig. 6(a), the
IAV=10.18A maximum electric field at the corner of P-well region is
2000

Drain-source voltage (V)

10 compared in Fig. 6(b). As shown in Fig. 6(b), the electric
Drain-source
Drain current (A)

8
1500 field at the corner of P-well region is the lowest at
voltage
WJFET=4um. When WJFET<4μm, the narrow JFET region
6 1000 width leads to a higher electric field at the corner of P-well
4 region. And when WJFET>4μm, the electric field at the
500
Drain current
corner of P-well region increases since the P-well regions in
2
0
two adjacent cells are separated wide apart from each other.
0
Meanwhile, the wide JFET region width weakens the
-500 shielding effect on channel. As shown in Fig.6(c), this leads
-2 0 2 4 6 8 10 to a low channel barrier and thus potential of channel
Time (µs) opening in DUT E.
(a)
12 -0.5 -0.5 -0.5
IAV=10.20A
2000
Drain-source voltage (V)

Cutline Y=0.002μm
0 0 0
10 0.5 0.5 0.5
Drain-source
Drain current (A)

Cutline Y=0.9μm
1500
8 voltage
1 1 1

1.5
A 1.5
B 1.5
C
6 1000
0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5
Avalanche -0.5 -0.5
4 faliure 500 0 0

Drain current
2 0.5 0.5

0 1 1

0 1.5 D 1.5 E
-500
-2 0 2 4 6 8 10 0 1 2 3 4 5 6 0 1 2 3 4 5 6

Time (µs) Fig. 5. The distribution of electric field in DUTs with varied WJFET
(b) (L=0.5mH).
Fig. 3. (a) Measured waveform (DUT D) in UIS test with avalanche
current of 10.18A before the DUT breakdown. (b) Measured waveform
Electric field (SiC) (MV·cm )

4.0 4.0
-1

W JFET=2µ m W JFET=4µ m L=0.5m H Minimum E

(DUT D) in UIS test when the DUT fails with avalanche current of
Electric field (MV·cm )
-1

W JFET=2.5µ m W JFET= 5µ m L=1m H

@W JFET=4µm
W JFET=3µ m
10.20A. 3.5
3.5

3.0
The maximum avalanche energy and avalanche current 3.0
without failure (i.e., avalanche energy capability and 2.5
L=0.5mH
avalanche current capability) for each DUT is summarized 2.0 2.5
L=1mH
0 2 4 6
in Fig. 4. The measured data illustrates that when
2 3 4 5
X (µ m) JFET width (µm)
WJFET=4μm, the device reaches the highest avalanche (a) (b)
energy capability and avalanche current capability at the
Conduction band energy (eV)

3
L=0.5mH W JFET=2µm
same time. L=1mH W JFET=2.5µm
W JFET=3µm
2
W JFET=4µm
Avalanche energy capability (mJ)

Avalanche current capability (A)

W JFET=5µm
60
1
14
55

50 12 0

45
10 -1
40 -0.5 0.0 0.5 1.0 1.5
Distance from the border of channel
L=0.5mH 8 L=0.5mH and JFET region on X-axis (µm)
35
L=1mH L=1mH
30 6
(c)
2 3 4
JFET width (µm)
5 2 3
JFET width (µm)
4 5
Fig. 6. (a) The distribution of electric field at cutline Y=0.9μm in Fig. 5.
(b) The maximum electric field at the corner of P-well region in DUTs.
(a) (b) (c) The distribution of conduction band energy at cutline Y=0.002μm.
Fig. 4. (a) The avalanche energy capability with varied WJFET. (b) The
avalanche current capability with varied WJFET. The distribution of avalanche current in DUTs is shown
in Fig. 7(a). Zoomed in from Fig. 7(a), the distribution of
current in channel region is shown in Fig. 7(b). The
IV. SIMULATION AND ANALYSIS ON FAILURE MECHANISM distribution of current at cutline Y=0.002μm in Fig. 7(b) is
TCAD Simulation is used for further investigation on shown in Fig. 8(a). Extracted from Fig. 8(a), the maximum
failure mechanism. The simulation is processed in mix- current density in channel region is compared in Fig. 8(b).
mode with identical DUT structure and test circuit setup As shown in Fig. 8(b), when L=1mH, the high-density
shown in Fig. 1 and Fig. 2, respectively. And all the channel current only occurs in the channel of DUT E
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because of its low channel barrier. And When L=0.5mH, the flowing in from the drift layer to the P-well region. Under
avalanche current in DUT A and DUT B becomes much such a high temperature, the channel turns on. Since the
higher than that in DUT C and DUT D, indicating that the channel conducts current in unipolar mode, the channel
channel is prone to open in DUT A and DUT B when current and channel temperature is coupled with positive
avalanche current increases. feedback. This induces a further temperature increase in
-0.5 -0.5 -0.5 channel which triggers a thermal runaway and finally leads
0
Channel region

0 0
to the device failure.
0.5 0.5 0.5
As a conclusion, when WJFET=4μm, the device meets the
1 1 1
lowest electric field, the lowest channel current density and
1.5
A 1.5
B 1.5
C the lowest channel temperature at the same time. Therefore,
0 1 2 3 4 5 0 1 2 3 4 5
DUT D presents the best avalanche capability.
0 1 2 3 4 5
-0.5 -0.5
-0.5 -0.5 -0.5
0 0
Cutline Y=0.002μm
0 0 0
0.5 0.5
0.5 0.5 0.5
1 1
1

D
1 1
1.5 1.5 E 1.5
A 1.5
B 1.5
C
0 1 2 3 4 5 6 0 1 2 3 4 5 6 5
0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4

(a) -0.5 -0.5

0 0
-0.04 -0.04 -0.04
0.5 0.5
-0.02 -0.02 -0.02
1 1
0
Cutline Y=0.002μm
0

0.02
0

0.02
1.5 D 1.5 E
0.02

0.04 A 0.04 B 0.04 C 0 1 2 3 4 5 6 0 1 2 3 4 5 6

0.5 1 1.5 2 1 1.5 2 2.5 1 1.5 2 2.5 Fig. 9. The distribution of lattice temperature in DUTs with varied
-0.04 WJFET (L=0.5mH).
-0.04

-0.02 -0.02
1000 1000
L=0.5mH
lattice temperature (K)

lattice temperature (K)

0
0 950
950
L=1mH
0.02
0.02 900

0.04 D 0.04 E 850 W JFET=2µm 900 Minimum TCH

W JFET=2.5µm W JFET=4µm L= 0.5mH
650 @WJFET=4µm
1.5 2 2.5 3 1 1.5 3 3.5 650 W JFET=3µm W JFET=5µm L= 1mH

(b) 600 600

Fig. 7. (a) The distribution of avalanche current in DUTs with varied

550 550
WJFET (L=0.5mH). (b) The distribution of current in channel (zoomed in 0 1 2 3 4 2 3 4 5
X (µ m) JFET width (µm)
from (a)).
(a) (b)
35000
W JFET=2µm L=0.5mH
35000
L=0.5mH Maximum J Fig. 10. (a) The distribution of lattice temperature at cutline
current density (A·cm )

current density (A·cm-2)

Y=0.002μm in Fig. 9. (b) The maximum channel temperature (TCH) in

-2

30000 W JFET=2.5µ m L=1mH 30000 L=1mH @WJFET=5µm

W JFET=3µm
25000 W JFET=4µm 25000 Rapid increasing J DUTs.
20000
W JFET=5µm
@WJFET=2µm/2.5µm
20000
15000
15000
10000

5000 10000

0 5000
0 1 2 3 4 2 3 4 5
X (µm) JFET width (µm)

(a) (b)
Fig. 8. (a) The distribution of avalanche current at cutline Y=0.002μm
in Fig. 7(b). (b) The maximum current in channel region in DUTs.
(a)
To explain the reason of channel opening in DUTs, the Temperatre rises and channel turns
distribution of lattice temperature in DUTs are compared in on, inducing thermal runaway
Fig. 9(a) and Fig. 9(b). As shown in Fig. 9(b), the narrower
WJFET of DUT A and DUT B leads to a higher JFET
resistance and thus a higher lattice temperature. Under such
N+
a high temperature, the threshold voltage drops far below P+
than that at room temperature [10]. Therefore, the channel is P well
prone to open in DUT A and DUT B in which the lattice High density channel
temperature is higher. current at high TJ
When DUTs fail in the experimental UIS test, they are all N- dirft
found three-terminal-shorted. Each DUT failed in test is Avalanche
decapsuled to recognize the location of failure point. In all current
decapsuled devices, the failure point emerges in the activa
area (See Fig. 11(a)). The failure mechanism is illustrated in (b)
Fig. 11(b). When the device is in avalanche mode, the Fig. 11. (a) The decapsulation image of a failed DUT. (b) The failure
mechanism of DUT’s breakdown in UIS test.
junction temperature rises from the high avalanche current
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 V. BALANCE BETWEEN PERFORMANCE AND RELIABILITY heat accumulation arising from high channel current density.
The output characteristic, blocking characteristic and The highest avalanche capability is achieved with a JFET
gate-drain charge of fresh DUTs are measured with region width of 4μm. And a feasible range of JFET region
B1505A. From the measured curves, the specific resistance, width (2.5μm to 3μm) is deduced by taking both the DUTs’
blocking voltage and gate-drain charge of each DUT are performance and reliability into account.
extracted in Fig. 12(a), Fig. 12(b) and Fig. 12(c).
0.5
0.38

BFOM (kV ·mO ·cm )

0.4

HF-FOM (O-1·nC-1)
-2
0.36
Specific On-resistance (mO·cm )
2

0.3

-1
10.0 1900
0.34
Blocking Voltage (V)

0.2

2
9.5 1800
0.32
0.1
9.0 1700 0.30
0.0
2 3 4 5 2 3 4 5
8.5 1600 JFET width (µm) JFET width (µm)

8.0 1500
(a) (b)
2 3 4 5 2 3 4 5

BFOM×EAV (kV2·mJ·mO -1·cm-2)

JFET width (µm) JFET width (µm) 0.020
0.021

HF-FOM×EAV(mJ·O-1·nC-1)
(a) (b) 0.015
0.018
-11.6% -20.7%
4.0 -47.5%
Gate-drain charge (nC)

0.010 -7.3%
3.5 0.015
-18.3%
3.0 0.005
0.012 L=0.5mH L=0.5mH -46.5%
2.5 L=1mH L=1mH
0.000
2 3 4 5 2 3 4 5
2.0 JFET width (µm) JFET width (µm)
1.5 (c) (d)
2 3 4 5 Fig. 13. (a) BFOM with varied JFET region width. (b) HF-FOM with
JFET width (µm)
varied JFET region width. (c) BFOM×EAV with varied JFET region
(c)
width. (d) HF-FOM×EAV with varied JFET region width.
Fig. 12. (a) The specific resistance at VGS=20V. (b) The blocking
voltage at VGS=-5V. (c)The gate-drain charge at VD=400V.
ACKNOWLEDGMENT
Aiming to characterize the performance of DUTs with
different designs, figure of merit (FOM) is utilized for This work was supported in part by the National Key
evaluation. In Fig. 13(a), Baliga’s figure of merit (BFOM = Research and Development Program of China under Grant
VB2/Ron,sp) is used to analyze the static performance of the 2016YFB0400504 and in part by the National Natural
DUTs. In Fig. 13(b), high-frequency figure of merit (HF- Science Foundation of China under Grant 52007165.
FOM=1/RON ×Qgd) is used to simultaneoulsy characterize
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