19-5646; Rev 0; 12/10

TION KIT
EVALUA BLE
AVA A
IL

HDCP Gigabit Multimedia Serial Link

Serializer with LVDS System Interface
General Description Features

MAX9265
The MAX9265 gigabit multimedia serial link (GMSL) S Pairs with Any GMSL Deserializer
serializer features an LVDS system interface and S HDCP Encryption Enable/Disable Programmable
high-bandwidth digital content protection (HDCP) with the Control Channel
encryption for content protection of DVD and Blu-ray™
S Control Channel Handles All HDCP Protocol
video and audio data. The serializer pairs with any HDCP
GMSL deserializer to form a digital serial link for the Transactions—Separate Control Bus Not Required
transmission of control data and HDCP-encrypted video S HDCP Keys Preprogrammed in Secure Nonvolatile
and audio data. GMSL is an HDCP technology approved Memory
by Digital Content Protection (DCP), LLC. S 2.5Gbps Payload Data Rate (3.125Gbps with
The 3-channel mode serializes three lanes of LVDS data Overhead)
(21 bits), UART control signals, and three audio inputs. S AC-Coupled Serial Link with 8b/10b Line Coding
The 4-channel mode serializes four lanes of LVDS data
S 8.33MHz to 104MHz (3-Channel LVDS) or 6.25MHz
(28 bits), UART control signals, three audio inputs, and
to 78MHz (4-Channel LVDS) Pixel Clock
auxiliary control inputs. The three audio inputs are for
I2S audio, supporting a sampling frequency from 8kHz S 4-Bit to 32-Bit Sample Depth, 8kHz to 192kHz I2S
to 192kHz and a sample depth of 4 to 32 bits. The Audio Channel Supports High-Definition Audio
embedded control channel forms a full-duplex differ- S Embedded Half-/Full-Duplex Bidirectional Control
ential 9.6kbps to 1Mbps UART link between the serial- Channel
izer and deserializer. An electronic control unit (ECU), Base Mode: 9.6kbps to 1Mbps
or microcontroller (FC), can be located on the serial- Bypass Mode: 9.6kbps to 1Mbps
izer side of the link (typical for video display), on the
S Two 3-Level Inputs Support 9 Slave Addresses
deserializer side of the link (typical for image sensing),
or on both sides. The control channel enables ECU/FC S Interrupt Supports Touch-Screen Displays
control of peripherals on the remote side, such as back- S Remote-End I2C Master for Peripherals
light control, touch screen, and perform HDCP-related
S Programmable Pre/Deemphasis
operations.
S Programmable Spread Spectrum on the Serial
The serial link signaling is AC-coupled CML with 8b/10b
Link and Deserializer Outputs Reduce EMI
coding. For driving longer cables, the serializer has
programmable driver pre/deemphasis, and for reduced S Auto Data-Rate Detection Allows “On-The-Fly”
EMI, has programmable spread spectrum on the serial Data-Rate Change
output. The serial output meets ISO 10605 and IEC S Bypassable PLL on LVDS Clock Input for Jitter
61000-4-2 ESD standards. Attenuation
The serializer operates with a 1.8V core supply, a 1.8V S Built-In PRBS Generator for BER Testing of the
to 3.3V I/O supply, and a 3.3V LVDS supply. This device Serial Link
is available in a 48-pin TQFP package with an exposed S Fault Detection of Serial Link Shorted Together, to
pad and is specified over the -40NC to +105NC automo- Ground, to Battery, or Open
tive temperature range.
S ISO 10605 and IEC 61000-4-2 ESD Tolerance
Applications
High-Resolution Automotive Navigation Ordering Information
Rear-Seat Infotainment
PART TEMP RANGE PIN-PACKAGE
Megapixel Camera Systems
MAX9265GCM/V+ -40NC to +105NC 48 TQFP-EP*
MAX9265GCM/V+T -40NC to +105NC 48 TQFP-EP*
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Blu-ray is a trademark of Blu-ray Disc Association. T = Tape and reel.

________________________________________________________________ Maxim Integrated Products   1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
ABSOLUTE MAXIMUM RATINGS
MAX9265

AVDD to AGND.....................................................-0.5V to +1.9V Junction-to-Case Thermal Resistance (BJC) (Note 1)

DVDD to GND.......................................................-0.5V to +1.9V 48-Lead TQFP..................................................................2NC/W
IOVDD to GND......................................................-0.5V to +3.9V Junction-to-Ambient Thermal Resistance (BJA) (Note 1)
LVDSVDD to AGND...............................................-0.5V to +3.9V 48-Lead TQFP.............................................................27.6NC/W
Any Ground to Any Ground..................................-0.5V to +0.5V Operating Temperature Range......................... -40NC to +105NC
RXIN__, RXCLKIN_ to AGND................................-0.5V to +3.9V Junction Temperature......................................................+150NC
OUT+, OUT- to AGND..........................................-0.5V to +1.9V Storage Temperature Range............................. -65NC to +150NC
LMN_ to AGND (15mA current limit).....................-0.5V to +3.9V Lead Temperature (soldering, 10s).................................+300NC
All Other Pins to GND.........................-0.5V to (VIOVDD + 0.5V) Soldering Temperature (reflow).......................................+260NC
Continuous Power Dissipation (TA = +70NC )
48-Lead TQFP (derate 36.2mW/NC above +70NC)...2898.6mW
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = 1.7V to 1.9V, VLVDSVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to
+105NC, unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V -
|VID/2|. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SINGLE-ENDED INPUTS (SD/CNTL0, SCK, WS, CNTL1, CNTL2, SSEN, DRS, BWS, PWDN , CDS, MS, AUTOS)
PWDN, SSEN, BWS, DRS, MS, CDS, 0.65 x
AUTOS VIOVDD
High-Level Input Voltage VIH1 V
0.7 x
SD/CNTL0, SCK, WS, CNTL_
VIOVDD
0.35 x
Low-Level Input Voltage VIL1 V
VIOVDD

Input Current IIN1 VIN = 0 to VIOVDD -10 +10 FA

Input Clamp Voltage VCL ICL = -18mA -1.5 V

SINGLE-ENDED OUTPUT (INT)
VIOVDD
High-Level Output Voltage VOH1 IOUT = -2mA V
- 0.2
Low-Level Output Voltage VOL1 IOUT = 2mA 0.2 V
VIOVDD = 3.0V to 3.6V 16 35 64
Output Short-Circuit Current IOS VO = VGND mA
VIOVDD = 1.7V to 1.9V 3 12 21
I2C/UART, I/O, AND OPEN-DRAIN OUTPUTS (RX/SDA, TX/SCL, LFLT)
0.7 x
High-Level Input Voltage VIH2 V
VIOVDD
0.3 x
Low-Level Input Voltage VIL2 V
VIOVDD
Input Current IIN2 VIN = 0 to VIOVDD (Note 2) -110 +5 FA
VIOVDD = 1.7V to 1.9V 0.4
Low-Level Output Voltage VOL2 IOUT = 3mA V
VIOVDD = 3.0V to 3.6V 0.3

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DC ELECTRICAL CHARACTERISTICS (continued)

MAX9265
(VAVDD = VDVDD = 1.7V to 1.9V, VLVDSVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to
+105NC, unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V -
|VID/2|. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIFFERENTIAL OUTPUTS (OUT+, OUT-)
Preemphasis off (Figure 1) 300 400 500
Differential Output Voltage VOD 3.3dB preemphasis setting (Figure 2) 350 610 mV
3.3dB deemphasis setting (Figure 2) 240 425
Change in VOD Between
DVOD 15 mV
Complementary Output States
Output Offset Voltage
VOS Preemphasis off 1.1 1.4 1.56 V
(VOUT+ + VOUT-)/2 = VOS
Change in VOS Between
DVOS 15 mV
Complementary Output States
VOUT+ or VOUT- = 0V -60
Output Short-Circuit Current IOS mA
VOUT+ or VOUT- = 1.9V 25
Magnitude of Differential Output
IOSD VOD = 0V 25 mA
Short-Circuit Current
Output Termination Resistance
RO From OUT+, OUT- to VAVDD 45 54 63 I
(Internal)
REVERSE CONTROL-CHANNEL RECEIVER (OUT+, OUT-)
High Switching Threshold VCHR 27 mV
Low Switching Threshold VCLR -27 mV
LINE-FAULT-DETECTION INPUTS (LMN0, LMN1)
Short-to-GND Threshold VTG Figure 3 0.3 V
Normal Thresholds VTN Figure 3 0.57 1.07 V
VIO +
Open Thresholds VTO Figure 3 1.45 V
60mV
Open Input Voltage VIO Figure 3 1.47 1.75 V
Short-to-Battery Threshold VTE Figure 3 2.47 V
THREE-LEVEL LOGIC INPUTS (ADD0, ADD1)
0.7 x
High-Level Input Voltage VIH V
VIOVDD
0.3 x
Low-Level Input Voltage VIL V
VIOVDD
Unconnected or connected to a driver with
Mid-Level Input Current IINM -10 +10 FA
output in high-impedance state (Note 3)
Input Current IIN -150 +150 FA
Input Clamp Voltage VCL ICL = -18mA -1.5 V

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 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
DC ELECTRICAL CHARACTERISTICS (continued)
MAX9265

(VAVDD = VDVDD = 1.7V to 1.9V, VLVDSVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to
+105NC, unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V -
|VID/2|. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LVDS INPUTS (RXIN_+/-, RXCLKIN_)
Differential Input High Threshold VTH 50 mV
Differential Input Low Threshold VTL -50 mV
Input Differential Termination
RTERM 85 110 135 I
Resistance
PWDN = high or low, IN+ and IN- are
Input Current IIN+, IIN- -25 +25 FA
shorted
Power-Off Input Current IIN0+, IIN0- VAVDD = VDVDD = VIOVDD = 0V -40 +40 FA
POWER SUPPLY
fRXCLKIN_ = 16.6MHz 137 178
Worst-Case Supply Current HDCP enabled, fRXCLKIN_ = 33.3MHz 146 186
IWCS mA
(Figure 4) BWS = low fRXCLKIN_ = 66.6MHz 166 206
fRXCLKIN_ = 104MHz 195 242
Sleep Mode Supply Current ICCS LVDS inputs are not driven 95 225 FA
Power-Down Supply Current ICCZ PWDN = GND, LVDS inputs are not driven 60 180 FA
ESD PROTECTION
Human Body Model, RD = 1.5kI,
Q8
CS = 100pF (Note 4)
IEC 61000-4-2, Contact discharge Q10
RD = 330I,
CS = 150pF Air discharge Q12
OUT+, OUT- VESD kV
(Note 5)
ISO 10605, Contact discharge Q10
RD = 2kI,
CS = 330pF Air discharge Q20
(Note 5)
RXIN_+, RXIN_-, RXCLKIN+, Human Body Model, RD = 1.5kI,
VESD Q8 kV
RXCLKIN- CS = 100pF (Note 4)
Human Body Model, RD = 1.5kI,
All Other Pins VESD Q3.5 kV
CS = 100pF (Note 4)

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AC ELECTRICAL CHARACTERISTICS

MAX9265
(VDVDD = VAVDD = 1.7V to 1.9V, VLVDSVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to
+105NC, unless otherwise noted. Differential input voltage |VID| = 0.15V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V
- |VID/2|. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CLOCK INPUTS (RXCLKIN_)
BWS = GND, VDRS = VIOVDD 8.33 16.66
BWS = GND, DRS = GND 16.66 104
Clock Frequency fRXCLKIN_ MHz
VBWS = VIOVDD, VDRS = VIOVDD 6.25 12.5
VBWS = VIOVDD, DRS = GND 12.5 78
I2C/UART PORT TIMING
I2C/UART Bit Rate 9.6 1000 kbps
30% to 70%, CL = 10pF to 100pF,
Output Rise Time tR 20 150 ns
1kI pullup to VIOVDD
70% to 30%, CL = 10pF to 100pF,
Output Fall Time tF 20 150 ns
1kI pullup to VIOVDD
Input Setup Time tSET I2C only (Figure 5, Note 6) 100 ns
Input Hold Time tHOLD I2C only (Figure 5, Note 6) 0 ns
SWITCHING CHARACTERISTICS
20% to 80%, VOD R 400mV, RL = 100I,
Differential Output Rise/Fall Time tR, tF 90 150 ps
serial bit rate = 3.125Gbps (Note 6)
3.125Gbps PRBS signal, measured at VOD
Total Serial Output Jitter tTSOJ1 = 0V differential, preemphasis disabled 0.25 UI
(Figure 6)
Deterministic Serial Output Jitter tDSOJ2 3.125Gbps PRBS signal 0.15 UI
CNTL_ Input Setup Time tSET CNTL_ (Figure 7) (Note 6) 3 ns
CNTL_ Input Hold Time tHOLD CNTL_ (Figure 7) (Note 6) 1.5 ns
RXIN__ Skew Margin tRSKM Figure 8 (Note 6) 0.3 UI
Spread spectrum enabled 2950
Serializer Delay (Notes 6, 7) tSD (Figure 9) Bits
Spread spectrum disabled 550
Link Start Time tLOCK (Figure 10) 3.5 ms
Power-Up Time tPU (Figure 11) 6 ms
I2S INPUT TIMING
WS Frequency fWS See Table 4 8 192 kHz
Sample Word Length nWS See Table 4 4 32 Bits
(8 x (192 x
SCK Frequency fSCK fSCK = fWS x nWS x 2 kHz
4) x 2 32) x 2

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 HDCP Gigabit Multimedia Serial Link
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AC ELECTRICAL CHARACTERISTICS (continued)
MAX9265

(VDVDD = VAVDD = 1.7V to 1.9V, VLVDSVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to
+105NC, unless otherwise noted. Differential input voltage |VID| = 0.15V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V
- |VID/2|. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
0.35
SCK Clock High Time tHC VSCK R VIH, tSCK = 1/fSCK (Note 6) ns
tSCK
0.35
SCK Clock Low Time tLC VSCK P VIL, tSCK = 1/fSCK (Note 6) ns
tSCK
SD, WS Setup Time tSET (Figure 12, Note 6) 2 ns
SD, WS Hold Time tHOLD (Figure 12, Note 6) 2 ns
Note 2: Minimum IIN due to voltage drop across the internal pullup resistor.
Note 3: To provide a mid level, leave the input unconnected, or, if driven, put driver in high impedance. High-impedance leakage
current must be less than Q10FA.
Note 4: Tested terminal to all grounds.
Note 5: Tested terminal to AGND.
Note 6: Guaranteed by design and not production tested.
Note 7: Measured in CML bit times. Bit time = 1/(30 x fRXCLKIN) for BWS = GND. Bit time = 1/(40 x fRXCLKIN) for VBWS = VIOVDD.

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Typical Operating Characteristics

MAX9265
(VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. SUPPLY CURRENT vs. OUTPUT POWER SPECTRUM vs.
RXCLKIN_ FREQUENCY (24-BIT MODE) RXCLKIN_ FREQUENCY (32-BIT MODE) RXCLKIN_ FREQUENCY (VARIOUS SPREAD)
200 200 0

MAX9265 toc02

MAX9265 toc03
MAX9265 toc01
PRBS ON, HDCP ON PRBS ON, HDCP ON fRXCLKIN = 33MHz
-10
190 190

OUTPUT POWER SPECTRUM (dBm)

PREEMPHASIS = PREEMPHASIS = -20 0.5% SPREAD
0% SPREAD
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)

180 0x0B TO 0x0F 180 0x0B TO 0x0F

-30
170 170 -40

160 160 -50

-60
150 PREEMPHASIS = 150 PREEMPHASIS =
0x01 TO 0x04 0x01 TO 0x04 -70
140 140 PREEMPHASIS = 0x00
-80
PREEMPHASIS = 0x00 2% SPREAD 4% SPREAD
130 130 -90
5 25 45 65 85 105 5 20 35 50 65 80 30 31 32 33 34 35 36
RXCLKIN FREQUENCY (MHz) RXCLKIN FREQUENCY (MHz) RXCLKIN FREQUENCY (MHz)

MAXIMUM RXCLKIN_ FREQUENCY

OUTPUT POWER SPECTRUM vs. MAXIMUM RXCLKIN_ FREQUENCY vs. ADDITIONAL DIFFERENTIAL
RXCLKIN_ FREQUENCY (VARIOUS SPREAD) vs. STP CABLE LENGTH (BER < 10-9) CL (BER < 10-9)
0 120 120
MAX9265 toc05

MAX9265 toc06
MAX9265 toc04

fRXCLKIN = 66MHz
10m STP CABLE
MAXIMUM RXCLKIN_ FREQUENCY (MHz)

MAXIMUM RXCLKIN_ FREQUENCY (MHz)

-10
OUTPUT POWER SPECTRUM (dBm)

100 100
-20 0% SPREAD 0.5% SPREAD
OPTIMUM OPTIMUM
-30 80 80
PE/EQ SETTINGS PE/EQ SETTINGS
-40 NO PE, 10.7dB
60 60
-50 EQUALIZATION
NO PE, 10.7dB
-60 40 NO PE, 5.2dB 40 EQUALIZATION
EQUALIZATION
-70 NO PE, 5.2dB EQUALIZATION
20 BER CAN BE AS LOW AS 10-12 FOR 20
-80 BER CAN BE AS LOW AS 10-12 FOR CL < 4pF
CABLE LENGTHS LESS THAN 10m
2% SPREAD 4% SPREAD FOR OPTIMUM PE/EQ SETTINGS
-90 0 0
61 63 65 67 69 71 0 5 10 15 20 0 2 4 6 8 10
RXCLKIN FREQUENCY (MHz) STP CABLE LENGTH (m) ADDITIONAL DIFFERENTIAL LOAD CAPACITANCE (pF)

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 HDCP Gigabit Multimedia Serial Link
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Pin Configuration
MAX9265

TOP VIEW

RX/SDA
TX/SCL
AGND
LMN0

LMN1
AVDD
OUT+

SSEN
OUT-
LFLT
DRS
INT
36 35 34 33 32 31 30 29 28 27 26 25

IOVDD 37 24 IOVDD

GND 38 23 GND

DVDD 39 22 DVDD

ADD0 40 21 AGND

BWS 41 20 CNTL2
PWDN 42 19 CNTL1
CDS 43 MAX9265 18 WS
MS 44 17 SCK
AUTOS 45 16 SD/CNTL0
ADD1 46 15 AVDD
*EP
AVDD 47 14 LVDSVDD
AGND 48 + 13 AGND

1 2 3 4 5 6 7 8 9 10 11 12
RXIN0-
RXIN0+
RXIN1-
RXIN1+

LVDSVDD
AGND
RXIN2-

RXIN2+

RXCLKIN-

RXCLKIN+

RXIN3-

RXIN3+

TQFP
*CONNECT EXPOSED PAD TO AGND

Pin Description
PIN NAME FUNCTION
1 RXIN0- Differential LVDS Data Input 0-
2 RXIN0+ Differential LVDS Data Input 0+
3 RXIN1- Differential LVDS Data Input 1-
4 RXIN1+ Differential LVDS Data Input 1+
3.3V LVDS Power Supply. Bypass LVDSVDD to AGND with 0.1FF and 0.001FF capacitors as close as
5, 14 LVDSVDD
possible to the device with the smaller value capacitor closest to LVDSVDD.
6, 13, 21,
AGND Analog Ground
29, 48
7 RXIN2- Differential LVDS Data Input 2-
8 RXIN2+ Differential LVDS Data Input 2+
RXCLKIN-,
9, 10 LVDS Input for the LVDS Clock
RXCLKIN+
Differential LVDS Data Input 3-. RXIN3- is not available in 3-channel mode. To use RXIN3-, drive BWS
11 RXIN3-
high (4-channel mode) (see Table 3).

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 HDCP Gigabit Multimedia Serial Link
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Pin Description (continued)

MAX9265
PIN NAME FUNCTION
Differential LVDS Data Input 3+. RXIN3+ is not available in 3-channel mode. To use RXIN3+, drive
12 RXIN3+
BWS high (4-channel mode) (see Table 3).
1.8V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as close as
15, 32, 47 AVDD
possible to the device with the smaller capacitor closest to AVDD.
I2S Serial-Data Input with Internal Pulldown to GND. Disable I2S to use SD/CNTL0 as an additional
16 SD/CNTL0
control/data input latched every RXCLKIN_ cycle (Figure 7). Encrypted when HDCP is enabled.
17 SCK I2S Serial-Clock Input with Internal Pulldown to GND
18 WS I2S Word-Select Input with Internal Pulldown to GND
Control Input 1 with Internal Pulldown to GND. Data is latched every RXCLKIN cycle (Figure 7).
CNTL1 is not available in 3-channel mode. To use CNTL1, drive BWS high (4-channel mode).
19 CNTL1
CNTL1 or RES (RES from VESA Standard Panel Specification) is mapped to DIN27 (see the
Reserved Bit (RES) section). CNTL1 is not encrypted when HDCP is enabled (see Table 3).

Control Input 2 with Internal Pulldown to GND. Data is latched every RXCLKIN cycle (Figure 7).
20 CNTL2 CNTL2 is not available in 3-channel mode. To use CNTL2, drive BWS high (4-channel mode).
CNTL2 is mapped to DIN28. CNTL2 is not encrypted when HDCP is enabled (see Table 3).
1.8V Digital Power Supply. Bypass DVDD to GND with 0.1FF and 0.001FF capacitors as close as
22, 39 DVDD
possible to the device with the smaller value capacitor closest to DVDD.
23, 38 GND Digital and I/O Ground
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to GND with 0.1FF and
24, 37 IOVDD 0.001FF capacitors as close as possible to the device with the smallest value capacitor closest to
IOVDD.

Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI pullup to IOVDD.
In UART mode, RX/SDA is the Rx input of the serializer’s UART. In the I2C mode, RX/SDA is the SDA
25 RX/SDA
input/output of the MAX9265’s I2C master. RX/SDA has an open-drain driver and requires a pullup
resistor.

Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI pullup to IOVDD.
26 TX/SCL In UART mode, TX/SCL is the Tx output of the MAX9265’s UART. In the I2C mode, TX/SCL is the SCL
output of the serializer’s I2C master. TX/SCL has an open-drain driver and requires a pullup resistor.

Spread-Spectrum Enable. Serial link spread-spectrum enable input requires external pulldown or
pullup resistor. The state of SSEN latches upon power-up or when resuming from power-down mode
27 SSEN
(PWDN = low). Set SSEN = high for Q0.5% spread spectrum on the serial link. Set SSEN = low to use
the serial link without spread spectrum.
28 LMN1 Line-Fault Monitor Input 1 (See Figure 3 for Details)
OUT-,
30, 31 Differential CML Output -/+. Differential outputs of the serial link.
OUT+
33 LMN0 Line-Fault Monitor Input 0 (See Figure 3 for Details)
Line Fault. Active-low open-drain line-fault output. LFLT has a 60kI internal pullup resistor.
34 LFLT
LFLT = low indicates a line fault. LFLT is high impedance when PWDN = low.
Interrupt Output. INT indicates remote-side requests. INT = low upon power-up and when PWDN =
35 INT
low. A transition on the INT input of the GMSL deserializer toggles the MAX9265’s INT output.

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 HDCP Gigabit Multimedia Serial Link
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Pin Description (continued)
MAX9265

PIN NAME FUNCTION

Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup resistor. The
state of DRS latches upon power-up or when resuming from power-down mode (PWDN = low).
36 DRS Set DRS = high for RXCLKIN frequencies of 8.33MHz to 16.66MHz (3-channel mode) or 6.25MHz
to 12.5MHz (4-channel mode). Set DRS = low for RXCLKIN frequencies of 16.66MHz to 104MHz
(3-channel mode) or 12.5MHz to 78MHz (4-channel mode).

Address Selection Input 0. Three-level input to select the MAX9265’s device address (see Table 2).
40 ADD0
The state of ADD0 latches upon power-up or when resuming from power-down mode (PWDN = low).
Bus-Width Select Input. BWS requires external pulldown or pullup resistor. Set BWS = low for
41 BWS
3-channel mode. Set BWS = high for 4-channel mode.
42 PWDN Active-Low Power-Down Input. PWDN requires external pulldown or pullup resistor.
Control Direction Selection. Control link direction selection input requires external pulldown or pullup
43 CDS resistor. Set CDS = low for FC use on the MAX9265 side of the serial link. Set CDS = high for FC use
on the GMSL deserializer side of the serial link.
Mode Select. Control link mode selection input requires external pulldown or pullup resistor. Set
44 MS
MS = low to select base mode. Set MS = high to select bypass mode.
Active-Low Autostart Setting. AUTOS requires external pulldown or pullup resistor. Set AUTOS = high
45 AUTOS to power up the device with no link active. Set AUTOS = low to have the serializer power up the serial
link with autorange detection (see Tables 9 and 10).
Address Selection Input 1. Three-level input to select the serializer’s device address (see Table 2).
46 ADD1
The state of ADD1 latches upon power-up or when resuming from power-down mode (PWDN = low).
Exposed Pad. EP internally is connected to AGND. MUST connect EP to the AGND plane for proper
— EP
thermal and electrical performance.

10   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Functional Diagram

MAX9265
LFLT

RXCLKIN+/- FILTER
SSPLL
PLL
LMN0
LINE
7x PLL FAULT
CLKDIV LMN1
DETECT

RGB[17:0] RGB HDCP

RXIN0+/- ENCRYPT OUT+
PARALLEL
HS HS
TO
VS VS SERIAL OUT-
RXIN1+/- VIDEO
LVDS TO DE DE
PARALLEL
CML Tx
RGB[23:18] SCRAMBLE/
RXIN2+/- HDCP HDCP PARITY/
(4-CH)
KEYS CONTROL 8b/10b
RES/CNTL1 ENCODE
CNTL1/RES (4-CH)
(4-CH) FIFO
RXIN3+/- CNTL2 (4-CH) Rx
(4-CH) REVERSE
CONTROL
CNTL1 ACB HDCP CHANNEL
(4-CH) AUDIO ENCRYPT

CNTL2 FCC
(4-CH) MAX9265

UART/I2C

SD/ WS SCK TX/SCL RX/SDA ADD0 ADD1

CNTLO

RL/2
OUT+

VOD

VOS
OUT-
RL/2

GND

((OUT+) + (OUT-))/2
OUT-
VOS(-) VOS(+) VOS(-)

OUT+

DVOS = |VOS(+) - VOS(-)|

VOD(+)
VOD = 0V

VOD(-) DVOD = |VOD(+) - VOD(-)| VOD(-)

(OUT+) - (OUT-)

Figure 1. Serial-Output Parameters

______________________________________________________________________________________   11
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
MAX9265

OUT+

VOS VOD(P) VOD(D)

OUT-

SERIAL-BIT
TIME

Figure 2. Output Waveforms at OUT+, OUT-

1.7V TO 1.9V

MAX9265 45kI* 45kI*

LMN0

LMN1

OUTPUT 5kI* 5kI*

LOGIC
(OUT+)
TWISTED PAIR
OUT+

OUT-

50kI* 50kI*
CONNECTORS
LFLT REFERENCE
VOLTAGE
GENERATOR

OUTPUT
LOGIC
(OUT-)

*Q1% TOLERANCE

Figure 3. Line-Fault Detector Circuit

12   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface

MAX9265
RXCLKIN+

RXCLKIN-

RXIN0+ TO RXIN3+

RXIN0- TO RXIN3-

CNTL_

Figure 4. Worst-Case Pattern Input

tR tF

TX/
SCL

tHOLD tSET

RX/
SDA

P S S P

Figure 5. I2C Timing Parameters

RXCLKIN-

RXCLKIN+

800mVP-P

RXIN_+/RXIN_-

tSET tHOLD
VIHMIN
CNTL_
VILMAX

t TSOJ1 t TSOJ1
2 2

Figure 6. Differential Output Template Figure 7. Input Setup and Hold Times

______________________________________________________________________________________   13
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
MAX9265

IDEAL SERIAL-BIT TIME

tRSKM tRSKM

IDEAL
MIN MAX
INTERNAL STROBE

Figure 8. LVDS Receiver Input Skew Margin

EXPANDED TIME SCALE

N-1 N N+1 N+2 N+3

RXIN_+/RXIN_-

RXCLKIN+

RXCLKIN-

N-1 N

OUT+/OUT-

FIRST BIT LAST BIT

tSD

Figure 9. Serializer Delay

RXCLKIN-

RXCLKIN+

tLOCK

350µs

SERIAL LINK INACTIVE SERIAL LINK ACTIVE

REVERSE CONTROL CHANNEL REVERSE CONTROL

CHANNEL ENABLED DISABLED CHANNEL ENABLED

PWDN MUST BE HIGH

Figure 10. Link Startup Time

14   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface

MAX9265
RXCLKIN+

RXCLKIN-

PWDN VIH1

tPU

POWERED UP, SERIAL

POWERED DOWN POWERED UP, SERIAL LINK ACTIVE
LINK INACTIVE

350µs

REVERSE CONTROL REVERSE CONTROL REVERSE CONTROL REVERSE CONTROL

CHANNEL DISABLED CHANNEL ENABLED CHANNEL DISABLED CHANNEL ENABLED

Figure 11. Power-Up Delay

WS

tSCK
tHOLD tSET
tLC
SCK

tHOLD tSET tHC

SD/CNTL0

Figure 12. Input I2S Timing Parameters

______________________________________________________________________________________   15
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
MAX9265

Detailed Description mat. A bypass mode enables full-duplex communication

using a user-defined UART format.
The MAX9265 GMSL serializer with LVDS interface
utilizes Maxim’s GMSL technology and HDCP. When The serializer pre/deemphasis, along with the GMSL
HDCP is enabled, the serializer encrypts video and deserializer channel equalizer, extends the link length
audio data on the serial link. When HDCP is disabled, and enhances the link reliability. Spread spectrum is
the serializer is backward compatible with the MAX9249 available to reduce EMI on the serial output. The CML
LVDS input serializer. and LVDS connections comply with ISO 10605 and IEC
61000-4-2 ESD protection standards.
The serializer has a maximum serial payload data rate
of 2.5Gbps for 15m or more of shielded twisted-pair Register Mapping
(STP) cable. The serializer operates up to a maximum The FC configures various operating conditions of the
input clock of 104MHz for 3-channel mode, or 78MHz for serializer and the GMSL deserializer through internal
4-channel mode, respectively. This serial link supports a registers. Table 1 lists the default register values for the
wide range of display panels from QVGA (320 x 240) up serializer. The device addresses are stored in registers
to WXGA (1280 x 800) and higher with 24-bit color. 0x00 and 0x01 of both the serializer and the GMSL
The 3-channel mode handles three lanes of LVDS data deserializer. Write to registers 0x00 and 0x01 in both
(21 bits), UART control signals, and three audio signals. devices to change the device address of the serializer
The 4-channel mode handles four lanes of LVDS data or the GMSL deserializer.
(28 bits), UART control signals, three audio signals, and HDCP Bitmapping and Bus-Width Selection
auxiliary parallel inputs. The three audio inputs form a The LVDS input has two selectable modes, 3-channel
standard I2S interface, supporting sample rates from mode and 4-channel mode. In 3-channel mode, RXIN3_
8kHz to 192kHz and audio word lengths of 4 to 32 bits. is not used. For both modes, the SD/CNTL0, SCK, and
The embedded control channel forms a full-duplex, WS pins are for I2S audio. The serializer uses RXCLKIN
differential 9.6kbps to 1Mbps UART link between the rates from 8.33MHz to 104MHz for 3-channel mode and
serializer and deserializer for HDCP-related control 6.25MHz to 78MHz for 4-channel mode.
operations. In addition, the control channel enables
Table 3 lists the bit mapping for the LVDS input. The
electronic control unit (ECU) or microcontroller (FC) con-
serializer has HDCP encryption on 18 RGB input bits and
trol of peripherals in the remote side, such as backlight
the I2S input. Four-channel mode has additional HDCP
control, gray-scale Gamma correction, camera module,
encryption on the additional RGB bits.
and touch screen. An ECU/FC can be located on the
serializer side of the link (typical for video display), on The control signals (CNTL_) do not have HDCP encryp-
the GMSL deserializer side of the link (typical for image tion. SD/CNTL0, when used as an additional control input
sensing), or on both sides. Base-mode communication (AUDIOEN = 0), also does not have HDCP encryption.
with peripherals uses either I2C or the GMSL UART for-

16   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 1. Power-Up Default Register Map (see Table 17 and Table 18)

MAX9265
REGISTER POWER-UP
POWER-UP DEFAULT SETTINGS
ADDRESS DEFAULT
(MSB FIRST)
(hex) (hex)
0x40, 0x48, 0x48, SERID = XX00XX0, serializer device address is determined by ADD0 and ADD1
0x00 0x80, 0x84, 0x88, (Table 2)
0xC0, 0xC4, 0xC8 CFGBLOCK = 0, registers 0x00 to 0x1F are read/write
0x50, 0x58, 0x58, DESID = XX00XX0, deserializer device address is determined by ADD0 and
0x01 0x90, 0x94, 0x98, ADD1 (Table 2)
0xD0, 0xD4, 0xD8 RESERVED = 0

SS = 000 (SSEN = low), SS = 001 (SSEN = high), spread-spectrum settings

depend on SSEN pin state at power-up
0x02 0x1F, 0x3F AUDIOEN = 1, I2S channel enabled
PRNG = 11, automatically detect the pixel clock range
SRNG = 11, automatically detect serial-data rate

AUTOFM = 00, calibrate spread-modulation rate only once after locking

0x03 0x00
SDIV = 000000, autocalibrate the sawtooth divider

SEREN = 0 (AUTOS = high), SEREN = 1 (AUTOS = low), serial link enable

default depends on AUTOS pin state at power-up
CLINKEN = 0, configuration link disabled
PRBSEN = 0, PRBS test disabled
0x03, 0x13, 0x83, or
0x04 SLEEP = 0 or 1, sleep mode state depends on CDS and AUTOS pin state at
0x93
power-up (see the Link Startup Procedure section)
INTTYPE = 00, base mode uses I2C
REVCCEN = 1, reverse control channel active (receiving)
FWDCCEN = 1, forward control channel active (sending)

I2CMETHOD = 0, I2C packets include register address

DISFPLL = 1, filter PLL disabled
0x05 0x70
CMLLVL = 11, 400mV CML signal level
PREEMP = 0000, preemphasis disabled
0x06 0x40 RESERVED = 01000000
0x07 0x22 RESERVED = 00100010
RESERVED = 0000
0x0A
0x08 LFNEG = 10, no faults detected
(read only)
LFPOS = 10, no faults detected
0x0C 0x70 RESERVED = 01110000
SETINT = 0, interrupt output set to low
INVVSYNC = 0, serializer does not invert VSYNC
0x0D 0x0F INVHSYNC = 0, serializer does not invert HSYNC
DISRES = 0, RES mapped to DIN27
SKEWADJ = 1111, No X7PLL clock skew adjust

0x07
0x1E ID = 00000111, device ID is 0x07
(read only)

______________________________________________________________________________________   17
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 1. Power-Up Default Register Map (see Table 17 and Table 18) (continued)
MAX9265

REGISTER POWER-UP
POWER-UP DEFAULT SETTINGS
ADDRESS DEFAULT
(MSB FIRST)
(hex) (hex)
RESERVED = 000
0x1X
0x1F CAPS = 1, serializer is HDCP capable
(read only)
REVISION = XXXX, revision number
0x80 to 0x84 0x0000000000 BKSV = 0x0000000000, HDCP receiver KSV is 0x0000000000
0x85 to 0x86 0x0000 RI = 0x0000, RI of the transmitter is 0x0000
0x87 0x00 PJ = 0x00, PJ of the transmitter is 0x00
0x0000000000000000
0x88 to 0x8F AN = 0000000000000000, session random number (read only)
(read only)
0xXXXXXXXXXX AKSV = 0xXXXXXXXXXXXXXXXX, HDCP transmitter KSV is 0xXXXXXXXXXX
0x90 to 0x94
(read only) (read only)
PD_HDCP = 0, HDCP circuits powered up
EN_INT_COMP = 0, internal link verification disabled
FORCE_AUDIO = 0, normal I2S audio operation
FORCE_VIDEO = 0, normal video link operation
0x95 0x00
RESET_HDCP = 0, normal HDCP operation
START_AUTHENTICATION = 0, HDCP authentication not started
VSYNC_DET = 0, VSYNC rising edge not detected
ENCRYPTION_ENABLE = 0, HDCP encryption disabled

RESERVED = 0000
V_MATCHED = 0, SHA-1 hash value not matched
0x00
0x96 PJ_MATCHED = 0, enhanced link verification response not matched
(read only)
R0_RI_MATCHED = 0, link verification response not matched
BKSV_INVALID = 0, invalid receiver KSV

RESERVED = 0000000
0x97 0x00
REPEATER = 0, HDCP receiver is not a repeater
0x98 to 0x9C 0x0000000000 ASEED = 0x0000000000, optional RNG seed value is 0x0000000000
0x9D to 0x9F 0x000000 DFORCE = 0x000000, video data forced to 0x000000 when FORCE_VIDEO = 1
0xA0 to 0xA3 0x00000000 H0 part of SHA-1 hash value is 0x00000000
0xA4 to 0xA7 0x00000000 H1 part of SHA-1 hash value is 0x00000000
0xA8 to 0xAB 0x00000000 H2 part of SHA-1 hash value is 0x00000000
0xAC to 0xAF 0x00000000 H3 part of SHA-1 hash value is 0x00000000
0xB0 to 0xB3 0x00000000 H4 part of SHA-1 hash value is 0x00000000
Reserved = 0000
0xB4 0x00 MAX_CASCADE_EXCEEDED = 0, less than 7 cascaded HDCP devices attached
DEPTH = 000, device cascade depth is zero
MAX_DEVS_EXCEEDED = 0, less than 127 HDCP devices attached
0xB5 0x00
DEVICE_COUNT = 0000000, zero attached devices
0xB6 0x00 GPMEM = 00000000, 0x00 stored in general-purpose memory
0xB7 to 0xB9 0x000000 Reserved = 0x000000
0xBA to 0xFF All zero KSV_LIST = all zero, no KSVs stored
X = Don’t care.

18   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 2. Device Address Defaults (Register 0x00, 0x01)

MAX9265
DEVICE ADDRESS SERIALIZER DEVICE DESERIALIZER DEVICE
PIN
(bin) ADDRESS ADDRESS
ADD1 ADD0 D7 D6 D5 D4 D3 D2 D1 D0 (hex) (hex)
Low Low 1 0 0 X* 0 0 0 R/W 80 90
Low High 1 0 0 X* 0 1 0 R/W 84 94
Low Open 1 0 0 X* 1 0 0 R/W 88 98
High Low 1 1 0 X* 0 0 0 R/W C0 D0
High High 1 1 0 X* 0 1 0 R/W C4 D4
High Open 1 1 0 X* 1 0 0 R/W C8 D8
Open Low 0 1 0 X* 0 0 0 R/W 40 50
Open High 0 1 0 X* 0 1 0 R/W 44 54
Open Open 0 1 0 X* 1 0 0 R/W 48 58
*X = 0 for the serializer address, X = 1 for the deserializer address.

Table 3. LVDS, HDCP Mapping and Bus Width Selection (see Figures 13 and 14)
3-CHANNEL MODE 4-CHANNEL MODE
(BWS = LOW) (BWS = HIGH)
INPUT BITS AUXILIARY HDCP AUXILIARY HDCP
BITMAPPING SIGNALS ENCRYPTION BITMAPPING SIGNALS ENCRYPTION
MAPPING CAPABILITY MAPPING CAPABILITY
DIN[0:5] R[0:5] — Yes R[0:5] — Yes
DIN[6:11] G[0:5] — Yes G[0:5] — Yes
DIN[12:17] B[0:5] — Yes B[0:5] — Yes
DIN[18:20] HS, VS, DE — No HS, VS, DE — No
DIN[21:22] Not available — — R6, R7 — Yes
DIN[23:24] Not available — — G6, G7 — Yes
DIN[25:26] Not available — — B6, B7 — Yes
DIN27 Not available Not available — RES* CNTL1* No
DIN28 — Not available — — CNTL2 No
SD — SD/CNTL0 I2S** — SD/CNTL0 I2S**
*See the Reserved Bit (RES) section for details.
**HDCP encryption on SD when used as an I2S signal.

______________________________________________________________________________________   19
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
MAX9265

RXCLKIN-

RXCLKIN+
CYCLE N-1 CYCLE N

RXIN0+/RXIN0- DIN1 DIN0 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0

RXIN1+/RXIN1- DIN8 DIN7 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7

RXIN2+/RXIN2- DIN15 DIN14 DIN20 DIN19 DIN18 DIN17 DIN16 DIN15 DIN14

RXIN3+/RXIN3- DIN22 DIN21 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21

CNTL1 DIN27

CNTL2 DIN28

SD/CNTL0* SD*

*WITH I2S ENABLED; OTHERWISE CNTL0

Figure 13. LVDS Input Timing

RXCLKIN-

RXCLKIN+

CYCLE N-1 CYCLE N

RXIN0+/RXIN0- R1 R0 G0 R5 R4 R3 R2 R1 R0

RXIN1+/RXIN1- G2 G1 B1 B0 G5 G4 G3 G2 G1

RXIN2+/RXIN2- B3 B2 DE VS HS B5 B4 B3 B2

RXIN3+/RXIN3- R7 R6 RES B7 B6 G7 G6 R7 R6

Figure 14. Panel Clock and Bit Assignment

20   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Serial Link Signaling and Data Format Reserved Bit (RES)

MAX9265
The serializer uses CML signaling with programmable pre- In 4-channel mode, the serializer serializes all bits of all four
emphasis and AC-coupling. The GMSL deserializer uses lanes, including RES, by default. Set DISRES (D4 of register
AC-coupling and programmable channel equalization. 0x0D) to 1 to map CNTL1 to DIN27 instead of RES.
Together, the GMSL link can operate at full speed over STP
Reverse Control Channel
cable lengths to 15m or more.
The serializer uses the reverse control channel to receive
In addition to HDCP encryption (when enabled), the I2C/UART and interrupt signals from the GMSL deserial-
serializer scrambles and encodes the input data and sends izer in the opposite direction of the video stream. The
the 8b/10b coded signal through the serial link. Figures 15 reverse control channel and forward video data coexist
and 16 show the serial-data packet format before HDCP on the same twisted pair forming a bidirectional link. The
encryption, scrambling and 8b/10b encoding. In 3-chan- reverse control channel operates independently from the
nel or 4-channel mode, 21 or 29 bits map from the LVDS forward control channel. The reverse control channel is
input. The audio channel bit (ACB) contains an encoded available 500Fs after power-up. The serializer temporarily
audio signal derived from the three I2S signals (SD, SCK, disables the reverse control channel for 350Fs after start-
and WS). The forward control-channel (FCC) bit carries the ing/stopping the forward serial link.
forward control data. The last bit (PCB) is the parity bit of
the previous 23 or 31 bits.
24 BITS

DIN0 DIN1 DIN17 DIN18 DIN19 DIN20 ACB FCC PCB

R0 R1 B5 HS VS DE

RGB DATA CONTROL BITS

LVDS DATA AUDIO

(3 CHANNELS) CHANNEL OR
CNTL0 BIT

FORWARD
NOTE: VS/HS MUST BE SET AT DIN[19:18]
CONTROL-
FOR HDCP FUNCTIONALITY.
CHANNEL BIT
ONLY DIN[17:0] AND ACB HAVE HDCP ENCRYPTION.

PACKET
PARITY CHECK BIT

Figure 15. 3-Channel Mode Serial Link Data Format

32 BITS

DIN0 DIN1 DIN17 DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 DIN24 DIN25 DIN26 DIN27 DIN28 ACB FCC PCB

RES/
R0 R1 B5 HS VS DE R6 R7 G6 G7 B6 B7 CNTL2
CNTL1*

RGB DATA CONTROL BITS RGB DATA AUX AUDIO

CONTROL CHANNEL OR
BITS CNTL0 BIT

FORWARD
LVDS DATA LVDS DATA CONTROL-
(RXIN[2:0]_) (RXIN3_) CHANNEL BIT
NOTE: VS/HS MUST BE SET AT DIN[19:18] FOR HDCP FUNCTIONALITY.
PACKET
ONLY DIN[17:0], DIN[26:21] AND ACB HAVE HDCP ENCRYPTION.
PARITY
*DIN27 FROM LVDS DATA (RXIN3_) OR EXTERNAL PIN (CNTL1). CHECK BIT

Figure 16. 4-Channel Mode Serial Link Data Format

______________________________________________________________________________________   21
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Data-Rate Selection serializer or GMSL deserializer, with the UART packets
MAX9265

The serializer uses the DRS input to set the RXCLKIN_ converted to I2C by the device on the remote side of the link
frequency range. Set DRS high for an RXCLKIN_ (GMSL deserializer for LCD or serializer for image-sensing
frequency range of 6.25MHz to 12.5MHz (4-channel applications). The FC communicates with a UART periph-
mode) or 8.33MHz to 16.66MHz (3-channel mode). eral in base mode (through INTTYPE register settings),
Set DRS low for normal operation with an RXCLKIN_ using the half-duplex default GMSL UART protocol of the
frequency range of 12.5MHz to 78MHz (4-channel serializer/GMSL deserializer. The device addresses of
mode) or 16.66MHz to 104MHz (3-channel mode). the serializer and GMSL deserializer in base mode are
programmable. The default value is determined by the pin
Audio Channel settings of ADD0 and ADD1 (Table 2).
The I2S audio channel supports audio sampling rates
from 8kHz to 192kHz, and audio word lengths from 4 When the peripheral interface uses I2C (default), the
bits to 32 bits. The audio bit clock (SCK) does not have serializer/GMSL deserializer convert packets to I2C
to be synchronized with RXCLKIN_. The serializer auto- that have device addresses different from those of the
matically encodes audio data into a single bit stream serializer or GMSL deserializer. The converted I2C bit rate
synchronous with RXCLKIN_. The GMSL deserializer is the same as the original UART bit rate.
decodes the audio stream and stores audio words in a The GMSL deserializer uses a proprietary differential
FIFO. Audio rate detection uses an internal oscillator to line coding to send signals back towards the serializer.
continuously determine the audio data rate and output The speed of the control channel ranges from 9.6kbps
the audio in I2S format. The audio channel is enabled by to 1Mbps in both directions. The serializer and GMSL
default. When the audio channel is disabled, SD/CNTL0 deserializer automatically detect the control-channel bit
on the serializer and GMSL deserializer is treated as an rate in base mode. Packet bit rates can vary up to 3.5x
additional control signal (CNTL0). from the previous bit rate (see the Changing the Clock
Since the audio data sent through the serial link is Frequency section).
synchronized with RXCLKIN, low RXCLKIN_ frequencies Figure 17 shows the UART protocol for writing and reading
limit the maximum audio sampling rate. Table 4 lists the in base mode between the FC and the serializer/GMSL
maximum audio sampling rate for various RXCLKIN_ deserializer.
frequencies. Spread-spectrum settings do not affect the Figure 18 shows the UART data format. Figure 19 and
I2S data rate or WS clock frequency. Figure 20 detail the formats of the SYNC byte (0x79) and
Control Channel and Register Programming the ACK byte (0xC3). The FC and the connected slave
The control channel is available for the FC to send chip generate the SYNC byte and ACK byte, respectively.
and receive control data over the serial link simultane- Events such as device wake-up and interrupt generate
ously with the high-speed data. Configuring the CDS pin transitions on the control channel that should be ignored
allows the FC to control the link from either the serializer by the FC. Data written to the serializer/GMSL deserializer
or the GMSL deserializer side to support video-display registers do not take effect until after the acknowledge
or image-sensing applications. The control channel byte is sent. This allows the FC to verify write commands
between the FC and serializer or GMSL deserializer runs received without error, even if the result of the write com-
in base mode or bypass mode according to the mode mand directly affects the serial link. The slave uses the
selection (MS) input of the device connected to the FC. SYNC byte to synchronize with the host UART data rate
Base mode is a half-duplex control channel and the automatically. If the INT or MS inputs of the GMSL deserial-
bypass mode is a full-duplex control channel. izer toggles while there is control-channel communication,
the control-channel communication can be corrupted. In
Base Mode the event of a missed acknowledge, the FC should assume
In base mode, the FC is the host and can access the there was an error in the packet when the slave device
core and HDCP registers of both the serializer and GMSL receives it, or that an error occurred during the response
deserializer from either side of the link by using the GMSL from the slave device. In base mode, the FC must keep
UART protocol. The FC can also program the peripherals the UART Tx/Rx lines high for 16 bit-times before starting to
on the remote side by sending the UART packets to the send a new packet.

22   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 4. LVDS, HDCP Mapping and Bus Width Selection (see Figures 13 and 14)

MAX9265
RXCLKIN_ FREQUENCY RXCLKIN_ FREQUENCY
WORD
(DRS = LOW) (DRS = HIGH)
LENGTH
(MHz) (MHz)
(bits)
12.5 15 16.6 > 20 6.25 7.5 8.33 > 10
8 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192
16 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192
18 185.5 > 192 > 192 > 192 185.5 > 192 > 192 > 192
20 174.6 > 192 > 192 > 192 174.6 > 192 > 192 > 192
24 152.2 182.7 > 192 > 192 152.2 182.7 > 192 > 192
32 123.7 148.4 164.3 > 192 123.7 148.4 164.3 > 192

WRITE DATA FORMAT

SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1 BYTE N

MASTER WRITES TO SLAVE ACK

MASTER READS FROM SLAVE

READ DATA FORMAT

SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES

MASTER WRITES TO SLAVE ACK BYTE 1 BYTE N

MASTER READS FROM SLAVE

Figure 17. GMSL UART Protocol for Base Mode

1 UART FRAME

START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP

FRAME 1 FRAME 2 FRAME 3

STOP START STOP START

Figure 18. GMSL UART Data Format for Base Mode

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
START 1 0 0 1 1 1 1 0 PARITY STOP START 1 1 0 0 0 0 1 1 PARITY STOP

Figure 19. Sync Byte (0x79) Figure 20. ACK Byte (0xC3)

______________________________________________________________________________________   23
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
As shown in Figure 21, the remote-side device converts the the serializer by writing to the SETINT register bit. In normal
MAX9265

packets going to or coming from the peripherals from the operation, the state of the interrupt output changes when
UART format to the I2C format and vice versa. The remote the interrupt input on the GMSL deserializer toggles. Do not
device removes the byte number count and adds or receives send a logic-low value longer than 100Fs in either base or
the ACK between the data bytes of I2C. The I2C’s data rate is bypass mode to ensure proper interrupt functionality.
the same as the UART data rate.
Pre/Deemphasis Driver
Interfacing Command-Byte-Only I2C Devices The serial line driver in the serializer employs current-mode
The serializer and GMSL deserializer UART-to-I2C conver- logic (CML) signaling. The driver can generate an adjust-
sion interfaces with devices that do not require register able preemphasized waveform according to the cable
addresses, such as the MAX7324 GPIO expander. In this length and characteristics. There are 13 preemphasis set-
mode, the I2C master ignores the register address byte and tings as shown in Table 5. Negative preemphasis levels are
directly reads/writes the subsequent data bytes (Figure 22). deemphasis levels in which the preemphasized swing level
Change the communication method of the I2C master using is the same as normal swing, but the no-transition data is
the I2CMETHOD bit. I2CMETHOD = 1 sets command-byte- deemphasized. Program the preemphasis levels through
only mode, while I2CMETHOD = 0 sets normal mode where register 0x05 D[3:0] of the serializer. This preemphasis
the first byte in the data stream is the register address. function compensates the high frequency loss of the
cable and enables reliable transmission over longer link
Bypass Mode
distances. Additionally, a lower power drive mode can be
In bypass mode, the serializer/GMSL deserializer ignore
entered by programming CMLLVL bits (0x05 D[5:4]) to
UART commands from the FC and the FC communi-
reduce the driver strength down to 75% (CMLLVL = 10) or
cates with the peripherals directly using its own defined
50% (CMLLVL = 01) from 100% (CMLLVL = 11, default).
UART protocol. The FC cannot access the serializer/GMSL
deserializer’s registers in this mode. Peripherals accessed Spread Spectrum
through the forward control channel using the UART To reduce the EMI generated by the transitions on the
interface need to handle at least one RXCLKIN_ period serial link, the serializer supports spread spectrum. Turning
±10ns of jitter due to the asynchronous sampling of the on spread spectrum on the serializer spreads the serial
UART signal by RXCLKIN_. Set MS = high to put the control link, which is tracked by the serializer deserializer. The
channel into bypass mode. For applications with the FC six selectable spread-spectrum rates at the serial output
connected to the deserializer (CDS is high), there is a 1ms are Q0.5%, Q1%, Q1.5%, Q2%, Q3%, and Q4% (Table 6).
wait time between setting MS high and the bypass control Some spread-spectrum rates can only be used at lower
channel being active. There is no delay time in switching RXCLKIN_ frequencies (Table 7). There is no RXCLKIN_
to bypass mode when the FC is connected to the serial- frequency limit for the 0.5% spread rate.
izer (CDS = low). Bypass mode accepts bit rates down to Set the serializer’s SSEN input high to select 0.5% spread
9.6kbps in either direction. See the Interrupt Control section at power-up and SSEN input low to select no spread at
for interrupt functionality limitations. The control-channel power-up. The state of SSEN is latched upon power-up or
data pattern should not be held low longer than 100Fs when resuming from power-down mode.
in either base or bypass mode to ensure proper interrupt
functionality. Whenever the serializer’s spread spectrum is turned on
or off, the serial link automatically restarts and remains
Interrupt Control unavailable while the GMSL deserializer relocks to the
The INT pin of the serializer is the interrupt output and the serial data. Turning on spread spectrum on the serializer or
INT pin of the GMSL deserializer is the interrupt input. The GMSL deserializer does not affect the audio data stream.
interrupt output on the serializer follows the transitions at the The serializer includes a sawtooth divider to control the
interrupt input. This interrupt function supports remote-side spread-modulation rate. Autodetection or manual pro-
functions such as touch-screen peripherals, remote power- gramming of the RXCLKIN_ operation range guarantees
up, or remote monitoring. Interrupts that occur during a spread-spectrum modulation frequency within 20kHz to
periods where the reverse control channel is disabled, such 40kHz. Additionally, manual configuration of the sawtooth
as link startup/shutdown, are automatically resent once the divider (SDIV, 0x03 D[5:0]) allows the user to set a modu-
reverse control channel becomes available again. Bit D4 lation frequency according to the RXCLKIN_ frequency.
of register 0x06 in the GMSL deserializer also stores the Always keep the modulation frequency between 20kHz to
interrupt input state. The INT output of the serializer is low 40kHz to ensure proper operation.
after power-up. In addition, the FC can set the INT output of

24   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface

MAX9265
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
FC SERIALIZER/GMSL DESERIALIZER
11 11 11 11 11 11 11
SYNC FRAME DEVICE ID + WR REGISTER ADDRESS NUMBER OF BYTES DATA 0 DATA N ACK FRAME

SERIALIZER/GMSL DESERIALIZER PERIPHERAL

1 7 1 1 8 1 8 1 8 1 1
S DEV ID W A REG ADDR A DATA 0 A DATA N A P

UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 0)

FC SERIALIZER/GMSL DESERIALIZER
11 11 11 11 11 11 11
SYNC FRAME DEVICE ID + RD REGISTER ADDRESS NUMBER OF BYTES ACK FRAME DATA 0 DATA N

SERIALIZER/GMSL DESERIALIZER PERIPHERAL

1 7 1 1 8 1 1 7 1 1 8 1 8 1 1
S DEV ID W A REG ADDR A S DEV ID R A DATA 0 A DATA N A P

: MASTER TO SLAVE : SLAVE TO MASTER S: START P: STOP A: ACKNOWLEDGE

Figure 21. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0)

UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)

FC SERIALIZER/GMSL DESERIALIZER
11 11 11 11 11 11 11
SYNC FRAME DEVICE ID + WR REGISTER ADDRESS NUMBER OF BYTES DATA 0 DATA N ACK FRAME

SERIALIZER/GMSL DESERIALIZER PERIPHERAL

1 7 1 1 8 1 8 1 1
S DEV ID W A DATA 0 A DATA N A P

UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 1)

FC SERIALIZER/GMSL DESERIALIZER
11 11 11 11 11 11 11
SYNC FRAME DEVICE ID + RD REGISTER ADDRESS NUMBER OF BYTES ACK FRAME DATA 0 DATA N

SERIALIZER/GMSL DESERIALIZER PERIPHERAL

1 7 1 1 8 1 8 1 1
S DEV ID R A DATA 0 A DATA N A P

: MASTER TO SLAVE : SLAVE TO MASTER S: START P: STOP A: ACKNOWLEDGE

Figure 22. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1)

______________________________________________________________________________________   25
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 5. CML Driver Strength (Default Level, CMLLVL = 11)
MAX9265

SINGLE-ENDED VOLTAGE SWING

PREEMPHASIS LEVEL PREEMPHASIS SETTING ICML IPRE
MAX MIN
(dB)* (0x05, D[3:0]) (mA) (mA)
(mV) (mV)
-6.0 0100 12 4 400 200
-4.1 0011 13 3 400 250
-2.5 0010 14 2 400 300
-1.2 0001 15 1 400 350
0 0000 16 0 400 400
1.1 1000 16 1 425 375
2.2 1001 16 2 450 350
3.3 1010 16 3 475 325
4.4 1011 16 4 500 300
6.0 1100 15 5 500 250
8.0 1101 14 6 500 200
10.5 1110 13 7 500 150
14.0 1111 12 8 500 100
*Negative preemphasis levels denote deemphasis.

Table 6. Serial Output Spread

SS SPREAD (%)
000 No spread spectrum. Power-up default when SSEN = low.
001 Q0.5% spread spectrum. Power-up default when SSEN = high.
010 Q1.5% spread spectrum.
011 Q2% spread spectrum.
100 No spread spectrum.
101 Q1% spread spectrum.
110 Q3% spread spectrum.
111 Q4% spread spectrum.

Table 7. Spread-Spectrum Rate Limitations

3-CHANNEL MODE 4-CHANNEL MODE
SERIAL LINK BIT-RATE
RXCLKIN_ FREQUENCY RXCLKIN_ FREQUENCY AVAILABLE SPREAD RATES
(Mbps)
(MHz) (MHz)
< 33.3 < 25 < 1000 All rates available
33.3 to < 66.7 20 to <50 1000 to < 2000 1.5%, 1%, 0.5%
66.7+ 50+ 2000+ 0.5%

26   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Manual Programming of the a low-power state. Entering sleep mode resets the HDCP

MAX9265
Spread-Spectrum Divider registers but not the configuration registers.
The modulation rate for the serializer relates to the
Power-Down Mode
RXCLKIN_ frequency as follows:
The serializer includes a shutdown mode to further
f
fM = (1 + DRS) RXCLKIN_ reduce power consumption. Set PWDN low to enter
MOD x SDIV power-down mode. While in power-down mode, the
outputs of the device remain high impedance. Entering
where:
power-down mode resets the internal registers of the
fM = Modulation frequency device. In addition, upon exiting power-down mode, the
DRS = DRS pin input value (0 or 1) serializer relatches the state of SSEN, DRS, AUTOS,
and ADD_.
fRXCLKIN_ = RXCLKIN_ frequency
MOD = Modulation coefficient given in Table 8 Configuration Link Mode
The GMSL includes a low-speed configuration link to
SDIV = 6-bit SDIV setting, manually programmed by allow control-data connection between the two devices
the FC in the absence of a valid clock input. In either display or
To program the SDIV setting, first look up the modulation camera applications, the configuration link can be used
coefficient according to the part number and desired to program equalizer/preemphasis or other registers
bus-width and spread-spectrum settings. Solve the before establishing the video link. An internal oscillator
above equation for SDIV using the desired pixel clock provides RXCLKIN_ for establishing the serial configura-
and modulation frequencies. If the calculated SDIV value tion link between the serializer and GMSL deserializer.
is larger than the maximum allowed SDIV value in Table Set CLINKEN = 1 on the serializer to turn on the con-
8, set SDIV to the maximum value. figuration link. The configuration link remains active as
long as the video link has not been enabled. The video
Sleep Mode
link overrides the configuration link and attempts to lock
The serializer includes a low-power sleep mode to
when SEREN = 1.
reduce power consumption. Set the SLEEP bit to 1 to
initiate sleep mode. The serializer sleeps immediately Link Startup Procedure
after setting its SLEEP = 1. See the Link Startup Table 9 lists four startup cases for video-display applica-
Procedure section for details on waking up the device tions. Table 10 lists two startup cases for image-sensing
for different FC and starting conditions. applications. In either video-display or image-sensing
The FC can only put the remote-side device to sleep. applications, the control link is always available after
Use the PWDN input pin to bring the FC-side device into the high-speed data link or the configuration link is

Table 8. Modulation Coefficients and Maximum SDIV Settings

SPREAD-SPECTRUM MODULATION COEFFICIENT SDIV UPPER LIMIT
BIT-WIDTH MODE
SETTING (%) MOD (decimal) (decimal)
1 104 40
0.5 104 63
3 152 27
4-Channel
1.5 152 54
4 204 15
2 204 30
1 80 52
0.5 80 63
3 112 37
3-Channel
1.5 112 63
4 152 21
2 152 42

______________________________________________________________________________________   27
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
established and the serializer/GMSL deserializer regis- to the GMSL deserializer. The GMSL deserializer exits
MAX9265

ters or the peripherals are ready for programming. sleep mode after locking to the serial data and sets
SLEEP = 0. If after 8ms the GMSL deserializer does
Video-Display Applications not lock to the input serial data, the GMSL deserializer
For the video-display application with a remote display goes back to sleep and the internal sleep bit remains set
unit, connect the FC to the serializer and set CDS = low (SLEEP = 1).
for both the serializer and GMSL deserializer. Table 9
summarizes the four startup cases based on the settings Case 3: Remote-Side Autostart Mode
of AUTOS and MS. After power-up or when PWDN transitions from low
to high, the remote device (GMSL deserializer) starts
Case 1: Autostart Mode up and tries to lock to an incoming serial signal with
After power-up or when PWDN transitions from low to sufficient power. The host side (serializer) is in standby
high for both the serializer and GMSL deserializer, the mode and does not try to establish a link. Use the FC and
serial link establishes if a stable clock is present. The program the serializer to set SEREN = 1 (and apply a
serializer locks to the clock and sends the serial data stable clock signal) to establish a video link, or CLINKEN
to the GMSL deserializer. The GMSL deserializer then = 1 to establish the configuration link. In this case, the
detects activity on the serial link and locks to the input GMSL deserializer ignores the short wake-up signal sent
serial data. from the serializer.
Case 2: Standby Start Mode Case 4: Remote Side in Sleep Mode
After power-up or when PWDN transitions from low to After power-up or when PWDN transitions from low to
high for both the serializer and GMSL deserializer, the high, the remote device (GMSL deserializer) starts up in
GMSL deserializer starts up in sleep mode and the sleep mode. The high-speed link establishes automati-
serializer stays in standby mode (does not send serial cally after the serializer powers up with a stable clock
data). Use the FC and program the serializer to set signal and sends a wake-up signal to the GMSL dese-
SEREN = 1 to establish a video link, or CLINKEN = 1 rializer. Use this mode in applications where the GMSL
to establish the configuration link. After locking to a deserializer powers up before the serializer.
stable clock (for SEREN = 1) or the internal oscillator
(for CLINKEN = 1), the serializer sends a wake-up signal

Table 9. Start Mode Selection for Display Applications (CDS = Low)

SERIALIZER MS GMSL
AUTOS
CASE POWER-UP (GMSL DESERIALIZER LINK STARTUP MODE
(SERIALIZER)
STATE DESERIALIZER) POWER-UP STATE
Serialization Normal Both devices power up with serial link
1 Low Low
enabled (SLEEP = 0) active (autostart).

The serial link is disabled and the

GMSL deserializer powers up in sleep
Serialization Sleep mode
2 High High mode. Set SEREN = 1 or CLINKEN =
disabled (SLEEP = 1)
1 in the serializer to start the serial link
and wake up the GMSL deserializer.

Both devices power up in normal mode

Serialization Normal with the serial link disabled. Set SEREN
3 High Low
disabled (SLEEP = 0) = 1 or CLINKEN = 1 in the serializer to
start the serial link.
The GMSL deserializer starts in sleep
mode. Link autostarts upon serializer
Serialization Sleep mode
4 Low High power-up. Use this case when the
enabled (SLEEP = 1)
GMSL deserializer powers up before
the serializer.

28   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface

MAX9265
CLINKEN = 0 OR
AUTOS PIN SEREN BIT SEREN = 1
SETTING POWER-UP VALUE
LOW 1
HIGH 0

CLINKEN = 0 OR
SEREN = 1 CONFIG LINK
PWDN = HIGH, CONFIG LINK
POWER-DOWN POWER-ON POWER-ON CONFIG UNLOCKED OPERATING
OR POWER-OFF IDLE LINK STARTING PROGRAM
AUTOS = LOW CLINKEN = 1 CONFIG LINK
LOCKED REGISTERS

SEREN = 1, SEREN = 0,
PWDN = LOW OR NO RXCLKIN_
RXCLKIN_ RUNNING
POWER-OFF
PWDN = HIGH
SEREN = 0, OR
POWER-ON,
NO RXCLKIN_
AUTOS = LOW PRBSEN = 0
VIDEO VIDEO LINK VIDEO LINK VIDEO LINK
ALL STATES
LINK LOCKING LOCKED OPERATING PRBS TEST
PRBSEN = 1

VIDEO LINK
UNLOCKED

Figure 23. State Diagram, CDS = Low (LCD Application)

Image-Sensing Applications the sleep bit (SLEEP = 0) of the serializer using a regular
For image-sensing applications, connect the FC to the control-channel write packet to power up the device fully.
GMSL deserializer and set CDS = high for both the Send the sleep bit write packet at least 500Fs after the
serializer and GMSL deserializer. The GMSL deserial- wake-up frame. The serializer goes back to sleep mode
izer powers up normally (SLEEP = 0) and continuously if its sleep bit is not cleared within 5ms (min) after detect-
tries to lock to a valid serial input. Table 10 summarizes ing a wake-up frame.
both startup cases, based on the state of the serializer’s
HDCP
AUTOS pin.
The explanation of HDCP operation in this data
Case 1: Autostart Mode sheet is given as a guide for general understand-
After power-up, or when PWDN transitions from low to ing. Implementation of HDCP in a product must
high, the serializer locks to a stable input clock and meet the requirements given in the “HDCP System
sends the high-speed data to the GMSL deserializer. The v1.3 Amendment for GMSL,” which is available from
GMSL deserializer locks to the serial data and outputs DCP, LLC.
the video data and clock. HDCP uses two main phases of operation: authentication
Case 2: Sleep Mode and the link integrity check. The FC starts authentication
After power-up or when PWDN transitions from low to by writing to the START_AUTHENTICATION bit in the
high, the serializer starts up in sleep mode. To wake up serializer. The serializer generates a 64-bit random num-
the serializer, use the FC to send a GMSL-protocol UART ber. The host FC first reads the 64-bit random number
frame containing at least three rising edges (e.g., 0x66), from the serializer and writes it to the GMSL deserializer.
at a bit rate no greater than 1Mbps. The low-power wake- The FC then reads the serializer public key selection
up receiver of the serializer detects the wake-up frame vector (AKSV) and writes it to the GMSL deserializer.
over the reverse control channel and powers up. Reset The FC then reads the GMSL deserializer KSV (AKSV)

______________________________________________________________________________________   29
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 10. Start Mode Selection for Image-Sensing Applications (CDS = High)
MAX9265

AUTOS SERIALIZER POWER- GMSL DESERIALIZER

CASE LINK STARTUP MODE
(SERIALIZER) UP STATE POWER-UP STATE
Normal
1 Low Serialization enabled Autostart.
(SLEEP = 0)
The serializer is in sleep mode. Wake up
Sleep mode Normal
2 High the serializer through the control channel
(SLEEP = 1) (SLEEP = 0)
(FC attached to GMSL deserializer).

AUTOS PIN POWER-UP VALUE

SETTING SEREN SLEEP
LOW 1 0 CLINKEN = 0 OR
HIGH 0 1 SEREN = 1

CLINKEN = 0 OR
SLEEP = 1 SEREN = 1 CONFIG LINK CONFIG LINK
FOR > 8ms SLEEP = 0, POWER-ON CONFIG UNLOCKED OPERATING
SLEEP WAKE-UP
SEREN = 0 IDLE CLINKEN = 1 LINK STARTED CONFIG LINK PROGRAM
REVERSE LINK
LOCKED REGISTERS
WAKE-UP SIGNAL
PWDN = HIGH, SEREN = 1,
SEREN = 0 OR
POWER-ON, SLEEP = 0, RXCLKIN_ RUNNING
SLEEP = 1 NO RXCLKIN_
AUTOS = HIGH SLEEP = 1
SEREN = 0 OR
NO RXCLKIN_
PWDN = HIGH, PRBSEN = 0
PWDN = LOW OR POWER-DOWN VIDEO LINK
POWER-ON VIDEO VIDEO LINK VIDEO LINK
ALL STATES OR
POWER-OFF AUTOS = LOW LINK LOCKING LOCKED OPERATING PRBSEN = 1 PRBS TEST
POWER-OFF

VIDEO LINK
UNLOCKED

Figure 24. State Diagram, CDS = High (Camera Application)

and writes it to the serializer. The FC begins checking reads and compares the R0/R0’ values from the serial-
the receiver BKSV against the revocation list. Using the izer/GMSL deserializer.
cipher, the serializer and GMSL deserializer calculate During response value generation and checking, the
a 16-bit response value (R0 and R0’, respectively). host FC checks for a valid BKSV against the revocation
The GMSL amendment for HDCP reduces the 100ms list. If BKSV is not on the list and the response values
minimum wait time allowed the receiver to generate R0’ match, the host authenticates the link. If the response
(specified in HDCP rev 1.3) to 128 pixel clock cycles in values do not match, the FC resamples the response
the GMSL amendment. values (as described in HDCP rev 1.3 Appendix C). If
There are two response value comparison modes: internal resampling fails, the FC restarts authentication. If BKSV
comparison and FC comparison. Set EN_INT_COMP = 1 appears on the revocation list, the host cannot transmit
to select internal comparison mode. Set EN_INT_COMP = data that requires protection. The host knows when the
0 to select FC comparison mode. In internal comparison link is authenticated and decides when to output data
mode, the FC reads the GMSL deserializer response R0’ requiring protection. The FC performs a link integrity
and writes it to the serializer. The serializer compares check every 128 frames or every 2s Q0.5s. The serializer/
R0’ to its internally generated response value R0, and GMSL deserializer generate response values every 128
sets R0_RI_MATCHED. In FC comparison mode, the FC frames. These values are compared internally (internal
comparison mode) or can be compared in the host FC.

30   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
In addition, the serializer/GMSL deserializer provide Repeater Support

MAX9265
response values for the enhanced link verification The serializer has features to build an HDCP repeater.
feature. Enhanced link verification is an optional meth- An HDCP repeater receives and decrypts HDCP content
od of link verification for faster detection of loss-of- and then encrypts and transmits on one or more down-
synchronization. For this option, the serializer and GMSL stream links. A repeater can also use decrypted HDCP
deserializer generate 16-bit values (Pj and Pj’) every 16 content (e.g., to display on a screen). To support HDCP
frames. The host must detect three consecutive Pj/Pj’ repeater authentication protocol, the GMSL deserial-
mismatches before going to the resampling. izer has a REPEATER register bit. This register bit must
be set to 1 by the FC (most likely on repeater module).
Encryption Enable
Both the serializer and GMSL deserializer use SHA-1
The GMSL link transfers either encrypted or nonen-
hash-value calculation over the assembled KSV lists.
crypted data. For encrypted data, the host FC sets the
HDCP GMSL links support a maximum of 15 receivers
encryption enable (ENCRYPTION_ENABLE) bit in both
(total number including the ones in repeater modules). If
the serializer and GMSL deserializer. The FC must set
the total number of receiver devices exceed 14, the FC
ENCRYPTION_ENABLE in the same VSYNC cycle in
must set the MAX_DEVS_EXCEEDED register bit when it
both the serializer and GMSL deserializer (no VSYNC
assembles the KSV list.
falling edges between the two writes). The same timing
applies when clearing ENCRYPTION_ENABLE to disable Force Video/Force Audio for Unencrypted Data
encryption. The serializer masks audio and video data through two
Note: ENCRYPTION_ENABLE enables/disables encryp- control bits: FORCE_AUDIO and FORCE_VIDEO. Set
tion on the GMSL irrespective of the content. To comply FORCE_VIDEO = 1 to transmit the 24-bit data word in
with HDCP, the FC must not allow content requiring the DFORCE register instead of the video data received
encryption to cross the GMSL unencrypted. See the at the LVDS input. Set FORCE_AUDIO = 0 to transmit
Force Video/Force Audio for Unencrypted Data section. 0 instead of the SD input (SCK and WS continue to be
output from the deserializer). Use these features to blank
The FC must complete the authentication process before out the screen and mute the audio.
enabling encryption. In addition, encryption must be
disabled before starting a new authentication session. HDCP Authentication Procedures
VSYNC Detection The serializer generates a 64-bit random number
If the FC cannot detect the video vertical sync (VSYNC) exceeding the HDCP requirement. The serializer/GMSL
falling edge, it can use the serializer’s VSYNC_DET deserializer internal one-time programmable (OTP)
register bit. The host FC first writes 0 to the VSYNC_DET memories contain unique HDCP keyset programmed at
bit. The serializer then sets VSYNC_DET = 1 once the factory. The host FC initiates and controls the HDCP
it detects an internal VSYNC falling edge (which authentication procedure. The serializer and GMSL
may correspond to an external VSYNC rising edge if deserializer generate HDCP authentication response
INVVSYNC of the serializer is set). The FC continu- values for the verification of authentication. Use the
ously reads VSYNC_DET and waits for the next inter- following procedures to authenticate the HDCP GMSL
nal VSYNC falling edge before setting ENCRYPTION_ encryption (refer to the HDCP 1.3 Amendment for GMSL
ENABLE. Poll VSYNC_DET fast enough to allow time to for details). The FC must perform link integrity checks
set ENCRYPTION_ENABLE in both the serializer/GMSL while encryption is enabled (see Tables 12 and 13). Any
deserializer within the same VSYNC cycle. event that indicates that the GMSL deserializer has lost
Synchronization of Encryption link synchronization should retrigger authentication. The
The VSYNC synchronizes the start of encryption. Once FC must first write 1 to the RESET_HDCP bit in the serial-
encryption has started, the GMSL generates a new izer before starting a new authentication attempt.
encryption key for each frame and each line, with the HDCP Protocol Summary
internal falling edge of VSYNC and HSYNC. Rekeying is Tables 11, 12, and 13 list the summaries of the HDCP
transparent to data and does not disrupt the encryption protocol. These tables serve as an implementation guide
of video or audio data. only. Meet the requirements in the GMSL amendment for
HDCP to be in full compliance.

______________________________________________________________________________________   31
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 11. Startup, HDCP Authentication and Normal Operation (GMSL DESERIALIZER
MAX9265

is not a Repeater)—First Part of the HDCP Authentication Protocol

NO. µC SERIALIZER GMSL DESERIALIZER
Powers up waiting for Powers up waiting for
1 Initial state after power-up.
HDCP authentication. HDCP authentication.
Ensures that A/V data not requiring protection (low-value
content) is available at the serializer inputs (such as blue or
informative screen). Alternatively, use the FORCE_VIDEO
2 — —
and FORCE_AUDIO bits of the serializer to mask the A/V
data at the input of the serializer. Starts the link by writing
SEREN = H or link starts automatically if AUTOS is low.
Starts serialization and Locks to incoming data
3 — transmits low-value content stream and outputs low-
A/V data. value content A/V data.
Reads the locked bit of the GMSL deserializer and makes
4 — —
sure link is established.

Combines seed with inter-

nally generated random
5 Optionally writes a random-number seed to the serializer. number. If no seed is pro- —
vided, only internal random
number is used.

If HDCP encryption is required, starts authentication by Generates (stores) AN

6 writing 1 to the START_AUTHENTICATION bit of the and resets the START_ —
serializer. AUTHENTICATION bit to 0.

Reads AN and AKSV from the serializer and writes to the Generates R0’ triggered by
7 —
GMSL deserializer. the FC’s write of AKSV.
Reads the BKSV and REPEATER bit from the GMSL deseri- Generates R0, triggered by
8 —
alizer and writes to the serializer. the FC’s write of BKSV.
Reads the INVALID_BKSV bit of the serializer and con-
tinues with authentication if it is 0. Authentication can be
9 — —
restarted if it fails (set RESET_HDCP = 1 before restarting
authentication).

Reads R0’ from the GMSL deserializer and reads R0 from

the serializer. If they match, continues with authentication;
otherwise retries up to two more times (optionally, the seri-
10 — —
alizer comparison can be used to detect if R0/R0’ match).
Authentication can be restarted if it fails (set RESET_HDCP
= 1 before restarting authentication).

Waits for the VSYNC falling edge (internal to the serial-

izer) and then sets the ENCRYPTION_ENABLE bit to 1 in Encryption is enabled after Decryption is enabled after
11 the GMSL deserializer and serializer (if the FC is not able the next VSYNC falling the next VSYNC falling
to monitor VSYNC, it can utilize the VSYNC_DET bit in the edge. edge.
serializer).

32   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 11. Startup, HDCP Authentication and Normal Operation (GMSL DESERIALIZER

MAX9265
is not a Repeater)—First Part of the HDCP Authentication Protocol (continued)
NO. µC SERIALIZER GMSL DESERIALIZER
Checks that BKSV is not in the Key Revocation List and
continues if it is not. Authentication can be restarted if it
12 fails. — —
Note: Revocation list check can start after BKSV is read in
step 8.

Performs HDCP encryption Performs HDCP decryption

13 Starts transmission of the A/V content that needs protection. on high-value content A/V on high-value content A/V
data. data.

Table 12. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption
is Enabled
NO. µC SERIALIZER GMSL DESERIALIZER
Generates Ri and updates Generates Ri’ and updates
1 — the RI register every 128 the RI’ register every 128
VSYNC cycles. VSYNC cycles.
Continues to receive,
Continues to encrypt and
2 — decrypt, and output A/V
transmit A/V data.
data.

3 Every 128 video frames (VSYNC cycles) or every 2s. — —

4 Reads RI from the serializer. — —

5 Reads RI’ from the GMSL deserializer. — —
Reads RI again from the serializer and ensures it is stable
6 (matches the previous RI that it has read from the serial- — —
izer). If RI is not stable, go back to step 5.
If RI matches RI’, the link integrity check is successful; go
7 — —
back to step 3.
If RI does not match RI’, the link integrity check fails.
After the detection of failure of link integrity check, the FC
ensures that A/V data not requiring protection (low-value
8 content) is available at the serializer’s inputs (such as blue — —
or informative screen). Alternatively, the FORCE_VIDEO
and FORCE_AUDIO bits of the serializer can be used to
mask the A/V data input of the serializer.

Disables encryption and Disables decryption and

Writes 0 to the ENCRYPTION_ENABLE bit of the serializer
9 transmits low-value content outputs low-value content
and GMSL deserializer.
A/V data. A/V data.
Restarts authentication by writing 1 to the RESET_HDCP
10 bit, followed by writing 1 to the START_AUTHENTICATION — —
bit in the serializer.

______________________________________________________________________________________   33
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 13. Optional Enhanced Link Integrity Check—Performed Every 16 Frames After
MAX9265

Encryption is Enabled
NO. µC SERIALIZER GMSL DESERIALIZER
Generates Pj and updates Generates Pj’ and updates
1 — the PJ register every 16 the PJ’ register every 16
VSYNC cycles. VSYNC cycles.
Continues to receive,
Continues to encrypt and
2 — decrypt, and output the
transmit the A/V data.
A/V data.
Every 16 video frames: reads PJ from the serializer and PJ’
3 — —
from the GMSL deserializer.
If PJ matches PJ’, enhanced link integrity check is
4 — —
successful; go back to step 3.

If there is a mismatch, retry up to two more times from step

3. Enhanced link integrity check fails after three mismatch-
es. After the detection of failure of enhanced link integrity
check, the FC ensures that A/V data not requiring protec-
5 — —
tion (low-value content) is available at the serializer inputs
(such as blue or informative screen). Alternatively, the
FORCE_VIDEO and FORCE_AUDIO bits of the serializer
can be used to mask the A/V data input of the serializer.

Disables encryption and Disables decryption and

Writes 0 to the ENCRYPTION_ENABLE bit of the serializer
6 transmits low-value content outputs low-value content
and GMSL deserializer.
A/V data. A/V data.
Restarts authentication by writing 1 to the RESET_HDCP
7 bit, followed by writing 1 to the START_AUTHENTICATION — —
bit in the serializer.

Example Repeater Network—Two µCs Use the following procedure to notify downstream links of
The example shown in Figure 25 has one repeater the start of a new authentication request:
and two FCs. Table 14 summarizes the authentication 1) Host FC begins authentication with HDCP repeater’s
operation. input receiver.
Detection and Action Upon 2) When AKSV is written to HDCP repeater’s input
New Device Connection receiver, its AUTH_STARTED bit is automatically set
When a new device is connected to the system, the and its GPIO1 goes high (if GPIO1_FUNCTION is set
device must be authenticated and the device’s KSV is to high).
checked against the revocation list. The downstream 3) HDCP repeater’s FC waits for a low-to-high transition
FCs can set the NEW_DEV_CONN bit of the upstream on HDCP repeater input receiver’s AUTH_STARTED
receiver and invoke an interrupt to notify upstream FCs. bit and/or GPIO1 (if configured) and starts authentica-
Notification of Start of Authentication and tion downstream.
Enable of Encryption to Downstream Links 4) HDCP repeater’s FC resets AUTH_STARTED bit.
HDCP repeaters do not immediately begin authentication
Set GPIO0_FUNCTION to high to have GPIO0 follow the
upon startup or detection of a new device, but instead
ENCRYPTION_ENABLE bit of the receiver. The repeater
wait for an authentication request from the upstream
FC can use this function to be notified when encryption
transmitter/repeaters.
is enabled/disabled by an upstream FC.

34   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface

MAX9265
BD-DRIVE REPEATER DISPLAY 1
TX_B1 RX_R1 TX_R1 RX_D1

VIDEO
µC_B ROUTING DISPLAY 2
MEMORY RX_R2 µC_R TX_R2 RX_D2
WITH SRM

VIDEO CONNECTION
CONTROL CONNECTION 1 (µC_B IN BD-DRIVE IS MASTER)
CONTROL CONNECTION 2 (µC_R IN REPEATER IS MASTER)

Figure 25. Example Network with One Repeater and Two µCs (TXs are for the Serializer and RXs are for the GMSL Deserializer)

Table 14. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol
GMSL
SERIALIZER
DESERIALIZER
NO. µC_B µC_R (TX_B1, TX_R1,
(RX_R1, RX_D1,
TX_R2)
RX_D2)

TX_B1 CDS = 0 RX_R1 CDS = 1

— — — TX_R1 CDS = 0 RX_D1 CDS = 0
TX_R2 CDS = 0 RX_D2 CDS = 0
All: Power-up All: Power-up
1 Initial state after power-up. Initial state after power-up. waiting for HDCP waiting for HDCP
authentication. authentication.

Writes REPEATER = 1 in RX_R1.

Retries until a proper acknowledge
frame is received. Note: This step
must be completed before the first
part of the authentication is started
between TX_B1 and RX_R1 by FC_B
2 — — —
(step 7). For example, to satisfy this
requirement, RX_R1 can be held at
power-down until FC_R is ready to
write the REPEATER bit. Alternatively,
FC_B can poll FC_R before starting
authentication.

______________________________________________________________________________________   35
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 14. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First
MAX9265

and Second Parts of the HDCP Authentication Protocol (continued)

GMSL
SERIALIZER
DESERIALIZER
NO. µC_B µC_R (TX_B1, TX_R1,
(RX_R1, RX_D1,
TX_R2)
RX_D2)

Ensures that the A/V data not requir-

ing protection (low-value content)
is available at TX_B1 inputs (such
as blue or informative screen). RX_R1: Locks to
TX_B1: Starts
Alternatively, the FORCE_VIDEO incoming data
serialization and
3 and FORCE_AUDIO bits of TX_B1 — stream and out-
transmits low-value
can be used to mask the A/V data puts low-value
content A/V data.
input of TX_B1. Starts the link content A/V data.
between TX_B1 and RX_R1 by writ-
ing SEREN = H to TX_B1 or link
starts automatically if AUTOS is low.

TX_R1, TX_R2: RX_D1, RX_D2:

Starts all downstream links by writing
Starts serialization Locks to incoming
SEREN = H to TX_R1, TX_R2, or links
4 — and transmits low- data stream and
start automatically if AUTOS of the
value content A/V outputs low-value
transmitters are low.
data. content A/V data.

Reads the locked bit of RX_D1 and

ensures link between TX_R1 and
Reads the locked bit of RX_R1 and
RX_D1 is established. Reads the
5 ensures link between TX_B1 and — —
locked bit of RX_D2 and ensures link
RX_R1 is established.
between TX_R2 and RX_D2 is estab-
lished.

Writes 1 to the GPIO_0_FUNCTION

and GPIO_1_FUNCTION bits in
Optionally, writes a random-number RX_R1 to change GPIO functional-
6 — —
seed to TX_B1. ity to be used for HDCP purpose.
Optionally, writes a random-number
seed to TX_R1 and TX_R2.

TX_B1: According
Starts and completes first part of RX_R1: According
to the commands
the authentication protocol between to the commands
7 — from FC_B, gen-
TX_B1, RX_R1 (see steps 6–10 in from FC_B, com-
erates AN, com-
Table 11). putes R0’.
putes R0.

When GPIO_1 = 1 is detected, TX_R1, TX_R2: RX_D1, RX_D2:

starts and completes first part of According to the According to the
8 — the authentication protocol between commands from commands from
(TX_R1, RX_D1) and (TX_R2, RX_D2) FC_R, generates FC_R, computes
links (see steps 6–10 in Table 11). AN, computes R0. R0’.

36   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 14. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First

MAX9265
and Second Parts of the HDCP Authentication Protocol (continued)
GMSL
SERIALIZER
DESERIALIZER
NO. µC_B µC_R (TX_B1, TX_R1,
(RX_R1, RX_D1,
TX_R2)
RX_D2)

Waits for the VSYNC falling edge

and then enables encryption on the
(TX_B1, RX_R1) link. Full
TX_B1: Encryption RX_R1: Decryption
authentication is not complete yet
is enabled after is enabled after
9 so it ensures A/V content that needs —
the next VSYNC the next VSYNC
protection is not transmitted. Since
falling edge. falling edge.
REPEATER = 1 was read from
RX_R1, the second part of authenti-
cation is required.

TX_R1, TX_R2: RX_D1, RX_D2:

When GPIO_0 = 1 is detected, Encryption is Decryption is
10 — enables encryption on the (TX_R1, enabled after the enabled after the
RX_D1) and (TX_R2, RX_D2) links. next VSYNC falling next VSYNC falling
edge. edge.

RX_R1: Control
Blocks control channel from FC_B channel from the
side by setting REVCCEN = serializer side
11 FWDCCEN = 0 in RX_R1. Retries — (TX_B1) is blocked
until the proper acknowledge frame after FWDCCEN =
is received. REVCCEN = 0 is
written.

RX_R1: Triggered
Waits for some time to allow FC_R to by FC_R’s write of
make the KSV List ready in RX_R1. Writes BKSVs of RX_D1 and RX_D2 BINFO, calculates
12 Then polls (reads) the KSV_LIST_ to KSV List in RX_R1. Then calculates — hash value (V’)
READY bit of RX_R1 regularly until and writes BINFO register of RX_R1. on the KSV list,
the proper acknowledge frame is BINFO, and the
received and bit is read as 1. secret value M0’.

RX_R1: Control
Writes 1 to the KSV_LIST_READY bit channel from the
of RX_R1 and then unblocks control serializer side (TX_
13 channel from FC_B side by set- — B1) is unblocked
ting REVCCEN = FWDCCEN = 1 in after FWDCCEN =
RX_R1. REVCCEN = 1 is
written.

______________________________________________________________________________________   37
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 14. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First
MAX9265

and Second Parts of the HDCP Authentication Protocol (continued)

GMSL
SERIALIZER
DESERIALIZER
NO. µC_B µC_R (TX_B1, TX_R1,
(RX_R1, RX_D1,
TX_R2)
RX_D2)
Reads the KSV List and BINFO from TX_B1: Triggered
RX_R1 and writes them to TX_B1. If by FC_B’s write of
any of the MAX_DEVS_EXCEEDED BINFO, calculates
14 or MAX_CASCADE_EXCEEDED bits — hash value (V) —
is 1, then authentication fails. Note: on the KSV list,
BINFO must be written after the KSV BINFO, and the
List. secret value M0.

Reads V from TX_B1 and V’ from

RX_R1. If they match, continues with
15 — — —
authentication; otherwise, retries up
to two more times.
Searches for each KSV in the KSV
16 List and BKSV of RX_R1 in the Key — — —
Revocation List.
If keys are not revoked, second part
17 of authentication protocol is com- — — —
pleted.
All: Perform HDCP All: Perform HDCP
Starts transmission of the A/V con-
18 — encryption on high- decryption on high-
tent that needs protection.
value A/V data. value A/V data.

Applications Information are set to high. However, if the CDS pin of the serializer
is low and the same pin of the GMSL deserializer is high,
Self PRBS Test then the serializer/GMSL deserializer connect to both
The serializer/GMSL deserializer link includes a PRBS FCs simultaneously. In such a case, the FCs on either
pattern generator and bit-error verification function. First, side can communicate with the serializer and GMSL.
disable the glitch filters (set DISVSFILT, DISHSFILT to 1) Contentions of the control link can happen if the FCs on
in the GMSL deserializer. Next, disable VSYNC/HSYNC both sides are using the link at the same time. The seri-
inversion in both the serializer and GMSL deserialzer alizer/GMSL deserializer do not provide the solution for
(set INVVSYNC, INVHSYNC to 0). Then, set PRBSEN = 1 contention avoidance. The serializer/GMSL deserializer
(0x04, D5) in the serializer and then the GMSL deserial- do not send an acknowledge frame when communica-
izer to start the PRBS test. Set PRBSEN = 0 (0x04, D5) tion fails due to contention. Users can always implement
first in the GMSL deserializer and then the serializer to a higher layer protocol to avoid the contention. In addi-
exit the PRBS self test. tion, if UART communication across the serial link is not
Microcontrollers on Both Sides of the required, the FCs can disable the forward and reverse
GMSL Link (Dual µC Control) control channel through the FWDCCEN and REVCCEN
Usually the microcontroller is either on the serializer side bits (0x04, D[1:0]) in the serializer/GMSL deserializer.
for video-display applications or on the GMSL deserial- UART communication across the serial link is stopped
izer side for image-sensing applications. For the former and contention between FCs no longer occurs. During
case, both the CDS pins of the serializer/GMSL deserial- dual FC operation, if one of the CDS pins on either side
izer are set to low, and for the later case, the CDS pins changes state, the link resumes the corresponding state
described in the Link Startup Procedure section.

38   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
As an example of dual FC use in an image-sensing appli- accurately tracks the LOCK status of the video link.

MAX9265
cation, the serializer can be in sleep mode and waiting LOCK asserts for video link only and not for the configu-
for wake-up by the GMSL deserializer. After wake-up, ration link.
the serializer-side FC sets the serializer’s CDS pin low
Software Programming of the
and assumes master control of the serializer’s registers.
Device Addresses
Jitter-Filtering PLL Both the serializer and GMSL deserializer have software-
In some applications, the LVDS input clock to the serial- programmable device addresses. This allows multiple
izer (RXCLKIN_) includes noise, which reduces link reli- GMSL devices, along with I2C peripherals to coexist on
ability. The serializer has a narrowband jitter-filtering PLL the same control channel. The serializer device address
to attenuate frequency components outside the PLL’s is stored in registers 0x00 of each device, while the
bandwidth (< 100kHz, typ). Enable the jitter-filtering PLL deserializer device address is stored in register 0x01 of
by setting DISFPLL = 0 (0x05, D6). each device. To change the device address, first write
to the device whose address changes (register 0x00 of
Changing the Clock Frequency the serializer for serializer device address change, or
Both the video clock rate (fRXCLKIN_) and the control-
register 0x01 of the GMSL deserializer for deserializer
channel clock rate (fUART) can be changed on-the-fly
device address change). Then write the same address
to support applications with multiple clock speeds. It is
into the corresponding register on the other device
recommended to enable the serial link after the video
(register 0x00 of the GMSL deserializer for serializer
clock stabilizes. To recalibrate any automatic settings
device address change, or register 0x01 of the serializer
if a clean frequency change cannot be guaranteed,
for deserializer device address change).
stop the video clock for 5Fs and restart the serial link
or toggle SEREN after each change in the video clock 3-Level Inputs for Default Device Address
frequency. The reverse control channel remains unavail- ADD0 and ADD1 are 3-level inputs that control the serial-
able for 350Fs after serial link start or stop. Limit on-the- izer’s default device slave addresses (Table 2). Connect
fly changes in fUART to factors of less than 3.5 at a time ADD0/ADD1 through a pullup resistor to IOVDD, a
to ensure that the device recognizes the UART sync pulldown resistor to GND, or a high-impedance connec-
pattern. For example, when lowering the UART frequen- tion. For digital control, use three-state logic to drive the
cy from 1Mbps to 100kbps, first send data at 333kbps 3-level logic inputs.
and then at 100kbps to have reduction ratios of 3 and ADD0/ADD1 set the device addresses in the serializer
3.333, respectively. only and not the GMSL deserializer. Set the GMSL dese-
Do not interrupt RXCLKIN or change its frequency while rializer’s ADD0/ADD1 inputs to the same settings as the
encryption is enabled. Otherwise HDCP synchronization serializer. Alternatively, write to register 0x00 and 0x01 of
is lost and authentication must be repeated. To change the GMSL deserializer to reflect any changes made due
the RXCLKIN_ frequency, stop the high-value content to the 3-level inputs.
A/V data. Then disable encryption in the serializer/GMSL
Configuration Blocking
deserializer within the same VSYNC cycle—encryption
The serializer can block changes to its non-HDCP
stops at the next VSYNC falling edge. RXCLKIN can now
registers. Set CFGBLOCK to make all non-HDCP
be changed/stopped. Reenable encryption before send-
registers as read only. Once set, the registers remain
ing any high-value content A/V data.
blocked until the supplies are removed or until PWDN
Fast Detection of Loss-of-Synchronization is low.
A measure of link quality is the recovery time from loss
Backward Compatibility
of HDCP synchronization. With the GMSL, loss of GMSL
The serializer is backward compatible with the non-
lock usually accompanies a loss of HDCP sync. The host
HDCP MAX9249 serializer, with the following exceptions:
can be quickly notified of loss-of-lock by connecting the
GMSL deserializer LOCK output to the INT input. If other • Address pins: The ADD0 and ADD1 pins on the
sources use the interrupt input, such as a touch-screen serializer are the reserved pins on the MAX9249
controller, the FC can implement a routine to distin- serializer. Connect ADD0 and ADD1 to GND to set
guish between interrupts from loss-of-sync and normal the serializer’s default device addresses to the same
interrupts. Reverse control-channel communication does values as the MAX9249 serializer.
not require an active forward link to operate and

______________________________________________________________________________________   39
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
• First UART packet delay: The FC must wait 2.7ms Internal Input Pulldowns
MAX9265

after power-up before sending the first UART packet The control and configuration inputs on the serializer/
to the serializer. This delay is < 200Fs for the GMSL deserializer include a pulldown resistor to GND.
MAX9249 serializer. Pulldowns are disabled when the device is shut down
The pinouts and packages are otherwise the same for PWDN = low) or put into sleep mode. Keep all inputs
both devices. See Table 3 and the Pin Description for driven or use external pullup/pulldown resistors to pre-
backward-compatible pin mapping. vent additional current consumption and undesired con-
figuration due to undefined inputs.
Key Memory
Each device has a unique HDCP key set that is stored Choosing I2C/UART Pullup Resistors
in secure on-chip nonvolatile memory (NVM). The HDCP Both I2C/UART open-drain lines require pullup resistors
key set consists of forty 56-bit private keys and one to provide a logic-high level. There are tradeoffs between
40-bit public key. The NVM is qualified for automotive power dissipation and speed, and a compromise made
applications. in choosing pullup resistor values. Every device connect-
ed to the bus introduces some capacitance even when
Line-Fault Detection the device is not in operation. I2C specifies 300ns rise
The line-fault detector in the serializer monitors for line times to go from low to high (30% to 70%) for fast mode,
failures such as short to ground, short to battery, and which is defined for data rates up to 400kbps (see the
open link for system fault diagnosis. Figure 3 shows the I2C specifications in the Electrical Characteristics table
required external resistor connections. LFLT = low when for details). To meet the fast-mode rise-time require-
a line fault is detected and LFLT goes high when the line ment, choose the pullup resistors so that rise time tR =
returns to normal. The line-fault type is stored in 0x08 0.85 x RPULLUP x CBUS < 300ns. The waveforms are not
D[3:0] of the serializer. Filter LFLT with the FC to reduce recognized if the transition time becomes too slow. The
the detector’s susceptibility to short ground shifts. The serializer/GMSL deserializer supports I2C/UART rates up
fault detector threshold voltages are referenced to the to 1Mbps.
serializer ground. Additional passive components set the
DC level of the cable (Figure 3). If the serializer and GMSL AC-Coupling
deserializer grounds are different, the link DC voltage dur- AC-coupling isolates the receiver from DC voltages up to
ing normal operation can vary and cross one of the fault- the voltage rating of the capacitor. Four capacitors (two
detection thresholds. For the fault-detection circuit, select at the serializer output and two at the deserializer input)
the resistor’s power rating to handle a short to the battery. are needed for proper link operation and to provide
protection if either end of the cable is shorted to a high
To detect the short-together case, refer to Application
voltage. AC-coupling blocks low-frequency ground shifts
Note 4709: GMSL Line-Fault Detection.
and low-frequency common-mode noise.
Table 15 lists the mapping for line-fault types.

Table 15. Line-Fault Mapping

REGISTER ADDRESS BITS NAME VALUE LINE FAULT TYPE
00 Negative cable wire shorted to supply voltage.
01 Negative cable wire shorted to ground.
D[3:2] LFNEG
10 Normal operation.
11 Negative cable wire disconnected.
0x08
00 Positive cable wire shorted to supply voltage.
01 Positive cable wire shorted to ground.
D[1:0] LFPOS
10 Normal operation.
11 Positive cable wire disconnected.
*For the short-together case, refer to Application Note 4709: GMSL Line-Fault Detection.

40   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Selection of AC-Coupling Capacitors canceling effects. Balanced cables pick up noise as

MAX9265
Voltage droop and the digital sum variation (DSV) of common mode rejected by the CML receiver. Table 16
transmitted symbols cause signal transitions to start lists the suggested cables and connectors used in the
from different voltage levels. Because the transition time GMSL link.
is finite, starting the signal transition from different volt-
Board Layout
age levels causes timing jitter. Choose the time constant
Separate the digital signals and CML/LVDS high-speed
for an AC-coupled link to reduce droop and jitter to an
signals to prevent crosstalk. Use a four-layer PCB with
acceptable level. The RC network for an AC-coupled link
separate layers for power, ground, CML/LVDS, and
consists of the CML receiver termination resistor (RTR),
digital signals. Lay out PCB traces close to each other
the CML driver termination resistor (RTD), and the series
for a 100I differential characteristic impedance. The
AC-coupling capacitors (C). The RC time constant for
trace dimensions depend on the type of trace used
four equal-value series capacitors is (C x (RTD + RTR))/4.
(microstrip or stripline). Note that two 50I PCB traces
RTD and RTR are required to match the transmission
do not have 100I differential impedance when brought
line impedance (usually 100I). This leaves the capaci-
close together—the impedance goes down when the
tor selection to change the system time constant. Use
traces are brought closer.
at least 0.2FF high-frequency surface-mount ceramic
capacitors, with sufficient voltage rating to withstand a Route the PCB traces for a CML/LVDS channel (there
short to battery, to pass the lower speed reverse control- are two conductors per CML/LVDS channel) in parallel to
channel signal. Use capacitors with a case size less than maintain the differential characteristic impedance. Avoid
3.2mm x 1.6mm to have lower parasitic effects to the vias. Keep PCB traces that make up a differential pair
high-speed signal. equal length to avoid skew within the differential pair.

Power-Supply Circuits and Bypassing ESD Protection

The serializer uses an AVDD and DVDD of 1.7V to 1.9V, The serializer’s ESD tolerance is rated for Human Body
and an LVDSVDD of 3.0V to 3.6V. All single-ended inputs Model, IEC 61000-4-2, and ISO 10605. The ISO 10605
and outputs derive power from an IOVDD of 1.7V to 3.6V, and IEC 61000-4-2 standards specify ESD tolerance
which scale with IOVDD. Proper voltage-supply bypass- for electronic systems. CML/LVDS I/O are tested for
ing is essential for high-frequency circuit stability. ISO 10605 ESD protection and IEC 61000-4-2 ESD
protection. All pins are tested for the Human Body Model.
Cables and Connectors The Human Body Model discharge components are CS
Interconnect for CML typically has a differential imped- = 100pF and RD = 1.5kI (Figure 26). The IEC 61000-4-2
ance of 100I. Use cables and connectors that have discharge components are CS = 150pF and RD = 330I
matched differential impedance to minimize impedance (Figure 27). The ISO 10605 discharge components are
discontinuities. Twisted-pair and shielded twisted-pair CS = 330pF and RD = 2kI (Figure 28).
cables tend to generate less EMI due to magnetic-field

Table 16. Suggested Connectors and

Cables for GMSL RD
1MI 1.5kI
VENDOR CONNECTOR CABLE
Rosenberger D4S10A-40ML5-Z Dacar 538 CHARGE-CURRENT- DISCHARGE
Nissei GT11L-2S F-2WME AWG28 LIMIT RESISTOR RESISTANCE
HIGH-
JAE MX38-FF A-BW-Lxxxxx CS STORAGE DEVICE
VOLTAGE
100pF CAPACITOR UNDER
DC
TEST
SOURCE

Figure 26. Human Body Model ESD Test Circuit

______________________________________________________________________________________   41
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
MAX9265

RD RD
330I 2kI

CHARGE-CURRENT- DISCHARGE CHARGE-CURRENT- DISCHARGE

LIMIT RESISTOR RESISTANCE LIMIT RESISTOR RESISTANCE
HIGH- HIGH-
CS STORAGE DEVICE CS STORAGE DEVICE
VOLTAGE VOLTAGE
150pF CAPACITOR UNDER 330pF CAPACITOR UNDER
DC DC
TEST TEST
SOURCE SOURCE

Figure 27. IEC 61000-4-2 Contact Discharge ESD Test Circuit Figure 28. ISO 10605 Contact Discharge ESD Test Circuit

Table 17. Serializer GMSL Core Register Table (see Table 1)

REGISTER DEFAULT
BITS NAME VALUE FUNCTION
ADDRESS VALUE
Serializer device address. Power-up default
D[7:1] SERID XXXXXXX address determined by ADD0 and ADD1 XX00XX0
0x00 (see Table 2).
0 Normal operation.
D0 CFGBLOCK 0
1 Registers 0x00 to 0x1F are read only.
Deserializer device address. Power-up default
D[7:1] DESID XXXXXXX address determined by ADD0 and ADD1 XX01XX0
0x01
(see Table 2).
D0 — 0 Reserved. 0
No spread spectrum. Power-up default when
000
SSEN = low.
±0.5% spread spectrum. Power-up default when
001
SSEN = high.
010 ±1.5% spread spectrum.
D[7:5] SS 000, 001
011 ±2% spread spectrum.
100 No spread spectrum.
101 ±1% spread spectrum.
110 ±3% spread spectrum.
111 ±4% spread spectrum.
0x02
0 Disable I2S channel.
D4 AUDIOEN 1
1 Enable I2S channel.
00 12.5MHz to 25MHz pixel clock.
01 25MHz to 50MHz pixel clock.
D[3:2] PRNG 11
10 50MHz to 104MHz pixel clock.
11 Automatically detect the pixel clock range.
00 0.5Gbps to 1Gbps serial-bit rate.
01 1Gbps to 2Gps serial-bit rate.
D[1:0] SRNG 11
10 2Gbps to 3.125Gbps serial-bit rate.
11 Automatically detect serial-bit rate.

42   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 17. Serializer GMSL Core Register Table (see Table 1) (continued)

MAX9265
REGISTER DEFAULT
BITS NAME VALUE FUNCTION
ADDRESS VALUE
Calibrate spread-modulation rate only once after
00
locking.
Calibrate spread-modulation rate every 2ms after
01
locking.
D[7:6] AUTOFM 00
Calibrate spread-modulation rate every 16ms after
10
0x03 locking.
Calibrate spread-modulation rate every 256ms after
11
locking.
000000 Autocalibrate sawtooth divider.
D[5:0] SDIV Manual SDIV setting. See the Manual Programming 000000
XXXXXX
of the Spread-Spectrum Divider section.

Disable serial link. Power-up default when AUTOS

= high. Reverse control-channel communication
0
remains unavailable for 350Fs after the serializer
starts/stops the serial link.
D7 SEREN 0, 1
Enable serial link. Power-up default when AUTOS
= low. Reverse control-channel communication
1
remains unavailable for 350Fs after the serializer
starts/stops the serial link.
0 Disable configuration link.
D6 CLINKEN 0
1 Enable configuration link.
0 Disable PRBS test.
D5 PRBSEN 0
1 Enable PRBS test.
Normal mode. Default value depends on the CDS
0
0x04 and AUTOS pin values at power-up).
D4 SLEEP 0, 1
Activate sleep mode. Default value depends on the
1
CDS and AUTOS pin values at power-up.
00 Base mode uses I2C peripheral interface.
D[3:2] INTTYPE 01 Base mode uses UART peripheral interface. 00
10, 11 Base mode peripheral interface disabled.
Disable reverse control channel from deserializer
0
(receiving).
D1 REVCCEN 1
Enable reverse control channel from deserializer
1
(receiving).
Disable forward control channel to deserializer
0
(sending).
D0 FWDCCEN 1
Enable forward control channel to deserializer
1
(sending).

______________________________________________________________________________________   43
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 17. Serializer GMSL Core Register Table (see Table 1) (continued)
MAX9265

REGISTER DEFAULT
BITS NAME VALUE FUNCTION
ADDRESS VALUE
0 I2C conversion sends the register address.
D7 I2CMETHOD Disable sending of I2C register address (command- 0
1
byte-only mode).
0 Filter PLL active.
D6 DISFPLL 1
1 Filter PLL disabled.
00 Do not use.
01 200mV CML signal level.
D[5:4] CMLLVL 11
10 300mV CML signal level.
11 400mV CML signal level.
0000 Preemphasis off.
0001 -1.2dB preemphasis.
0010 -2.5dB preemphasis.
0x05 0011 -4.1dB preemphasis.
0100 -6.0dB preemphasis.
0101 Do not use.
0110 Do not use.
0111 Do not use.
D[3:0] PREEMP 0000
1000 1.1dB preemphasis.
1001 2.2dB preemphasis.
1010 3.3dB preemphasis.
1011 4.4dB preemphasis.
1100 6.0dB preemphasis.
1101 8.0dB preemphasis.
1110 10.5dB preemphasis.
1111 14.0dB preemphasis.
0x06 D[7:0] — 01000000 Reserved. 01000000
0x07 D[7:0] — 00100010 Reserved. 00100010
0000
D[7:4] — 0000 Reserved.
(read only)
00 Negative cable wire shorted to supply voltage.
01 Negative cable wire shorted to ground. 10
D[3:2] LFNEG
10 Normal operation. (read only)
0x08
11 Negative cable wire disconnected.
00 Positive cable wire shorted to supply voltage.
01 Positive cable wire shorted to ground. 10
D[1:0] LFPOS
10 Normal operation. (read only)
11 Positive cable wire disconnected.
0x0C D[7:0] — 01110000 Reserved. 01110000

44   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 17. Serializer GMSL Core Register Table (see Table 1) (continued)

MAX9265
REGISTER DEFAULT
BITS NAME VALUE FUNCTION
ADDRESS VALUE
0 Set INT low when SETINT transitions from 1 to 0.
D7 SETINT 0
1 Set INT high when SETINT transitions from 0 to 1.
0 Serializer does not invert VSYNC.
D6 INVVSYNC 0
1 Serializer inverts VSYNC.
0 Serializer does not invert HSYNC.
D5 INVHSYNC 0
1 Serializer inverts HSYNC.
D[4:0] — 00000 Reserved. 00000
0 RES (LVDS interface) mapped to DIN27.
D4 DISRES 0
1 CNTL1 mapped to DIN27.
0000 Adjust x7PLL clock skew +50ps.
0001 Adjust x7PLL clock skew +100ps.
0010 Adjust x7PLL clock skew +200ps.
0x0D 0011 Adjust x7PLL clock skew +250ps.
0100 Adjust x7PLL clock skew +300ps.
0101 Adjust x7PLL clock skew +350ps.
0110 Adjust x7PLL clock skew +400ps.
0111 Do not use.
D[3:0] SKEWADJ 1111
1000 Adjust x7PLL clock skew +50ps.
1001 Adjust x7PLL clock skew +100ps.
1010 Adjust x7PLL clock skew +200ps.
1011 Adjust x7PLL clock skew +250ps.
1100 Adjust x7PLL clock skew +300ps.
1101 Adjust x7PLL clock skew +350ps.
1110 Adjust x7PLL clock skew +400ps.
1111 No x7PLL clock skew adjustment.
00000111
0x1E D[7:0] ID 00000111 Device identifier (MAX9265 = 0x07).
(read only)
000
D[7:5] — 000 Reserved.
(read only)
0x1F 0 Not HDCP capable. 1
D4 CAPS
1 HDCP capable. (read only)
D[3:0] REVISION XXXX Device revision. (read only)

______________________________________________________________________________________   45
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 18. Serializer HDCP Register Table (see Table 1)
MAX9265

REGISTER SIZE READ/ DEFAULT VALUE

NAME FUNCTION
ADDRESS (BYTES) WRITE (hex)
0x80 to 0x84 5 BKSV Read/write HDCP receiver KSV 0x0000000000
RI (read only) of the transmitter when
EN_INT_COMP = 0
0x85 to 0x86 2 RI/RI’ Read/write 0x0000
RI’ (read/write) of the receiver when
EN_INT_COMP = 1

PJ (read only) of the transmitter when

EN_INT_COMP = 0
0x87 1 PJ/PJ’ Read/write 0x00
PJ’ (read/write) of the receiver when
EN_INT_COMP = 1
0x88 to 0x8F 8 AN Read only Session random number (Read only)
0x90 to 0x94 5 AKSV Read only HDCP transmitter KSV (Read only)
D7 = PD_HDCP
1 = Power down HDCP circuits
0 = HDCP circuits normal
D6 = EN_INT_COMP
1 = Internal comparison mode
0 = FC comparison mode
D5 = FORCE_AUDIO
1 = Force audio data to 0
0 = Normal operation
D4 = FORCE_VIDEO
1 = Force video data DFORCE value
0 = Normal operation

0x95 1 ACTRL Read/write D3 = RESET_HDCP 0x00

1 = Reset HDCP circuits
Automatically set to 0 upon completion
0 = Normal operation

D2 = START_AUTHENTICATION
1 = Start authentication
Automatically set to 0 once authentication starts
0 = Normal operation

D1 = VSYNC_DET
1 = Internal falling edge on VSYNC detected
0 = No falling edge detected
D0 = ENCRYPTION_ENABLE
1 = Enable encryption
0 = Disable encryption

46   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 18. Serializer HDCP Register Table (see Table 1) (continued)

MAX9265
REGISTER SIZE READ/ DEFAULT VALUE
NAME FUNCTION
ADDRESS (BYTES) WRITE (hex)
D[7:4] = Reserved
D3 = V_MATCHED
1 = V matches V’ (when EN_INT_COMP = 1)
0 = V does not match V’ or EN_INT_COMP = 0
D2 = PJ_MATCHED
1 = PJ matches PJ’ (when EN_INT_COMP = 1)
0 = PJ does not match PJ’ or EN_INT_COMP = 0 0x00
0x96 1 ASTATUS Read only
(read only)
D1 = R0_RI_MATCHED
1 = RI matches RI’ (when EN_INT_COMP = 1)
0 = RI does not match RI’ or EN_INT_COMP = 0
D0 = BKSV_INVALID
1 = BKSV is not valid
0 = BKSV is valid
D[7:1] = RESERVED
D0 = REPEATER
0x97 1 BCAPS Read/write 0x00
1 = Set to 1 if device is a repeater
0 = Set to 0 if device is not a repeater
Internal random number generator optional seed
0x98 to 0x9C 5 ASEED Read/write 0x0000000000
value

Forced video data transmitted when

FORCE_VIDEO = 1
0x9D to 0x9F 3 DFORCE Read/write R[7:0] = DFORCE[7:0] 0x000000
G[7:0] = DFORCE[15:8]
B[7:0] = DFORCE[23:16]

H0 part of SHA-1 hash value

V (read only) of the transmitter when
V.H0,
0xA0 to 0xA3 4 Read/write EN_INT_COMP = 0 0x00000000
V’.H0
V’ (read/write) of the receiver when
EN_INT_COMP = 1

H1 part of SHA-1 hash value

V (read only) of the transmitter when
V.H1,
0xA4 to 0xA7 4 Read/write EN_INT_COMP = 0 0x00000000
V’.H1
V’ (read/write) of the receiver when
EN_INT_COMP = 1

H2 part of SHA-1 hash value

V (read only) of the transmitter when
V.H2,
0xA8 to 0xAB 4 Read/write EN_INT_COMP = 0 0x00000000
V’.H2
V’ (read/write) of the receiver when
EN_INT_COMP = 1

______________________________________________________________________________________   47
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 18. Serializer HDCP Register Table (see Table 1) (continued)
MAX9265

REGISTER SIZE READ/ DEFAULT VALUE

NAME FUNCTION
ADDRESS (BYTES) WRITE (hex)

H3 part of SHA-1 hash value

V (read only) of the transmitter when
V.H3,
0xAC to 0xAF 4 Read/write EN_INT_COMP = 0 0x00000000
V’.H3
V’ (read/write) of the receiver when
EN_INT_COMP = 1

H4 part of SHA-1 hash value

V (read only) of the transmitter when
V.H4,
0xB0 to 0xB3 4 Read/write EN_INT_COMP = 0 0x00000000
V’.H4
V’ (read/write) of the receiver when
EN_INT_COMP = 1
D[15:12] = Reserved
D11 = MAX_CASCADE_EXCEEDED
1 = Set to one if more than 7 cascaded devices
attached
0 = Set to zero if 7 or fewer cascaded devices
attached
0xB4 to 0xB5 2 BINFO Read/write D[10:8] = DEPTH 0x0000
Depth of cascaded devices
D7 = MAX_DEVS_EXCEEDED
1 = Set to one if more than 14 devices attached
0 = Set to zero if 14 or fewer devices attached
D[6:0] = DEVICE_COUNT
Number of devices attached
0xB6 1 GPMEM Read/write General-purpose memory byte 0x00
0xB7 to 0xB9 3 — Read only Reserved 0x000000
List of KSV’s downstream repeaters and
0xBA to 0xFF 70 KSV_LIST Read/write All zero
receivers (maximum of 14 devices)

48   �������������������������������������������������������������������������������������
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Typical Application Circuit

MAX9265
PCLKOUT PCLK
DOUT[17:0] RGB
DOUT18/HS HSYNC
TXCLK+/- RXCLKIN+/- DOUT19/VS VSYNC
TX0+/- TO TX2+/- RXIN0+/- TO RXIN2+/- DOUT20 DE
GPU CDS 45kI 45kI CDS DISPLAY
AUTOS

LMN1

ECU LMN0
MAX9264
5kI 5kI
MAX9265
TO PERIPHERALS
OUT+ IN+ INT
TX RX/SDA RX/SDA
UART OUT- IN-
RX TX/SCL TX/SCL
50kI 50kI
LFLT LFLT SCL
ADD0 SDA
INT INT LOCK
MS MS ADD1 WS WS
SCK
WS WS SD MAX9850
AUDIO SCK SCK
SCK
SD SD/CNTL0
SD MCLK
PLL
NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.
X1 OUT
VIDEO-DISPLAY APPLICATION

Chip Information Package Information

PROCESS: BiCMOS For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.

PACKAGE PACKAGE OUTLINE LAND

TYPE CODE NO. PATTERN NO.

48 TQFP-EP C48E+8 21-0065 90-0138

______________________________________________________________________________________   49
 HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Revision History
MAX9265

REVISION REVISION PAGES

DESCRIPTION
NUMBER DATE CHANGED
0 12/10 Initial release —

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
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