LLC_series_resonant_converter_with_PID_controller_for_battery_charging_application
LLC_series_resonant_converter_with_PID_controller_for_battery_charging_application
S1
Rectifier
DC NP
Vin NS
Cr Lr CO RL
LCC Resonant Tank LLC Resonant Tank
S2 Lm NS
Fig. 2. LCC and LLC resonant tank.
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a soft commutation of the rectifier diodes. The resonance period
is equal to the switching period and the resonant current is sine
wave. The operation at series resonance is only a single point
operation, to cover both line and load variations, the switching
frequency will have to be adjusted away from the resonance
frequency [19].
Operation below Resonance: Below resonance operation
handles the undervoltage condition due to abrupt load increase Fig. 4. AC equivalent circuit of the LLC resonant converter.
and provides the converter with specified holdup capability. For
fsw < fr1 the resonant current Ir falls equal to the magnetizing
current Im before the end of switching pulse width, causing the
power transfer to the load to be ceased. This is because the
resonance duration being smaller than the pulse width.
Operation below fr1 achieves primary ZVS and ZCS of the
rectifier diodes on the secondary side. The rectifier diodes are in
Gain G
discontinuous current mode and require more circulating current
in the resonant circuit to deliver the same amount of energy to
the load causing conduction losses in both the primary and the
secondary sides. The primary ZVS may be lost if the switching
frequency becomes low than fr2 resulting in high switching
losses and several associated issues [19].
Operation above Resonance: The above resonance operation is
used to handle overvoltage condition due to abrupt decrease in
load. In this mode fsw > fr1 and there is a smaller circulating fr2 fr1
current in the resonant circuit. This reduces conduction loss Normalized frequency fn
because the resonant circuit’s current is in continuous-current Fig. 5. Operating regions of LLC series resonant converter.
mode, resulting in less RMS current for the same amount of load.
In this mode the resonance period is greater than the switching An approximate relationship between gain and normalized
period. The reverse recovery losses exist because the rectifier frequency is given in [21] as:
diodes are not softly commutated. The operation above fr1 can
still achieve primary ZVS and causes significant frequency (4)
increase under light-load conditions [19].
III. AC EQUIVALENT CIRCUIT OF THE LLC RESONANT Equation (4) gives the approximated value of fsw at required
output voltage which can be used as initial frequency of VCO,
CONVERTER AND ITS VOLTAGE GAIN
and it will be further adjusted by PID controller. Using (3) the
The LLC resonant converter’s nonlinear circuit is replaced DC characteristics of LLC resonant converter can be derived,
by a linear and time-invariant circuit, based on the first- and are divided into ZCS and ZVS regions, as illustrated in Fig.
harmonic approximation (FHA) approach as shown in Fig. 4 [1]. 5 [22]. Below fr2 is the ZCS region and is not preferred for power
This approximation model simplifies the analysis of the main MOSFET application due to the loss of ZVS operation [21].
complex circuit and illustrates variations of the output voltage
by changing the load and frequency. IV. CIRCUIT OPERATION
The voltage gain of the converter is given as follows [10]: In one switching cycle the operation of the LLC resonant
converter in Fig. 3 can be divided into four modes [23] as shown
in Fig. 7. Only first two modes in the half switch cycle are
(3) explained. For the next half cycle, operation is similar and is
omitted here. The equivalent circuit for these two modes is
shown in Fig. 6.
Mode 1: This mode starts when the voltage across S1
with the parameters: becomes zero before it turns on. When S1 is turned on, the
resonant current Ir starts flowing through it and increases
sinusoidal-type due to resonance between Lr and Cr The
Quality factor: magnetizing inductance Lm is clamped to the output voltage
nV0 and is charged linearly. The magnetizing current Im
where with P0 as output power. increases linearly and Lm does not participate in resonance.
The rectifier diode D1 is turned on under ZCS condition and
Normalized frequency: delivers energy to the load. This mode ends when Ir falls
equal to Im and energy transfer to the load is ceased resulting
diode current ID1 equal to zero.
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S1 Vgs1 Vgs2
D1 0
Ir
+ NP Vds1
_ NS ID1
Vin Cr Lr RL
Im Co
S2 Lm
NS
Vcr
D2 0
(a) Mode 1 IL
S1
0
D1
Ir Im
+ NP
_ NS
Vin Cr Lr RL
Im Co
S2 Lm
NS
D2 ID1 ID2
(b) Mode 2
Fig. 6. Equivalent circuits for first two modes of operation.
0
Mode 2: This mode starts when Ir = Im and continues until
Mode 1 Mode 2 Mode 3 Mode 4
both currents remain equal. During this mode, output is
Fig. 7. Simulation waveforms for modes of operation.
separated from the input and no power is transferred to the
load from the input side. Lm becomes in series with Lr & Cr Step 3. Choose the resonance frequency fr1 and find
participating in resonance operation and, the current
equivalent AC resistance Rac, input impedance Z0 and
circulates in the primary side. This mode ends after S1 is
turned off and voltage across it starts rising. the load resistance values as;
For the next half switching cycle operation is similar as above. Rac = n2R0
where,
V. DESIGN PROCEDURE
The converter specifications for the design are given as follows: Using values of Z0 and k calculate the tank parameters
Input DC Voltage range 380 V ~ 420 V. as:
Output Voltage range 28 V ~ 72 V
LC Resonant frequency fr1 = 200 kHz
LLC Resonant frequency fr2 = 85.28 kHz Step 4. Find the minimum and maximum switching
Switching frequency range 94.6 kHz ~ 226.6 kHz frequencies from the gain plot.
The design procedure for the converter is summarized in the The gain plot is shown in Fig. 8. Using above steps with n = 9,
following steps [19]. Q = 0.15, and k = 4.5 the tank parameters are calculated as:
Cr = 34.2 µF, Lr = 1.855 µF, and Lm = 8.356 µH.
Step 1. Calculate the transformer’s turns ratio, minimum and
maximum gain values [20] using the following
equations:
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VI. SIMULATION RESULTS Line Variation
Vref
38 Vo
Voltage
32
50
Vref
Vo
48
Voltage
42
for MOSFETs with required fixed duty cycle. 40
38
36
34
0.024 0.0245 0.025 0.0255 0.026 0.0265 0.027 0.0275
Simulation Time
Line Variation
75
70
Vref
65 Vo
Vin/11
60
Voltage
55
50
45
40
35
70
65
55
Load Variation
50
28
45
26 Vref
40
Vo
22 Fig. 12. Voltage regulation with linear and step variations in reference signal at
20
different output voltage levels.
18
Vref
Vo
Io
Fig. 10 shows the performance of controller for 20%
16
3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
variation in load at 28V, 48V and 72V. It can be seen from the
Simulation Time
figure that the controller adjusted the load variations for both
-3
x 10
Load Variation
42
40
Voltage
34
and the controller’s response for the adjustment of effect. The
32
Vref input voltage was increase to maximum value of 420V and then
dropped down to 380V and then adjusted back to the nominal
30 Vo
Io
28
0.01 0.0105 0.011
Simulation Time
0.0115 0.012 0.0125
value of 400V. Figure shows the line variation at 28V, 48V and
Load Variation 72V and it can be seen the controller has adjusted the effect more
75
quickly at higher output voltage than the lower one. The output
70
Voltage was scaled by 1/11 in the figure.
65
60
Fig. 12 shows the output voltage regulation with step and
Voltage
55
linear changes in the reference signal at different voltage levels.
50
From the figure it can be seen that the output voltage follows the
45
Vref
Vo
reference signal in both step and linear variations. The controller
40
Io
has adjusted the output voltage according to the variations in
reference signal. For higher voltage level adjustment is quicker
0.0185 0.019 0.0195 0.02 0.0205 0.021 0.0215
Simulation Time
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than that of lower voltage level. In linear variation, the output [9] T. Duerbaum, “First harmonic approximation including design con-
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