Computers and Electrical Engineering 107 (2023) 108650

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Computers and Electrical Engineering

journal homepage: www.elsevier.com/locate/compeleceng

Trapezoidal reference-based single carrier pulse width modulation

method for multilevel converters with novel FPGA implementation✩
Fatih Eroğlu a ,∗, Mehmet Kurtoğlu b
a Electrical and Electronics Engineering Department, Gaziantep University, 27310 Sehitkamil, Gaziantep, Turkey
b Electrical and Electronics Engineering Department, Iskenderun Technical University, 31200 Iskenderun, Hatay, Turkey

ARTICLE INFO ABSTRACT

Keywords: Recent attention has focused on trapezoidal reference-based pulse width modulation (PWM)
Multilevel converters schemes in multilevel converters (MLCs) with easier implementation and better harmonic
Pulse width modulation performance. Nevertheless, these studies utilize trapezoidal reference only for multi carrier
FPGA implementation
PWM methods and details of FPGA implementation are not provided. This paper proposes
VHDL programming
a trapezoidal reference-based single carrier PWM (TSC-PWM) with its novel FPGA imple-
Power quality
mentation. Design parameters of TSC-PWM is determined such that harmonic performance
is maximized and architectural details of FPGA implementation of TSC-PWM are provided.
Results reveal that TSC-PWM significantly reduces the resource utilization compared to other
methods. Single-phase three-module cascaded H-bridge MLC (CHB-MLC) is established in both
simulation and experimental platforms. Results indicate that the TSC-PWM provides better
harmonic performance along with higher DC utilization ratio compared to other methods.
Moreover, both half-wave and quarter-wave symmetries are ensured with TSC-PWM.

1. Introduction

The past decade has seen an increased importance of multilevel converters (MLCs) in medium-high power applications [1]. Active
power filters [2], high-voltage DC transmission [3], medium-voltage motor drives [4], reactive power compensators [5], renewable
energy systems [6] and battery energy storage systems [7] can be counted among the most popular ones of such applications.
MLCs can be mainly divided into three categories: diode-clamped MLCs (DC-MLCs), flying-capacitor MLCs (FC-MLCs) and cascaded
H-bridge MLCs (CHB-MLCs) [8]. CHB-MLC consists of serially connected H-bridges (modules) and it is advantageous compared to
other topologies due to its properties like ease of control, less complexity and modular architecture [9]. Much of the current literature
on modulation of CHB-MLCs pays particular attention to carrier-based pulse width modulation (PWM) methods. Phase-shifted PWM
(PS-PWM) and level-shifted PWM (LS-PWM) are the most popular carrier-based PWM methods in the literature. Carriers in PS-PWM
have the same magnitude but they are displaced in phase. On the contrary, there are no phase-shifts between the carriers in LS-
PWM but they are displaced in magnitude [10]. LS-PWM methods can also be classified into three categories: phase-disposition
LS-PWM (PD-LS-PWM), phase-opposition-disposition LS-PWM (POD-LS-PWM), alternative phase-opposition-disposition LS-PWM
(APOD-LS-PWM) [11]. Previous studies have reported that LS-PWM provides output waveforms with better quality compared to
PS-PWM [12].
Utilization of digital signal processors (DSPs) and field programmable gate arrays (FGPAs) are key to implement PWM methods
digitally. Carrier-based PWM methods require large number of carriers to achieve higher number of levels at the output of CHB-MLC.

✩ This paper is for regular issues of CAEE. Reviews were processed by Area Editor Dr. E. Cabal-Yepez and recommended for publication.
∗ Corresponding author.
E-mail address: [email protected] (F. Eroğlu).

https://doi.org/10.1016/j.compeleceng.2023.108650
Received 2 December 2022; Received in revised form 15 February 2023; Accepted 16 February 2023
Available online 23 February 2023
0045-7906/© 2023 Elsevier Ltd. All rights reserved.
F. Eroğlu and M. Kurtoğlu Computers and Electrical Engineering 107 (2023) 108650

This increases the complexity of digital implementation of these methods in real time. It is hard to generate sufficient number of
gating signals in parallel by using DSPs as time synchronization become a problem [13]. On the other hand, FGPAs are able to
produce large number of gating signals in parallel corresponding to the levels of MLC with their high speed parallel processing
features. This is the most significant advantage of FPGAs compared to DSPs which is inherently employed to drive traditional two-
or three-level voltage source converters [14].
Reducing the complexity and resource utilization are critical aspects in real-time digital implementation of carrier-based PWM
methods. To achieve this purpose, a significant amount of research has been carried out on generating multilevel waveform at the
output of MLCs by utilizing a single carrier instead of multiple carriers. The main purpose of single carrier PWM (SC-PWM) methods
is to mimic the switching behavior LS-PWM. It is known that LS-PWM employs single reference signal along with multiple carriers to
generate gating signals for the modules of CHB-MLC. SC-PWM methods can be divided into two main categories: SC-PWM methods
that employ single reference signal [15–17] and SC-PWM methods that employ multiple reference signals [18–20]. Among these,
former method is more suitable for real-time digital applications due to simpler implementation and reduced resource utilization.
For single reference SC-PWM methods, raw reference signal is rescaled into the magnitude of the carrier. Then, a raw PWM is
obtained by comparing the rescaled reference signal to the carrier. After generating the raw PWM, a gate decoding approach is
employed to generate suitable gating signals for each module of CHB-MLC. In [15], masks that have previously been generated and
stored in a look-up table (LUT) are used for each module for gate decoding purpose. However, masks are created with a predefined
frequency. For this reason, some switching instants of PD-LS-PWM are not replicated successfully. A quantizer signal is employed
in [16] for gate decoding process to mimic the multilevel behavior of PD-LS-PWM and APOD-LS-PWM respectively. Raw reference
signal is used to generate different levels of PD-LS-PWM in [17] for gate decoding along with equal power sharing strategy. The
mutual aspects of all the above-mentioned studies are to utilize sinusoidal signal as the raw reference along with triangular carrier.
Generating sinusoidal reference and triangular carriers are challenging parts of real-time digital implementation of carrier based
PWM methods in FPGA [21]. In most recent studies, carriers are produced by using up-down counters while sinusoidal reference
signal is formed by storing the previously generated sinusoidal values into LUTs [14,22–24]. Aiming reduction in the memory
requirements, FPGA based implementation of the Coordinate Rotation Digital Computer (CORDIC) algorithm is proposed in [25,26]
to generate sinusoidal reference signal. Although this method is memory friendly, it is defined by a slower speed in comparison to
LUT based sinusoid generation.
Recently, researchers have shown an increased interest in trapezoidal reference signals in MLC applications due to its ease of
digital implementation and better output waveform quality [27–30]. Despite this interest, these studies only utilize trapezoidal
reference signal for multi carrier PWM methods. Moreover, real-time digital implementation of trapezoidal reference signal is held
by using microcontrollers [27,29] and FPGAs [28,30]. Trapezoidal reference signals are generated in a simulation platform and
external hardware description language (HDL) generators are used in [28] for FPGA implementation. On the other hand, previously
generated trapezoidal signal is stored in a LUT in [30] and architectural design is created by VHDL programming. Yet, it fails to
provide a comparison between sinusoidal and trapezoidal reference signals in terms of resource utilization within FPGA.
This paper proposes a trapezoidal reference based SC-PWM (TSC-PWM) along with its novel FPGA implementation for CHB-MLCs.
The suggested TSC-PWM is designed in a way that it generates a multilevel waveform at the output with a single carrier. Moreover,
VHDL programming based FPGA implementation of TSC-PWM is held to show the efficacy of the proposed method in terms of
resource utilization. There are several important areas where this study makes an original contribution to and those areas are listed
as follows:

1. TSC-PWM is proposed for CHB-MLCs so that output waveform quality is improved compared to sinusoidal reference based
SC-PWM methods.
2. A gate decoding strategy for TSC-PWM is suggested in a way that both half-wave and quarter-wave symmetries are ensured
at the output.
3. VHDL based FPGA implementation of TSC-PWM is investigated in detail with corresponding behavioral models.
4. Both LUT and counter based trapezoidal reference generation methods are proposed for TSC-PWM in FPGA and superior
behavior of both methods are demonstrated compared to other methods in the literature in terms of resource utilization.

The overall structure of the study takes the form of seven sections, including this introductory section. Second section gives a
brief overview on the properties of trapezoidal waveform along with selection process of the best possible parameters for trapezoidal
waveform in terms of output voltage quality. The details of the proposed TSC-PWM method is given in Section 3. In the fourth
section, VHDL based FPGA implementation of TSC-PWM is provided along with comparisons to other methods in the literature.
Simulation results are presented in Section 5 and Section 6 gives experimental realization of TSC-PWM on a laboratory prototype.
Finally, conclusions are drawn in Section 7 along with future directives.

2. Trapezoidal waveform

Circuit diagram of a single-phase n-module CHB-MLC is given in Fig. 1 along with multi carrier PWM generation strategy. It can
be seen that reference signal is compared to carriers of each module to produce gating signals. In this study, trapezoidal reference
signal and triangular carriers are employed. A trapezoidal signal has the properties of both square and triangular signals; and it
consists of four main parts as seen in Fig. 2: rise time (𝑡𝑅 ), high time (𝑡𝐻 ), fall time (𝑡𝐹 ) and low time (𝑡𝐿 ). It becomes maximum
having the value of the amplitude modulation index (𝑚𝑎 ) during 𝑡𝐻 and conversely, it has its minimum value during 𝑡𝐿 (−𝑚𝑎 ).

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Fig. 1. Circuit diagram of a single-phase n-module CHB-MLC with PWM generation.

Fig. 2. Trapezoidal waveform.

Moreover, it linearly increases and decreases during 𝑡𝑅 and 𝑡𝐹 respectively. As a result, fundamental period of a trapezoidal signal
(𝑇𝑡 ) can be defined as follows:

𝑇𝑡 = 𝑡𝑅 + 𝑡𝐻 + 𝑡𝐹 + 𝑡𝐿 (1)

In a symmetrical trapezoidal signal, following conditions are satisfied:

𝑡𝐻 = 𝑡𝐿 (2a)
𝑡𝑅 = 𝑡𝐹 (2b)

Hence, a symmetrical trapezoidal signal can be defined by two parameters in time-domain and the relationship between those
parameters can be defined as given below:
𝑇𝑡 − 2𝑡𝐻
𝑡𝑅 = (3)
2
Square signal is obtained when 𝑡𝐻 = 𝑡𝐿 = 𝑇𝑡 ∕2 and triangular signal is generated when 𝑡𝐻 = 𝑡𝐿 = 0.
Fig. 3 demonstrates the waveforms of trapezoidal reference based multi carrier PD-LS-PWM (T-PD-LS-PWM). It is the same
as traditional PD-LS-PWM except that trapezoidal signal is employed instead of sinusoidal signal as the reference. Selection of
trapezoidal signal parameters is of the utmost importance when it comes to improving the output voltage quality of CHB-MLC.
Hence, two critical performance parameters are considered while choosing the value of 𝑡𝑅 : total harmonic distortion (𝑇 𝐻𝐷) and
magnitude of fundamental frequency component (𝑉𝑜𝑢𝑡,𝑓 𝑢𝑛𝑑 ). In this analysis, 𝑇 𝐻𝐷 of output voltage is calculated up to 50th harmonic
and therefore it is called as 𝑇 𝐻𝐷50 . A single-phase CHB-MLC with the parameters given in Fig. 4 is run for different 𝑡𝑅 values by
using T-PD-LS-PWM and corresponding 𝑇 𝐻𝐷50 and 𝑉𝑜𝑢𝑡,𝑓 𝑢𝑛𝑑 values are stored. Results of this analysis are revealed in Fig. 4. Fig. 4a
shows 𝑇 𝐻𝐷50 results for different 𝑡𝑅 values. As seen, the lowest 𝑇 𝐻𝐷50 is obtained between 𝑡𝑅 = 4.5 ms and 𝑡𝑅 = 7.5 ms. With
that in mind, Fig. 4b presents 𝑉𝑜𝑢𝑡,𝑓 𝑢𝑛𝑑 results for different 𝑡𝑅 values. It can be seen that as 𝑡𝑅 increases, 𝑉𝑜𝑢𝑡,𝑓 𝑢𝑛𝑑 decreases in an

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Fig. 3. Trapezoidal reference based multi carrier PD-LS-PWM (T-PD-LS-PWM).

Fig. 4. 𝑇 𝐻𝐷50 (a) and fundamental amplitude (b) of output voltage for T-PD-LS-PWM on a CHB-MLC (𝑛 = 3, 𝑉𝑑𝑐 = 50, 𝑚𝑎 = 0.8, 𝑇𝑡 = 20 ms).

exponential manner. Under these circumstances, the most suitable 𝑡𝑅 value could be 5 ms (𝑇𝑡 ∕4) ensuring both low 𝑇 𝐻𝐷50 and
somewhat high 𝑉𝑜𝑢𝑡,𝑓 𝑢𝑛𝑑 at the output. Therefore, 𝑡𝑅 = 𝑇𝑡 ∕4 is used for the rest of the paper based on the findings of this analysis.

3. The proposed TSC-PWM method

This section presents the proposed TSC-PWM that achieves multilevel waveform at the output of CHB-MLC by imitating T-PD-
LS-PWM. The proposed TSC-PWM can be treated under three headings: reference rescaling, gating signal decoding and equal power
sharing.

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Fig. 5. Rescaling the raw trapezoidal reference for TSC-PWM for 3-module CHB-MLC (red: rescaled reference, blue: single carrier).

3.1. Reference rescaling

In SC-PWM methods, reference signal should be rescaled so that it fits within the boundaries of a single carrier. Fig. 5 shows
the reference rescaling approach for the proposed TSC-PWM to replicate the switching behavior of T-PD-LS-PWM. Given that
unity magnitude carriers are utilized in T-PD-LS-PWM, magnitude of the single carrier in the proposed TSC-PWM should be
unity as well. Consequently, magnitude of rescaled reference should be reduced to unity as given in Fig. 5. The level bands
(𝑖 = −𝑛, −𝑛 + 1, … , 0, 1, … , 𝑛 − 1, 𝑛) are also given in Fig. 5 where 𝑛 is the number of modules that CHB-MLC consists of. Level bands
are detected depending on the position of the raw trapezoidal reference and they are utilized to produce the rescaled reference as
given below:

𝑣𝑟,𝑟𝑠𝑐 = 𝑣𝑟,𝑟𝑎𝑤 − (𝑖 − 1), 𝑖 > 0 (4a)

𝑣𝑟,𝑟𝑠𝑐 = −𝑣𝑟,𝑟𝑎𝑤 + (𝑖 + 1), 𝑖 ≤ 0 (4b)

where 𝑣𝑟,𝑟𝑎𝑤 and 𝑣𝑟,𝑟𝑠𝑐 represent raw and rescaled trapezoidal references respectively.

3.2. Gating signal decoding

To generate gating signals for CHB-MLC on the proposed TSC-PWM, firstly a raw PWM should be created. Generation process
of the raw PWM is the same as producing PWM signals on T-PD-LS-PWM. The main idea is to compare the rescaled trapezoidal
reference signal to the single carrier signal. If the reference is greater than the carrier, raw PWM becomes logic ‘1’. If the reference
is smaller than the carrier, raw PWM becomes logic ‘0’ as seen in Fig. 6. After raw PWM is generated, it should be distributed
among modules of CHB-MLC in a way that a multilevel waveform is obtained at the output of CHB-MLC. For this reason, a gating
signal decoding approach is proposed as indicated in Fig. 7. Similar to reference rescaling process, level bands are utilized to set
up different combinations of gating signals by using the raw PWM. It should be noted that the notation given in Fig. 7 can be

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Fig. 6. Generating the raw PWM for 3-module CHB-MLC.

Fig. 7. Gating signal decoding flowchart for 3-module CHB-MLC.

comprehended as follows: 𝑔𝐿,𝑗,𝑘 indicates 𝑗th semiconductor on a module of CHB-MLC for the 𝑘th level band. For example, 𝑔𝐿,1,2
represents the upper semiconductor on the left-leg of a module in CHB-MLC for the second level band (𝑖 = 2). Moreover, 𝑃 𝑊 𝑀
represents the generated raw PWM.

3.3. Equal power sharing

Sharing the power equally among modules of CHB-MLC is critical since different power levels among modules could result in
different lifetimes for semiconductors. Unequal power sharing is an inherent property of traditional PD-LS-PWM methods due to
different conduction periods of semiconductors. Since TSC-PWM is a replication of T-PD-LS-PWM, it would be inevitable to obtain
different power levels among modules of CHB-MLC. For this reason, a power sharing strategy is proposed for TSC-PWM in this study
as seen in Fig. 8. In this method, generated gating signals are rotated among semiconductors of modules with a rotation period (𝑇𝑟𝑜𝑡 ).

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Fig. 8. Equal power sharing strategy for 3-module CHB-MLC.

Fig. 9. Schematic diagram for the architectural design of the proposed TSC-PWM for 3-module CHB-MLC.

Consequently, average power of each module become equal after three rotation periods. It should be noted that a proper selection
of rotation period would be between carrier period and reference period.

4. FPGA implementation of the proposed TSC-PWM method

This section features FPGA implementation of the proposed TSC-PWM for 3-module CHB-MLC. In this study, architectural
behaviour of the entire system is designed by using VHDL. Firstly, the VHDL modules that form the architectural design within
Fig. 9 will be investigated in detail with their corresponding pseudocodes. Then, a comparison between the proposed TSC-PWM,
traditional PD-LS-PWM and other SC-PWM methods will be held in terms of resource utilization within the FPGA.

4.1. Single carrier module

As explained in the previous section, the proposed TSC-PWM includes a single carrier instead of six carriers for a 3-module
CHB-MLC. To generate the single carrier, up-down counters are utilized. As seen in Fig. 6, the value of the carrier varies between
zero and unity. In digital implementation of the single carrier, unity value should be selected as an integer that is greater than one
so that up-down counter works properly. For this reason, the limit of the carrier is selected as 40 in this work. Carrier value is
initialized to zero and increased by 1 at each clock cycle. When the limit is reached, the direction of the carrier is changed and
value is decreased by 1 at each clock cycle until zero is achieved where the direction is again changed. Carrier generation process
is summarized in Algorithm 1.

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Algorithm 1 Pseudocode of single carrier module

Input: 𝑐𝑙𝑜𝑐𝑘𝑐𝑟 , reset ⊳ carrier sampling clock
Output: 𝑐𝑟𝑜𝑢𝑡 ⊳ single carrier
Initialization: 𝑐𝑜𝑢𝑛𝑡𝑐𝑟 = 0, 𝑙𝑖𝑚𝑖𝑡𝑈 = 120, 𝑙𝑖𝑚𝑖𝑡𝐿 = 0,
𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛𝑐𝑟 = 0 ⊳ 0: upward, 1: downward
1: Carrier: process(𝑐𝑙𝑜𝑐𝑘𝑐𝑟 ,reset)
2: if rising_edge(𝑐𝑙𝑜𝑐𝑘𝑐𝑟 ) then
3: if 𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛𝑐𝑟 = 0 then
4: if 𝑐𝑜𝑢𝑛𝑡𝑐𝑟 = 𝑙𝑖𝑚𝑖𝑡𝑈 ∕3 then
5: 𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛𝑐𝑟 ← 1
6: else
7: 𝑐𝑜𝑢𝑛𝑡𝑐𝑟 ← 𝑐𝑜𝑢𝑛𝑡𝑐𝑟 + 1
8: end if
9: else
10: if 𝑐𝑜𝑢𝑛𝑡𝑐𝑟 = 𝑙𝑖𝑚𝑖𝑡𝐿 then
11: 𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛𝑐𝑟 ← 0
12: else
13: 𝑐𝑜𝑢𝑛𝑡𝑐𝑟 ← 𝑐𝑜𝑢𝑛𝑡𝑐𝑟 − 1
14: end if
15: end if
16: end if
17: end process
18: 𝑐𝑟𝑜𝑢𝑡 ← 𝑐𝑜𝑢𝑛𝑡𝑐𝑟

4.2. Trapezoidal reference module

Raw trapezoidal reference signal is generated in this module. As stated in the Introduction section, LUT based approaches are
popular among researchers to produce trapezoidal waveforms digitally. In this study, two different trapezoidal signal generation
ways are suggested: LUT based and up-down counter based.
In LUT based approach, trapezoidal signal is generated externally and the samples are stored on a LUT with the size of number of
samples. Pseudocode of trapezoidal signal generation by LUT approach is given in Algorithm 2. It should be noted that trapezoidal
signal varies between +120 and −120 without 𝑚𝑎 integration. A different form of 𝑚𝑎 is first multiplied by each sample of the
trapezoidal signal. Then, it is shifted by 10 bits to imitate the division by 1024. For example, let 90 to be used as 𝑚𝑎 for 𝑚𝑎 = 0.9.
Normally, it should be multiplied by 10 and divided by 1000 to achieve the value of 0.9. However, dividing by 1000 is tricky in
FPGA. For this reason, 1024 is used instead of 1000 as a denominator and consequently, shifting operator is used to realize division
operation. This yields to employing 92 instead of 90 for the initial 𝑚𝑎 to achieve the right 𝑚𝑎 value which is 0.9.

Algorithm 2 Pseudocode of trapezoidal generation by LUT

Input: 𝑐𝑙𝑜𝑐𝑘𝑡𝑟𝑎 , reset ⊳ trapezoid sampling clock
Output: 𝑡𝑟𝑎𝑜𝑢𝑡 ⊳ trapezoidal signal
Initialization: 𝐾𝑚𝑢𝑙𝑡𝑖𝑝𝑙𝑖𝑒𝑟 = 10, 𝑚𝑎 = 92, round = 512
r_tra_int, r_tra_sgn, 𝐿𝑈 𝑇𝑡𝑟𝑎 ⊳ LUT for trapezoidal signal
1: Raw Trapezoidal Signal: process(𝑐𝑙𝑜𝑐𝑘𝑡𝑟𝑎 ,reset)
2: if rising_edge(𝑐𝑙𝑜𝑐𝑘𝑡𝑟𝑎 ) then
3: r_tra_int ← 𝐾𝑚𝑢𝑙𝑡𝑖𝑝𝑙𝑖𝑒𝑟 ⋅ 𝑚𝑎 ⋅ 𝐿𝑈 𝑇𝑡𝑟𝑎 (𝑖) + round
4: r_tra_sgn ← to_signed(r_tra_int,18)
5: 𝑡𝑟𝑎𝑜𝑢𝑡 ← r_tra_sgn(17 downto 10)
6: 𝑖←𝑖+1
7: if i = 239 then ⊳ LUT with the size of 240
8: 𝑖←0
9: end if
10: end if
11: end process
The other way to generate trapezoidal signal using FPGA is to utilize up-down counters. It is similar to triangular carrier
generation process, however, it includes regions where the value of the trapezoidal signal becomes constant in contrast to triangular
carriers. The pseudocode of trapezoidal signal generation process by up-down counter method is given in Algorithm 3. Modulation
index is introduced at another module having the same process with the LUT based approach.

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Algorithm 3 Pseudocode of trapezoidal generation by counter

Input: 𝑐𝑙𝑜𝑐𝑘𝑡𝑟𝑎 , reset ⊳ trapezoid sampling clock
Output: 𝑡𝑟𝑎𝑜𝑢𝑡 ⊳ trapezoidal signal
Initialization: 𝑙𝑖𝑚𝑖𝑡 = 120, 𝑛𝑢𝑝 = 30, 𝛥𝑛 = 𝑙𝑖𝑚𝑖𝑡/𝑛𝑢𝑝
𝑛𝑓 𝑙𝑎𝑡 = 2 ⋅ 𝑙𝑖𝑚𝑖𝑡, 𝑐𝑜𝑢𝑛𝑡𝑡𝑟𝑎 = 0, 𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛𝑡𝑟𝑎 = "000"
1: Raw Trapezoidal Signal: process(𝑐𝑙𝑜𝑐𝑘𝑡𝑟𝑎 ,reset)
2: if rising_edge(𝑐𝑙𝑜𝑐𝑘𝑡𝑟𝑎 ) then
3: if 𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛𝑡𝑟𝑎 = "000" then ⊳ first increasing region
4: if 𝑐𝑜𝑢𝑛𝑡𝑡𝑟𝑎 = 𝑙𝑖𝑚𝑖𝑡 then
5: 𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛𝑡𝑟𝑎 ← "001"
6: else
7: 𝑐𝑜𝑢𝑛𝑡𝑡𝑟𝑎 ← 𝑐𝑜𝑢𝑛𝑡𝑡𝑟𝑎 + 𝛥𝑛
8: end if
9: end if
10: if 𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛𝑡𝑟𝑎 = "001" then ⊳ upper flat region
11: 𝑖 ← 𝑖 + 𝛥𝑛
12: 𝑐𝑜𝑢𝑛𝑡𝑡𝑟𝑎 ← 𝑐𝑜𝑢𝑛𝑡𝑡𝑟𝑎 + 0
13: if 𝑖 = 𝑛𝑓 𝑙𝑎𝑡 then
14: 𝑖←0
15: 𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛𝑡𝑟𝑎 ← "010"
16: end if
17: end if
18: if 𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛𝑡𝑟𝑎 = "010" then ⊳ decreasing region
19: if 𝑐𝑜𝑢𝑛𝑡𝑡𝑟𝑎 = -𝑙𝑖𝑚𝑖𝑡 then
20: 𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛𝑡𝑟𝑎 ← "011"
21: else
22: 𝑐𝑜𝑢𝑛𝑡𝑡𝑟𝑎 ← 𝑐𝑜𝑢𝑛𝑡𝑡𝑟𝑎 - 𝛥𝑛
23: end if
24: end if
25: if 𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛𝑡𝑟𝑎 = "011" then ⊳ lower flat region
26: 𝑖 ← 𝑖 + 𝛥𝑛
27: 𝑐𝑜𝑢𝑛𝑡𝑡𝑟𝑎 ← 𝑐𝑜𝑢𝑛𝑡𝑡𝑟𝑎 + 0
28: if 𝑖 = 𝑛𝑓 𝑙𝑎𝑡 then
29: 𝑖←0
30: 𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛𝑡𝑟𝑎 ← "100"
31: end if
32: end if
33: if 𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛𝑡𝑟𝑎 = "100" then ⊳ second increasing region
34: if 𝑐𝑜𝑢𝑛𝑡𝑡𝑟𝑎 = 0 then
35: 𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛𝑡𝑟𝑎 ← "000"
36: else
37: 𝑐𝑜𝑢𝑛𝑡𝑡𝑟𝑎 ← 𝑐𝑜𝑢𝑛𝑡𝑡𝑟𝑎 + 𝛥𝑛
38: end if
39: end if
40: end if
41: end process
42: 𝑡𝑟𝑎𝑜𝑢𝑡 ← 𝑐𝑜𝑢𝑛𝑡𝑡𝑟𝑎

4.3. Reference rescaling module

In this module, raw trapezoidal reference signal that is generated in trapezoidal reference module is rescaled to make it suitable
for the proposed TSC-PWM as demonstrated in Fig. 5. The detailed pseudocode of reference rescaling process is provided in
Algorithm 4.

4.4. Clock divider module

In this module, master clock of the FPGA with the frequency of 125 MHz (𝑓𝑚𝑐𝑙𝑘 ) is divided into clock with different frequencies
depending on the needs of the modules. For this purpose, clocks for three different modules are generated: single carrier module,
trapezoidal reference module and equal power sharing module. In this study, carrier frequency (𝑓𝑐𝑟 ) is selected to be 1 kHz.

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F. Eroğlu and M. Kurtoğlu Computers and Electrical Engineering 107 (2023) 108650

Algorithm 4 Pseudocode of reference rescaling

Input: mclk, reset, 𝑡𝑟𝑎𝑟𝑎𝑤 ⊳ master clock, raw trapezoid
Output: 𝑡𝑟𝑎𝑟𝑠𝑐 ⊳ rescaled trapezoidal signal
Initialization: 𝑙𝑖𝑚𝑖𝑡 = 120
1: Reference Rescaling: process(mclk, reset)
2: if rising_edge(𝑐𝑙𝑜𝑐𝑘𝑡𝑟𝑎 ) then
3: if 𝑡𝑟𝑎𝑟𝑎𝑤 ≥ 0 and 𝑡𝑟𝑎𝑟𝑎𝑤 < 𝑙𝑖𝑚𝑖𝑡∕3 then
4: 𝑡𝑟𝑎𝑟𝑠𝑐 ← 𝑡𝑟𝑎𝑟𝑎𝑤
5: end if
6: if 𝑡𝑟𝑎𝑟𝑎𝑤 ≥ 𝑙𝑖𝑚𝑖𝑡∕3 and 𝑡𝑟𝑎𝑟𝑎𝑤 < 2 ⋅ 𝑙𝑖𝑚𝑖𝑡∕3 then
7: 𝑡𝑟𝑎𝑟𝑠𝑐 ← 𝑡𝑟𝑎𝑟𝑎𝑤 - 𝑙𝑖𝑚𝑖𝑡∕3
8: end if
9: if 𝑡𝑟𝑎𝑟𝑎𝑤 ≥ 2 ⋅ 𝑙𝑖𝑚𝑖𝑡∕3 and 𝑡𝑟𝑎𝑟𝑎𝑤 ≤ 𝑙𝑖𝑚𝑖𝑡 then
10: 𝑡𝑟𝑎𝑟𝑠𝑐 ← 𝑡𝑟𝑎𝑟𝑎𝑤 - 2 ⋅ 𝑙𝑖𝑚𝑖𝑡∕3
11: end if
12: if 𝑡𝑟𝑎𝑟𝑎𝑤 ≥ -𝑙𝑖𝑚𝑖𝑡∕3 and 𝑡𝑟𝑎𝑟𝑎𝑤 < 0 then
13: 𝑡𝑟𝑎𝑟𝑠𝑐 ← -𝑡𝑟𝑎𝑟𝑎𝑤
14: end if
15: if 𝑡𝑟𝑎𝑟𝑎𝑤 ≥ -2 ⋅ 𝑙𝑖𝑚𝑖𝑡∕3 and 𝑡𝑟𝑎𝑟𝑎𝑤 < -𝑙𝑖𝑚𝑖𝑡∕3 then
16: 𝑡𝑟𝑎𝑟𝑠𝑐 ← -𝑡𝑟𝑎𝑟𝑎𝑤 - 𝑙𝑖𝑚𝑖𝑡∕3
17: end if
18: if 𝑡𝑟𝑎𝑟𝑎𝑤 ≥ -𝑙𝑖𝑚𝑖𝑡 and 𝑡𝑟𝑎𝑟𝑎𝑤 < -2 ⋅ 𝑙𝑖𝑚𝑖𝑡∕3 then
19: 𝑡𝑟𝑎𝑟𝑠𝑐 ← -𝑡𝑟𝑎𝑟𝑎𝑤 - 2 ⋅ 𝑙𝑖𝑚𝑖𝑡∕3
20: end if
21: end if
22: end process

Consequently, carrier period (𝑇𝑐𝑟 ) would be 1 ms. Moreover, 80 samples are utilized to generate a carrier period. Hence, sampling
period of the carrier (𝑇𝑠,𝑐𝑟 ) is calculated as follows:
𝑇𝑐𝑟
𝑇𝑠,𝑐𝑟 = = 12.5 μs (5)
80
Here, the purpose is to create a clock with the period of 12.5 μs according to (5). The main principle of the clock divider module
is that a counter is incremented up to a certain value at each sampling time of the master clock. It is kept at logic ‘1’ and ‘0’ for that
certain number. Based on the fact that 𝑓𝑚𝑐𝑙𝑘 = 125 MHz, period of the master clock (𝑇𝑚𝑐𝑙𝑘 ) becomes 8 ns. Therefore, the number of
clock ticks required (𝑐𝑛𝑡𝑐𝑙𝑘,𝑐𝑟 ) to generate 𝑇𝑠,𝑐𝑟 ∕2 can be calculated as follows:
𝑇𝑠,𝑐𝑟
𝑐𝑛𝑡𝑐𝑙𝑘,𝑐𝑟 = = 781 (6)
2𝑇𝑚𝑐𝑙𝑘
Note that the result of (6) is rounded to the nearest integer. A similar process is held for trapezoidal reference module as well.
It is known that the number of samples that is used in the first increasing region of trapezoidal signal is 𝑛𝑢𝑝 = 30 for counter based
method (see Algorithm 3). For LUT based method, total number of samples is 240 (see Algorithm 2). Hence, first increasing region
consists of 30 samples as well. Moreover, first increasing region takes 2.5 ms for 𝑇𝑡 = 20 ms. Consequently, the number of clock
ticks required (𝑐𝑛𝑡𝑐𝑙𝑘,𝑡𝑟𝑎 ) to generate a period of trapezoidal samples are as follows:
𝑇𝑡
𝑐𝑛𝑡𝑐𝑙𝑘,𝑡𝑟𝑎 = = 5208 (7)
16𝑇𝑚𝑐𝑙𝑘 𝑛𝑢𝑝
Finally, a rotation period of 20 ms (𝑇𝑟𝑜𝑡 = 20 ms) is employed for equal power sharing module and master clock is utilized to
generate the samples. Therefore, the number of clock cycles (𝑐𝑛𝑡𝑐𝑙𝑘,𝑟𝑜𝑡 ) to generate a period of rotation is given below:
𝑇𝑡
𝑐𝑛𝑡𝑐𝑙𝑘,𝑟𝑜𝑡 = = 1250000 (8)
2𝑇𝑚𝑐𝑙𝑘
The details of pseudocode that is used in the clock divider module is given in Algorithm 5.

4.5. Gating signal decoding module

In this module, gating signals are generated for different levels based on Fig. 7. The pseudocode of gating signal decoding module
is given in Algorithm 6.

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F. Eroğlu and M. Kurtoğlu Computers and Electrical Engineering 107 (2023) 108650

Algorithm 5 Pseudocode of clock divider

Input: mclk, reset, ⊳ master clock
Output: 𝑐𝑙𝑜𝑐𝑘𝑐𝑟 , 𝑐𝑙𝑜𝑐𝑘𝑡𝑟𝑎 , 𝑐𝑙𝑜𝑐𝑘𝑟𝑜𝑡 ⊳ new clocks
Initialization: 𝑐𝑛𝑡𝑐𝑙𝑘,𝑐𝑟 = 781, 𝑐𝑛𝑡𝑐𝑙𝑘,𝑡𝑟𝑎 = 5208, 𝑐𝑛𝑡𝑐𝑙𝑘,𝑟𝑜𝑡 = 1250000, 𝑐𝑜𝑢𝑛𝑡𝑒𝑟𝑐𝑟 = 1, 𝑐𝑜𝑢𝑛𝑡𝑒𝑟𝑡𝑟𝑎 = 1, 𝑐𝑜𝑢𝑛𝑡𝑒𝑟𝑟𝑜𝑡 = 1,
𝑙𝑜𝑔𝑖𝑐𝑐𝑟 = ’0’, 𝑙𝑜𝑔𝑖𝑐𝑡𝑟𝑎 = ’0’, 𝑙𝑜𝑔𝑖𝑐𝑟𝑜𝑡 = ’0’
1: Clock Divider: process(mclk, 𝑐𝑙𝑜𝑐𝑘𝑐𝑟 , 𝑐𝑙𝑜𝑐𝑘𝑡𝑟𝑎 , 𝑐𝑙𝑜𝑐𝑘𝑟𝑜𝑡 , reset)
2: if rising_edge(mclk) then
3: 𝑐𝑜𝑢𝑛𝑡𝑒𝑟𝑐𝑟 ← 𝑐𝑜𝑢𝑛𝑡𝑒𝑟𝑐𝑟 + 1
4: 𝑐𝑜𝑢𝑛𝑡𝑒𝑟𝑡𝑟𝑎 ← 𝑐𝑜𝑢𝑛𝑡𝑒𝑟𝑡𝑟𝑎 + 1
5: 𝑐𝑜𝑢𝑛𝑡𝑒𝑟𝑟𝑜𝑡 ← 𝑐𝑜𝑢𝑛𝑡𝑒𝑟𝑟𝑜𝑡 + 1
6: if 𝑐𝑜𝑢𝑛𝑡𝑒𝑟𝑐𝑟 = 𝑐𝑛𝑡𝑐𝑙𝑘,𝑐𝑟 then
7: 𝑐𝑜𝑢𝑛𝑡𝑒𝑟𝑐𝑟 ← 1
8: 𝑙𝑜𝑔𝑖𝑐𝑐𝑟 ← not 𝑙𝑜𝑔𝑖𝑐𝑐𝑟
9: end if
10: if 𝑐𝑜𝑢𝑛𝑡𝑒𝑟𝑡𝑟𝑎 = 𝑐𝑛𝑡𝑐𝑙𝑘,𝑡𝑟𝑎 then
11: 𝑐𝑜𝑢𝑛𝑡𝑒𝑟𝑡𝑟𝑎 ← 1
12: 𝑙𝑜𝑔𝑖𝑐𝑡𝑟𝑎 ← not 𝑙𝑜𝑔𝑖𝑐𝑡𝑟𝑎
13: end if
14: if 𝑐𝑜𝑢𝑛𝑡𝑒𝑟𝑟𝑜𝑡 = 𝑐𝑛𝑡𝑐𝑙𝑘,𝑟𝑜𝑡 then
15: 𝑐𝑜𝑢𝑛𝑡𝑒𝑟𝑟𝑜𝑡 ← 1
16: 𝑙𝑜𝑔𝑖𝑐𝑟𝑜𝑡 ← not 𝑙𝑜𝑔𝑖𝑐𝑟𝑜𝑡
17: end if
18: end if
19: end process
20: 𝑐𝑙𝑜𝑐𝑘𝑐𝑟 ← 𝑙𝑜𝑔𝑖𝑐𝑐𝑟
21: 𝑐𝑙𝑜𝑐𝑘𝑡𝑟𝑎 ← 𝑙𝑜𝑔𝑖𝑐𝑡𝑟𝑎
22: 𝑐𝑙𝑜𝑐𝑘𝑟𝑜𝑡 ← 𝑙𝑜𝑔𝑖𝑐𝑟𝑜𝑡

4.6. Equal power sharing module

In this module, equal power sharing procedure that is given in Fig. 8 is held. The pseudocode of equal power sharing module is
given in Algorithm 7.

4.7. Performance comparison of TSC-PWM to existing methods

The performance of the proposed TSC-PWM method is verified on an actual design by implementing it on an FPGA board. In
this analysis, the traditional sinusoidal reference based PD-LS-PWM (S-PD-LS-PWM), two types of T-PD-LS-PWM (LUT based and
counter based), sinusoidal reference based SC-PWM (S-SC-PWM) [17] and two types of the proposed TSC-PWM (LUT based and
counter based) are implemented on Xilinx Zynq-7000 Zybo Z7-10 FPGA board. This FPGA board contains XC7Z010-1CLG400C
FPGA device on it. Moreover, resource utilization and power consumption analysis of each method are held by using Xilinx Vivado
Design Suite v2020.2. Number of LUTs, flip-flops (FF), digital signal processors (DSP), input–outputs (IO) and global clock buffers
(BUFG) are considered as the parameters to compare the performance of all methods in terms of resource utilization. Total on-chip
power (dynamic and static) and junction temperature are selected as the parameters for power consumption comparisons among
different methods.
The results of this analysis are revealed in Table 1. It is apparent from the table that DSP, IO and BUFG utilization of all methods
are the same. Looking at LUT and FF parameters, it is evident that the multi carrier methods which are S-PD-LS-PWM and T-PD-
LS-PWM use more resources than the SC-PWM methods. Among the two T-PD-LS-PWM methods, LUT based method stands for less
resource utilization compared to the other. Similar deductions can be obtained when the two TSC-PWM methods are compared
as well. However, counter based TSC-PWM gives the user the flexibility to change the configuration parameters of the trapezoidal
signal more easily compared to LUT based TSC-PWM which requires external generation of trapezoidal signal. The most critical
observation to emerge from Table 1 is that the utilization of the proposed LUT based TSC-PWM method significantly reduces the
number of components compared to S-SC-PWM method [17]. Hence, it can be said that the proposed TSC-PWM is superior in terms
of resource utilization in FPGA implementation.
Dynamic, static and total on-chip power consumption of the FPGA device for each method are presented in Table 1 as well
as junction temperatures. Implementation of the traditional S-PD-LS-PWM provides the least power consumption and junction
temperature compared to other methods. Among SC-PWM methods, both versions of the proposed TSC-PWM methods give close
results to S-SC-PWM method [17] in terms of power consumption and junction temperature. Yet, it can be said that LUT based
TSC-PWM is advantageous in this aspect compared to counter based TSC-PWM.

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F. Eroğlu and M. Kurtoğlu Computers and Electrical Engineering 107 (2023) 108650

Algorithm 6 Pseudocode of gating signal decoding

Input: mclk, reset, 𝑡𝑟𝑎𝑟𝑎𝑤 , PWM ⊳ raw trapezoid, raw PWM
Output: 𝑔𝐿,1,1 , 𝑔𝐿,3,1 , 𝑔𝐿,1,2 , 𝑔𝐿,3,2 , 𝑔𝐿,1,3 , 𝑔𝐿,3,3 ⊳ gating signals
Initialization: 𝑙𝑖𝑚𝑖𝑡 = 120
1: Gate Decoding: process(mclk, reset)
2: if rising_edge(mclk) then
3: if 𝑡𝑟𝑎𝑟𝑎𝑤 ≥ 0 and 𝑡𝑟𝑎𝑟𝑎𝑤 < 𝑙𝑖𝑚𝑖𝑡∕3 then
4: 𝑔𝐿,1,1 ← PWM
5: 𝑔𝐿,3,1 ← ’0’
6: 𝑔𝐿,1,2 ← ’0’
7: 𝑔𝐿,3,2 ← ’0’
8: 𝑔𝐿,1,3 ← ’0’
9: 𝑔𝐿,3,3 ← ’0’
10: end if
11: if 𝑡𝑟𝑎𝑟𝑎𝑤 ≥ 𝑙𝑖𝑚𝑖𝑡∕3 and 𝑡𝑟𝑎𝑟𝑎𝑤 < 2 ⋅ 𝑙𝑖𝑚𝑖𝑡∕3 then
12: 𝑔𝐿,1,1 ← ’1’
13: 𝑔𝐿,3,1 ← ’0’
14: 𝑔𝐿,1,2 ← PWM
15: 𝑔𝐿,3,2 ← ’0’
16: 𝑔𝐿,1,3 ← ’0’
17: 𝑔𝐿,3,3 ← ’0’
18: end if
19: if 𝑡𝑟𝑎𝑟𝑎𝑤 ≥ 2 ⋅ 𝑙𝑖𝑚𝑖𝑡∕3 and 𝑡𝑟𝑎𝑟𝑎𝑤 ≤ 𝑙𝑖𝑚𝑖𝑡 then
20: 𝑔𝐿,1,1 ← ’1’
21: 𝑔𝐿,3,1 ← ’0’
22: 𝑔𝐿,1,2 ← ’1’
23: 𝑔𝐿,3,2 ← ’0’
24: 𝑔𝐿,1,3 ← PWM
25: 𝑔𝐿,3,3 ← ’0’
26: end if
27: if 𝑡𝑟𝑎𝑟𝑎𝑤 ≥ -𝑙𝑖𝑚𝑖𝑡∕3 and 𝑡𝑟𝑎𝑟𝑎𝑤 < 0 then
28: 𝑔𝐿,1,1 ← ’0’
29: 𝑔𝐿,3,1 ← PWM
30: 𝑔𝐿,1,2 ← ’0’
31: 𝑔𝐿,3,2 ← ’0’
32: 𝑔𝐿,1,3 ← ’0’
33: 𝑔𝐿,3,3 ← ’0’
34: end if
35: if 𝑡𝑟𝑎𝑟𝑎𝑤 ≥ -2 ⋅ 𝑙𝑖𝑚𝑖𝑡∕3 and 𝑡𝑟𝑎𝑟𝑎𝑤 < -𝑙𝑖𝑚𝑖𝑡∕3 then
36: 𝑔𝐿,1,1 ← ’0’
37: 𝑔𝐿,3,1 ← ’1’
38: 𝑔𝐿,1,2 ← ’0’
39: 𝑔𝐿,3,2 ← PWM
40: 𝑔𝐿,1,3 ← ’0’
41: 𝑔𝐿,3,3 ← ’0’
42: end if
43: if 𝑡𝑟𝑎𝑟𝑎𝑤 ≥ -𝑙𝑖𝑚𝑖𝑡 and 𝑡𝑟𝑎𝑟𝑎𝑤 < -2 ⋅ 𝑙𝑖𝑚𝑖𝑡∕3 then
44: 𝑔𝐿,1,1 ← ’0’
45: 𝑔𝐿,3,1 ← ’1’
46: 𝑔𝐿,1,2 ← ’0’
47: 𝑔𝐿,3,2 ← ’1’
48: 𝑔𝐿,1,3 ← ’0’
49: 𝑔𝐿,3,3 ← PWM
50: end if
51: end if
52: end process

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F. Eroğlu and M. Kurtoğlu Computers and Electrical Engineering 107 (2023) 108650

Algorithm 7 Pseudocode of equal power sharing

Input: mclk, 𝑐𝑙𝑜𝑐𝑘𝑟𝑜𝑡 , reset, 𝑔𝐿,1,1 , 𝑔𝐿,3,1 , 𝑔𝐿,1,2 , 𝑔𝐿,3,2 , 𝑔𝐿,1,3 , 𝑔𝐿,3,3 ⊳ decoded gating signals
Output: 𝑔1,1 , 𝑔3,1 , 𝑔1,2 , 𝑔3,2 , 𝑔1,3 , 𝑔3,3 ⊳ actual gating signals
Initialization: 𝑛 = 3, 𝑟𝑜𝑡𝑐𝑜𝑢𝑛𝑡 = 1
1: Power Sharing: process(mclk, 𝑐𝑙𝑜𝑐𝑘𝑟𝑜𝑡 , reset)
2: if rising_edge(mclk) then
3: if 𝑟𝑜𝑡𝑐𝑜𝑢𝑛𝑡 = 1 then ⊳ first rotation interval
4: 𝑔1,1 ← 𝑔𝐿,1,1
5: 𝑔3,1 ← 𝑔𝐿,3,1
6: 𝑔1,2 ← 𝑔𝐿,1,2
7: 𝑔3,2 ← 𝑔𝐿,3,2
8: 𝑔1,3 ← 𝑔𝐿,1,3
9: 𝑔3,3 ← 𝑔𝐿,3,3
10: end if
11: if 𝑟𝑜𝑡𝑐𝑜𝑢𝑛𝑡 = 2 then ⊳ second rotation interval
12: 𝑔1,1 ← 𝑔𝐿,1,3
13: 𝑔3,1 ← 𝑔𝐿,3,3
14: 𝑔1,2 ← 𝑔𝐿,1,1
15: 𝑔3,2 ← 𝑔𝐿,3,1
16: 𝑔1,3 ← 𝑔𝐿,1,2
17: 𝑔3,3 ← 𝑔𝐿,3,2
18: end if
19: if 𝑟𝑜𝑡𝑐𝑜𝑢𝑛𝑡 = 3 then ⊳ third rotation interval
20: 𝑔1,1 ← 𝑔𝐿,1,2
21: 𝑔3,1 ← 𝑔𝐿,3,2
22: 𝑔1,2 ← 𝑔𝐿,1,3
23: 𝑔3,2 ← 𝑔𝐿,3,3
24: 𝑔1,3 ← 𝑔𝐿,1,1
25: 𝑔3,3 ← 𝑔𝐿,3,21
26: end if
27: end if
28: if falling_edge(𝑐𝑙𝑜𝑐𝑘𝑟𝑜𝑡 ) then
29: 𝑟𝑜𝑡𝑐𝑜𝑢𝑛𝑡 ← 𝑟𝑜𝑡𝑐𝑜𝑢𝑛𝑡 + 1
30: if 𝑟𝑜𝑡𝑐𝑜𝑢𝑛𝑡 = 𝑛 then
31: 𝑟𝑜𝑡𝑐𝑜𝑢𝑛𝑡 ← 1
32: end if
33: end if
34: end process

Table 1
Performance comparison of the proposed TSC-PWM to existing methods in terms of FPGA resource usage.
S-PD-LS-PWM T-PD-LS-PWM T-PD-LS-PWM S-SC-PWM TSC-PWM TSC-PWM
(LUT Based) (Counter Based) [17] (LUT Based) (Counter Based)
LUT 437 (2.48%) 391 (2.22%) 474 (2.69%) 334 (1.90%) 288 (1.64%) 370 (2.10%)
FF 337 (0.96%) 335 (0.95%) 361 (1.03%) 256 (0.73%) 254 (0.72%) 280 (0.80%)
DSP 1 (1.25%) 1 (1.25%) 1 (1.25%) 1 (1.25%) 1 (1.25%) 1 (1.25%)
IO 14 (14%) 14 (14%) 14 (14%) 14 (14%) 14 (14%) 14 (14%)
BUFG 3 (9.38%) 3 (9.38%) 3 (9.38%) 3 (9.38%) 3 (9.38%) 3 (9.38%)
Total On-Chip
0.096 2.801 2.898 1.327 1.37 1.626
Power (W)
Junction
26.1 57.3 58.4 40.3 40.8 43.7
Temp. (°Celsius)
Dynamic
0.006 (6%) 2.663 (95%) 2.757 (95%) 1.221 (92%) 1.263 (92%) 1.514 (93%)
Power (W)
Static
0.090 (94%) 0.138 (5%) 0.141 (5%) 0.106 (8%) 0.107 (8%) 0.111 (7%)
Power (W)

5. Simulation results

A single-phase 3-module CHB-MLC is designed in simulation environment to demonstrate the superior performance of the
proposed TSC-PWM compared to the methods in the literature. Design parameters of the simulated system is given in Table 2.

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Table 2
Simulation design parameters.
Parameter Value Parameter Value
Number of modules (𝑁) 3 Modulation index (𝑚𝑎 ) 0.8
DC voltage (𝑉𝑑𝑐 ) 50 V Fundamental frequency (𝑓𝑓 𝑢𝑛𝑑 ) 50 Hz
Load 10 Ω Carrier frequency (𝑓𝑐𝑟 ) 1 kHz
Rotation frequency (𝑓𝑟𝑜𝑡 ) 50 Hz

Fig. 10. 𝑇 𝐻𝐷50 (a) and fundamental amplitude (𝑉𝑜𝑢𝑡,𝑓 𝑢𝑛𝑑 ) (b) of output voltage for different methods on a 3-module CHB-MLC.

Fig. 11. Output voltage of 3-module CHB-MLC obtained by TSC-PWM.

Those parameters are mutual for all the methods which are S-PD-LS-PWM, T-PD-LS-PWM, S-SC-PWM [17] and the proposed TSC-
PWM. Performance of those methods are compared for different modulation indices as 𝑇 𝐻𝐷50 and 𝑉𝑜𝑢𝑡,𝑓 𝑢𝑛𝑑 are the parameters
to consider. Moreover, individual harmonics are examined for all methods to investigate the symmetrical properties of the output
voltage of CHB-MLC. The results of the comparative analysis regarding 𝑇 𝐻𝐷50 and 𝑉𝑜𝑢𝑡,𝑓 𝑢𝑛𝑑 are presented in Fig. 10. This figure is

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F. Eroğlu and M. Kurtoğlu Computers and Electrical Engineering 107 (2023) 108650

Fig. 12. Harmonic spectrum of output voltage of 3-module CHB-MLC obtained by different methods.

Fig. 13. Gating signals and equal power sharing strategy of 3-module CHB-MLC.

quite revealing in several ways. First, trapezoidal reference based methods provide better harmonic performance along with higher
fundamental magnitude compared to sinusoidal reference based methods throughout the whole modulation index range. Secondly,
results of S-PD-LS-PWM and S-SC-PWM are very similar to each other for both performance indications. Finally, it is apparent from
Fig. 10a that the proposed TSC-PWM gives better results in terms of harmonic performance compared to other methods especially
for modulation indices that are higher than 0.4.
Fig. 11 shows the output voltage waveform of single-phase 3-module CHB-MLC obtained by the proposed TSC-PWM. It can be
seen that a seven-level waveform is obtained and it is symmetrical around 𝑦-axis. Regarding symmetries, harmonic spectrums of

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F. Eroğlu and M. Kurtoğlu Computers and Electrical Engineering 107 (2023) 108650

Table 3
Experimental design parameters.
Parameter Value Parameter Value
Number of modules (𝑁) 3 Modulation index (𝑚𝑎 ) [0.3 1.0]
Battery type Li-Ion Fundamental frequency (𝑓𝑓 𝑢𝑛𝑑 ) 50 Hz
Battery nominal voltage (𝑉𝑑𝑐 ) 3.7 V Carrier frequency (𝑓𝑐𝑟 ) 1 kHz
Load 10 Ω + 15 mH Rotation frequency (𝑓𝑟𝑜𝑡 ) 50 Hz

Table 4
Comparison of experimentally obtained 𝑇 𝐻𝐷50 of output voltage of CHB-MLC for different methods.
Method/𝑚𝑎 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
S-PD-LS-PWM 58.48 40.28 37.26 31.58 23.32 22.73 22.15 16.47
T-PD-LS-PWM 45.95 38.58 37.22 29.98 22.57 24.77 23.64 17.40
S-SC-PWM [17] 57.75 40.42 37.56 31.24 23.23 22.94 21.73 16.24
TSC-PWM 46.03 38.20 36.07 28.75 21.71 22.93 21.60 15.15

Table 5
Comparison of experimentally obtained fundamental amplitude of output voltage of CHB-MLC for different methods.
Method/𝑚𝑎 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
S-PD-LS-PWM 3.47 4.61 5.74 6.75 7.85 8.93 9.92 11.12
T-PD-LS-PWM 3.93 5.29 6.58 7.73 9.05 10.28 11.52 12.49
S-SC-PWM [17] 3.51 4.67 5.74 6.79 7.95 9.02 10.08 11.12
TSC-PWM 3.98 5.30 6.54 7.91 9.16 10.19 11.57 12.16

the seven-level output voltage obtained by different methods are presented in Fig. 12. As seen, only the harmonics that are up to
50th are provided in the figure. Here, it is critical to realize that even harmonics are not present in the harmonic spectrum for
S-SC-PWM and the proposed TSC-PWM. This means that output voltage waveform that is generated by the proposed TSC-PWM
contains no even harmonics. Therefore, both half-wave and quarter-wave symmetries are ensured at the output with the utilization
of the proposed TSC-PWM. Moreover, 𝑇 𝐻𝐷50 results given in Fig. 12 comply with the values given in Fig. 10a. Finally, Fig. 13
demonstrates the gating signals in each module of CHB-MLC. It can be inferred from the figure that gating signals are interchanged
between semiconductors of all modules so that equal power sharing is ensured at three rotational periods.

6. Experimental results

In order to validate the implementation of the proposed TSC-PWM and the other methods mentioned in this study on FPGA, a
laboratory prototype of a single-phase three-module CHB-MLC is built as seen in Fig. 14. Design parameters of the experimental
setup are given in Table 3. Separate Li-Ion batteries with 3.7 V nominal voltage are utilized as input DC sources. Xilinx Zynq-7000
Zybo Z7-10 FPGA board is employed to generate switching signals for all methods. All output voltage waveforms are obtained by
Tektronix TPS2024 digital storage oscilloscope. Similar to simulation analysis, S-PD-LS-PWM, T-PD-LS-PWM, S-SC-PWM [17] and
the proposed TSC-PWM are compared in terms of 𝑇 𝐻𝐷50 and 𝑉𝑜𝑢𝑡,𝑓 𝑢𝑛𝑑 for different modulation indices.
Results of this performance comparison are given in Tables 4 and 5. Note that the best result at each column is given bold for
both tables. As seen in Table 4, harmonic performance of trapezoidal reference based methods is better than sinusoidal reference
based techniques especially for modulation indices that are less than 0.7. For higher modulation indices, the proposed TSC-PWM
provides the best harmonic performance among all methods. Table 5 presents comparison of experimentally obtained fundamental
amplitude of output voltage of CHB-MLC for all methods. It can be seen that, trapezoidal reference based methods provide much
higher fundamental voltage compared to sinusoidal reference based methods for all modulation indices. Hence, it is verified by
experiments that trapezoidal reference based methods, especially the proposed TSC-PWM, is superior compared to sinusoidal
reference based schemes in terms of harmonic performance and DC voltage utilization. Finally, Fig. 15 shows oscilloscope waveforms
of experimentally obtained output voltage and current of CHB-MLC for all methods when 𝑚𝑎 = 0.8.

7. Conclusions

A large and growing body of literature has investigated MLCs and PWM methods in the last decade. MLCs work in a way that
multi carrier PWM schemes are employed so that multilevel waveform is obtained at the output. In real life applications, it is critical
to implement those PWM schemes on digital systems in an efficient manner. Here, FPGAs come into play due to their high parallel
processing feature. Besides being able to achieve high number of levels with the help of FPGAs, reducing the resource utilization
within the FPGA is of major significance as well. For this reason, researchers focus on SC-PWM schemes. The main purpose in those
schemes is to mimic the switching behavior of a multi carrier PWM schemes, mostly LS-PWM, to generate multilevel waveform at
the output of MLC. It is achieved by rescaling the raw sinusoidal reference signal, to a single carrier level before passing the raw
PWM through some gate decoding process. Eventually, a multilevel waveform is attained at the output of MLC.

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F. Eroğlu and M. Kurtoğlu Computers and Electrical Engineering 107 (2023) 108650

Fig. 14. Laboratory prototype of a single-phase 3-module CHB-MLC.

Fig. 15. Oscilloscope waveforms of the output voltage and current of CHB-MLC for different methods (a) S-PD-LS-PWM, (b) T-PD-LS-PWM, (c) S-SC-PWM [17],
(d) TSC-PWM (𝑚𝑎 = 0.8).

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F. Eroğlu and M. Kurtoğlu Computers and Electrical Engineering 107 (2023) 108650

Producing sinuosoidal reference from the scratch is a challenging task in FPGAs. That is why LUTs are employed to store
the previously generated sinusoidal values within the memory of FPGAs. However, this increases the resource utilization as well.
Recently, use of trapezoidal reference instead of sinusoidal has become popular in the literature due to advantages of trapezoidal
signal in terms of better output voltage quality and higher fundamental amplitude generation. It has been employed in some multi
carrier PWM schemes by using LUTs, similar to sinusoidal case. Moreover, details of FPGA implementation has never been provided.
This paper proposes a trapezoidal reference based SC-PWM named as TSC-PWM for MLCs. First, features of trapezoidal reference
is investigated and best parameters are determined in terms of better output voltage quality. Then, properties of the proposed TSC-
PWM is presented. Later, architectural details of the FPGA implementation of TSC-PWM is given by providing the pseudocodes of
each module that constitutes the overall behavioral design. Here, two types of approaches are presented to generate trapezoidal
reference: counter and LUT based. Performance comparison of both types of TSC-PWM is held to other similar methods in the
literature by implementing those methods on an actual FPGA. It is revealed that the proposed TSC-PWM successfully reduces
the resource utilization within FPGA. Finally, a single-phase three-module CHB-MLC is built in both simulation and experimental
platforms. The results reveal that the proposed TSC-PWM is superior compared to similar methods in terms of harmonic performance
and DC utilization ratio.

CRediT authorship contribution statement

Fatih Eroğlu: Conceptualization, Visualization, Methodology, Software, Writing – original draft. Mehmet Kurtoğlu: Data
curation, Writing – review & editing.

Declaration of competing interest

No author associated with this paper has disclosed any potential or pertinent conflicts which may be perceived to have impending
conflict with this work. For full disclosure statements refer to https://doi.org/10.1016/j.compeleceng.2023.108650.

Data availability

No data was used for the research described in the article.

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Fatih Eroglu received his B.S. degree from Ihsan Dogramaci Bilkent University, Department of Electrical and Electronics Engineering in 2015; M.S. and Ph.D.
degrees at Gaziantep University, Department of Electrical and Electronics Engineering in 2018 and 2022 respectively, where he is currently working as research
assistant. His research interests include control of power converters for renewable energy and battery storage systems.

Mehmet Kurtoglu received his B.S. degree from the Department of Electrical and Electronics Engineering, Çukurova University, Adana, Turkey, in 2014; and his
M.S. and Ph.D. degrees from the Department of Electrical and Electronics Engineering, Gaziantep University, Gaziantep, Turkey, in 2017 and 2022, respectively.
His research interests include multilevel converters, modulation techniques, energy conversion systems and applications of power electronic systems.

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