CS 322 – Computer

Organization
Lectures – 5 & 6
Dr. Ahmed Hesham Mostafa
 Chapter 5
Basic Computer Organization And
Design
Part1
Basic Computer
Organization And Design
• Instruction Codes
• Computer Registers
• Computer Instructions
• Timing and Control
• Instruction Cycle
• Memory Reference Instructions
• Input-Output and Interrupt
• Complete Computer Description
• Design of Basic Computer
• Design of Accumulator Logic

3
Instruction Codes
• Every different processor type has its own design (different registers, buses,
microoperations, machine instructions, etc)
• Modern processor is a very complex device
• It contains
• Many registers
• Multiple arithmetic units, for both integer and floating-point calculations
• The ability to pipeline several consecutive instructions to speed execution

4
Instruction Codes
• However, to understand how processors work, we will
start with a simplified processor model
• This is similar to what real processors were like ~25
years ago
• M. Morris Mano introduces a simple processor model
he calls the Basic Computer
• We will use this to introduce processor organization
and the relationship of the RTL model to the higher-
level computer processor
• Computer organization: - set of registers, memory size
(word size, one memory for instructions and data or
separated?), buses (data, address), machine
microoperations (based on ALU), machine instructions,
instruction format

5
The Basic
Computer
• The Basic Computer has two components, a processor and
memory
• The memory has 4096 words (4 k) in it
• 4096 = 212, so it takes 12 bits to select a word in
memory
• Each word is 16 bits long
• Four bits for the operation code (opcode) to specify one
out of 16 possible operations, 12 bits to specify the
address of an operand.
• The control reads a 16-bit instruction from the program
portion of memory. It uses the 12-bit address part of the
instruction to read a 16-bit operand from the data portion
of memory. It then executes the operation specified by the
6
operation code.
Instructions
• A program
• It is a set of (machine) instructions that specify the operations, operand, and the
sequence (control)
• A (machine) instruction
• It is a binary code that tell the computer to perform a specific operation (a sequence
of microoperations).
• The instructions of a program, along with any needed data are stored in memory
• The CPU reads each instruction from memory and places it in an Instruction Register (IR).
• Control circuitry in control unit then decodes the instruction into the sequence of
microoperations necessary to execute it.

7
Computer Registers
• A processor has many registers to hold instructions, addresses, data, etc…
• In Basic Computer, the processor has:
• Program Counter (PC) holds the memory address of the next instruction to get.
• The PC only needs 12 bits
• Address Register (AR) is used by processor to keep track of what locations in memory it is addressing (direct or
indirect addressing)
• The AR is 12 bits register
• Instruction Register (IR) holds the instruction read from memory
• It is 16 bits register
• Data Register (DR) it is where the operand is placed (either using either direct or indirect addressing)
• It is 16 bits register.
• Temporary Register (TR) is a scratch register to store intermediate results or other temporary data
• It is 16 bits register.
 Instruction codes

Computer Registers (Cont.)

• The Basic Computer has
• A single general-purpose register – the Accumulator (AC)
• It is 16 bits register
• The significance of a general-purpose register is that it can be referred to in instructions
• e.g., load AC with the contents of a specific memory location; store the contents of AC
into a specified memory location
• If an operation in an instruction code does not need an operand from memory, the rest
of the bits in the instruction can be used for other purposes.
• For example, operations such as clear AC, complement AC, and increment AC operate on
data stored in the AC register. They do not need an operand from memory.
• For these types of operations, the second part of the instruction code (bits 0 through 11)
is not needed for specifying a memory address and can be used to specify other
operations for the computer.

9
Computer Registers (Cont.)

• The Basic Computer uses a very simple model of input/output (I/O) operations
• Input devices are considered to send 8 bits of character data to the processor
• The Input Register (INPR) holds an 8-bit character gotten from an input device
• The processor can send 8 bits of character data to output devices
• The Output Register (OUTR) holds an 8-bit character to be sent to an output
device
 Basic Computer Registers
Registers in the Basic Computer

11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
11
 Common Bus System

The registers in the Basic Computer are connected using

a bus system.

This gives a savings in circuitry over complete

connections between registers

Amore efficient scheme for transferring information in a

system with many registers is to use a common bus.

We have shown in Ch. 4 how to construct a bus system

using multiplexers or three-state buffer gates.

12
 s0 s1 s2
Common Bus System Bus
Memory Unit
7
4096x16
Address
WRITE READ
AR 1 S2 S1 S0 Register
LD INR CLR 0 0 0 None
PC 2 0 0 1 AR
Question 1 LD INR CLR
0 1 0 PC
DR 3
Question 2
LD INR CLR 0 1 1 DR
Adder E 1 0 0 AC
& Logic
AC 4
LD INR CLR 1 0 1 IR
INPR 1 1 0 TR
IR 5 1 1 1 Memory
LD INR CLR
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus 13
Computer System Architecture, Mano, Copyright (C) 1993 Prentice-Hall, Inc.
 Common Bus System

• The outputs of seven registers and memory are connected to the common bus. The specific
output that is selected for the bus lines at any given time is determined from the binary value of
the selection variables S2, S1, and S0
• The number along each output shows the decimal equivalent of the required binary
selection.
• For example, the number along the output of DR is 3. The 16-bit outputs of DR are placed on the
bus lines when S2S1S0 = 011 since this is the binary value of decimal 3.
• The lines from the common bus are connected to the inputs of each register and the data inputs
of the memory. The particular register whose LD (load) input is enabled receives the data from
the bus during the next clock pulse transition.
• The memory receives the contents of the bus when its write input is activated. The memory
places its 16-bit output onto the bus when the read input is activated and S2S1S0 = 111.

15
 Common Bus System

• The 12-bit registers, AR and PC, have 0’s loaded onto the bus in the high order 4 bits positions
• When the 8-bit register OUTR is loaded from the bus, the data comes from the low order 8 bits on
the bus
• INPR is connected to provide information to the bus but OUTR can only receive information from
the bus.
• This is because INPR receives a character from an input device which is then transferred to AC .
OUTR receives a character from AC and delivers it to an output device. There is no transfer from
OUTR to any of the other registers.
Common Bus System

• The 16 lines of the common bus receive information from six registers and the memory
unit.
• The bus lines are connected to the inputs of six registers and the memory.
• Five registers have three control inputs: LD (load), INR (increment), and CLR (clear). This
type of register is equivalent to a binary counter with parallel load and synchronous clear.
• The increment operation is achieved by enabling the count input of the counter.
• Two registers have only an LD input.
Common Bus System

• The input data and output data of the memory are connected to the common bus, but
the memory address is connected to AR . Therefore, AR must always be used to specify a
memory address. By using a single register for the address, we eliminate the need for an
address bus that would have been needed otherwise.
• The content of any register can be specified for the memory data input during a write
operation. Similarly, any register can receive the data from memory after a read
operation except AC .
Common Bus System

• The 16 inputs of AC come from an adder and logic circuit. This circuit has three sets of
inputs. One set of 16-bit inputs comes from the outputs of AC.
• They are used to implement register microoperations such as complement AC and shift
AC.
• Another set of 16-bit inputs comes from the data register DR. The inputs from DR and
AC are used for arithmetic and logic micro-operations, such as adding DR to AC or AND
DR to AC.
• The result of an addition is transferred to AC and the end carry-out of the addition is
transferred to flip-flop E (extended AC bit).
• The third set of 8-bit inputs comes from the input register INPR.
Common Bus System

• Note that the content of any register can be applied onto the bus and an operation can
be performed in the adder and logic circuit during the same clock cycle.
• The clock transition at the end of the cycle transfers the content of the bus into the
designated destination register and the output of the adder and logic circuit into AC. For
example, the two microoperations :
• DR AC , AC  DR can be executed at the same time.
• This can be done by placing the content of AC on the bus (with S2S1S0= 100), enabling the
LD (load) input of DR, transferring the content of DR through the adder and logic circuit
into AC, and enabling the LD (load) input of AC, all during the same clock cycle. The two
transfers occur upon the arrival of the clock pulse transition at the end of the clock cycle.
 Question 1

• The following control inputs are

active in the bus system shown in
Fig. 5-4. For each case, specify the
register transfer that will be
executed during the next clock
transition.

• Answer

21
 Question 2
• The following register transfers are to be executed in the system of Fig. 5-4.
For each transfer, specify: (1)the binary value that must be applied to bus
select inputs S2, S1 and S0 (2) the register whose LD control input must be
active (if any);(3) a memory read or write operation (if needed) and (4) the
operation in the adder and logic circuit (if any).
a) AR  PC Answer

b) IR  M[AR]
c) M[AR]  TR
d) AC  DR, DR  AC

22
 Question 3
• Explain why each of the following microoperations ns cannot be executed during a single clock pulse in the
system shown in Fig. 5-4. Specify a sequence of microoperations that will perform the operation.
• a. IR M[PC]
• b. AC  AC + TR
• c. DR  DR + AC (AC does not change)
(a) IR ← M[PC] PC cannot provide the address to memory. Address must be transferred to AR first
AR← PC
IR ← M[AR]
(b) AC ← AC + TR Add operation must be done with DR. Transfer TR to DR first.
DR ← TR
AC ← AC + DR
(c) DR ← DR + AC Result of addition is transferred to AC (not DR). To save the value of AC its content must be stored
temporarily in DR (or TR).
AC ← DR, DR ← AC (See answer to Question 3(d))
AC ← AC + DR
AC ← DR, DR ← AC
23
 Instruction Format
• A computer instruction is often divided into two parts:
• An opcode (Operation Code) that specifies the operation for that instruction
• An address that specifies the registers and/or locations in memory to use for that operation

• In Basic Computer,
• Memory contains 4096 (= 212) words, so we needs 12 bits to specify which
memory address this instruction will use
• Bit 15 of the instruction specifies the addressing mode (0: direct addressing, 1:
indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits long, that
leaves 3 bits for the instruction’s opcode
15 14 12 11 0
I Opcode Address
Addressing
mode Instruction Format
24
 Addressing Modes
• The address field of an instruction can represent either
• Direct address: the address in memory of the data to use (the address of the operand), or
• Indirect address: the address in memory of the address in memory of the data to use

ACAC +M[457] ACAC + M[M[300]]

AC AC

• Effective Address (EA) Effective address: 457 Effective address: 1350

• Address where an operand is physically located
25
 Computer Instructions
Memory-Reference Instructions (OP-code = 000 ~ 110)
• Basic Computer Instruction Format

Op-code
15 14 12 11 0
I Opcode Address (3 bits)
000
Register-Reference Instructions (OP-code = 111, I = 0) 001
15 14 12 11 0 010
0 111 Register operation 011
100
101
Input-Output Instructions (OP-code =111, I = 1)
110
111
15 14 12 11 0
1 111 I/O operation

26
Basic Hex Code
Computer Symbol
AND
I=0
0xxx
I=1
8xxx
Description
AND memory word to AC Memory-
Instructions ADD
LDA
1xxx
2xxx
9xxx
Axxx
Add memory word to AC
Load AC from memory reference
STA 3xxx Bxxx Store content of AC into memory instruction
BUN 4xxx Cxxx Branch unconditionally
Op-code BSA 5xxx Dxxx Branch and save return address (OP-code = 000 ~ 110)
I=0 (Hex) I=1(Hex) ISZ 6xxx Exxx Increment and skip if zero I=0: 0xxx ~ 6xxx,
0000(0) 1000(8) I=1: 8xxx ~ Exxx
CLA 7800 Clear AC
0001(1) 1001(9) CLE 7400 Clear E
0010(2) 1010(A) CMA 7200 Complement AC
0011(3) 1011(B) CME 7100 Complement E Register-
0100(4) 1100(C)
CIR 7080 Circulate right AC and E reference
CIL 7040 Circulate left AC and E
0101(5) 1101(D) INC 7020 Increment AC instruction
0110(6) 1110(E) SPA 7010 Skip next instr. if AC is positive
0111(7) 1111(F) SNA 7008 Skip next instr. if AC is negative (OP-code = 111, I = 0)
SZA 7004 Skip next instr. if AC is zero 7xxx
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

Input-
OUT F400 Output character from AC output
SKI F200 Skip on input flag
SKO F100 Skip on output flag
instruction
ION F080 Interrupt on (OP-code =111, I = 1)
IOF F040 Interrupt off Fxxx
27
 Question
• A computer uses a memory unit with 256K words of 32
bits each. A binary instruction code is stored in one
word of memory. The instruction has four parts: an
indirect bit. an operation code, a register code part to
specify one of 64 registers, and an address part.
• a. How many bits are there in the operation code, the
register code part, and the address part? Total=18+6+1 =

• b. Draw the instruction word format and indicate the

number of bits in each part.
• c. How many bits are there in the data and address
inputs of the memory?

28
 Question

Each time start with

AC=A937 and E=1
Then apply the register-
reference instructions from
the previous table

29
 Question

Answer

30
 Question

CLE \*Clear E *\
CME \*Complement E *\

31
 • A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function
that is known to be computable.
• Instruction Types
• Functional Instructions
• - Arithmetic, logic, and shift instructions
• - ADD, CMA, INC, CIR, CIL, AND, CLA
• Transfer Instructions
Instruction Set • - Data transfers between the main memory and the
processor registers
Completeness • - LDA, STA
• Control Instructions
• - Program sequencing and control
• - BUN, BSA, ISZ
• Input/Output Instructions
• - Input and output
• - INP, OUT

32
Timing and Control

The timing for all registers in the basic computer is controlled by a master clock generator.

The clock pulses are applied to all flip-flops and registers in the system, including the flip-flops and
registers in the control unit.

The clock pulses do not change the state of a register unless the register is enabled by a control
signal.

The control signals are generated in the control unit and provide control inputs for the multiplexers
in the common bus, control inputs in processor registers, and microoperations for the accumulator.
 Control unit (CU) of a processor translates from machine instructions to
the control signals for the microoperations that implement them

Control units are implemented in one of two ways

Hardwired Control (optimized to produce a fast mode of operation)

Control Unit • CU is made up of sequential and combinational circuits to generate

the control signals

Microprogrammed Control(Chapter 7)

• A control memory on the processor contains microprograms that

activate the necessary control signals
We will consider a hardwired implementation of the control unit for the
Basic Computer

34
Control unit of Basic Computer
Instruction register (IR)
15 14 13 12 11 - 0 Other inputs

Op-code
3x8 (3 bits)
decoder 000
7 6543 210
D0 001
I
D7
Combinational
Control
010
Control
logic signals 011
T15
100
T0
101
110
15 14 . . . . 2 1 0 111
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock
Control unit of Basic Computer

• The block diagram of the control unit consists of two decoders, a sequence counter, and a
number of control logic gates.
• An instruction read from memory is placed in the instruction register (IR).
• The operation code in bits 12 through 14 is decoded with a 3 x 8 decoder.
• The eight outputs of the decoder are designated by the symbols D0 through D7
• The subscripted decimal number is equivalent to the binary value of the corresponding operation
code.
• Bit 15 of the instruction is transferred to a flip-flop designated by the symbol I.
• Bits 0 through 11 are applied to the control logic gates.
• The 4-bit sequence counter can count in binary from 0 through 15. The outputs of the counter are
decoded into 16 timing signals T0 through T15
 T0 T1 T2 T3 T4 T0

Timing Signals Clock

T0

T1
• Generated by 4-bit sequence counter
and 416 decoder T2

• The SC can be incremented or cleared. T3

T4
• Example: T0, T1, T2, T3, T4, T0, T1, . . .
• Assume: At time T4, SC is cleared to 0 D3
if decoder output D3 is active.
• D3T4: SC  0 CLR
SC

37
 T0 T1 T2 T3 T4 T0

Timing Signals Clock

T0

T1
• The last three waveforms in Fig. show how SC is cleared
when D3T4 = I.
T2
• Output D3 from the operation decoder becomes active
at the end of timing signal T2
T3
• When timing signal T4 becomes active, the output of the
AND gate that implements the control function D3T4
T4
becomes active.
• This signal is applied to the CLR input of SC. On the next
D3
positive clock transition (the one marked T, in the
diagram) the counter is cleared to 0.
CLR
• This causes the timing signal To to become active instead SC
of T5 which would have been active if SC were
incremented instead of cleared.
Question

39
 S E R IEN FGI FGO DR

instruction register (IR)

15 14 13 12 11-0 AC

3x8
decoder
7 6 5 4 3 2 1 0
D0

...
D7 Control
I logic
gates
T15

...
T0
...
15 14 .... 2 1 0
4x6
decoder

(INR)
4-bit
(CLR)
Sequence
Counter (SC) Clock
40
Instruction Cycle
• In Basic Computer, a machine instruction is executed in the following cycle:
1. Fetch instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect address
4. Execute the instruction
• This cycle repeats indefinitely unless a HALT instruction is
encountered
• Note: Every different processor has its own (different) instruction cycle

41
Instruction Cycle Fetch and Decode
• Fetch and Decode T0: AR  PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1 S2

T0 S1 Bus

S0
Memory
7
Fetch:
unit IRM[PC]
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus 42
Instruction Cycle Fetch and Decode
• Initially, the Program Counter (PC) is loaded with the address of the first instruction in
the program
• The sequence counter SC is cleared to 0, providing a decoded timing signal T0
• After each clock pulse, SC is incremented by one, so that the timing signals go through a
sequence of T0, T1, T2, and so on
• T0: AR←PC (this is essential!!) The address of the instruction is moved to AR.
• T1: IR←M[AR], PC←PC+1 The instruction is fetched from the memory to IR, and the PC
is incremented.
• T2: D0,…, D7←Decode IR(12-14), AR←IR(0-11), I←IR(15)
Determine The Type Of Instruction
Start
SC  0

T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

44
 Determine The Type Of Instruction
• Decoder output D7 is equal to 1 if the operation code is equal to
binary 111 . if D7 = I, the instruction must be a register-reference or
input-output type.
• If D7 = 0, the operation code must be one of the other seven values
000 through 110, specifying a memory-reference instruction.
• So D7 =1 if opcode =111 otherwise the D7 =0
• If D7 = 0 and I = 1, we have a memory reference instruction with an
indirect address. It is then necessary to read the effective address
from memory. AR  M[AR]
 Determine The Type Of Instruction
• The three instruction types are subdivided into four separate paths.
The selected operation is activated with the clock transition
associated with timing signal T3. This can be symbolized as follows:
• D'7IT3: AR  M[AR]
• D'7I'T3: Nothing
• D7I'T3: Execute a register-reference instr.
• D7IT3: Execute an input-output instr.
 Register Reference Instructions
Register Reference Instructions are identified when
• D7 = 1, I = 0
• Register Ref. Instr. is specified in b0 ~ b11 of IR
• Execution starts with timing signal T 3
• Each control function needs the Boolean relationr = D7 IT3 which we refered for
convenience by the symbol r.
• r = D7 IT3
• The control function is distinguished by one of the bits in IR(0-11) By assigning
the symbol Bi, to bit i of IR, r: SC  0
• all control functions can be simply CLA rB11: AC  0
denoted by rBi. CLE rB10: E0
• Bi = IR(i) , i=0,1,2,...,11 CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop)
 Memory Reference Instructions
Operation
Symbol Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
49
 Memory Reference Instructions
Memory, PC, AR at time T4 Memory, PC after execution
20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

LDA: Load to AC AR = 135 135 21

D2T4: DR  M[AR] 136 Subroutine PC = 136 Subroutine
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally 1 BUN 135 1 BUN 135
D4T4: PC  AR, SC  0 Memory Memory

BSA: Branch and Save Return Address

D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0
50
Flowchart For Memory Ref. Instructions
Memory-reference instruction

AND ADD LDA STA

D0 T 4 D1 T 4 D2 T 4 D 3T 4
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0

D0 T 5 D1 T 5 D2 T 5
AC  AC  DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D4 T 4 D5 T 4 D6 T 4
PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5 T 5 D6 T 5

PC  AR DR  DR + 1
SC  0
D6 T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0
 Question

Each time start with E=0 , AC=A937, PC=021

Then apply the memory-reference instructions from the previous table

52
 Question
7FF EA9F

A9F 0C35

C35 FFFF

Memory

T0: AR  PC
T1: IR  M [AR], PC  PC + 1
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)
D’7 I T3 :AR  M[AR] read affective address as I=1 and D7=0
ISZ: Increment and Skip-if-Zero
D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0
 Question
3AF 932E

32E 09AC

9AC 8B9F

(a) AR=PC =3AF so IR  M [AR], Memory

IR= 932E , so 9 =1001 refer to ADD operation and I=1
So operation is ADD 32E so AR =32E
Note:indirect mode , so AR =M[AR]= 09AC
so DR will be DR=M[AR]= 8B9F
(b) AC =AC +DR
AC= 7EC3 + 8B9F = 0A62 and E=1 T0: AR  PC (S0S1S2=010, T0=1)
(C) PC = 3AF + 1 =3B0 T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
IR = 932E T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)
D’7 I T3 :AR  M[AR] read affective address as I=1 and D7=0
DR = 8B9F ADD to AC
AC= 0A62 D1T4: DR  M[AR] Read operand
E=1 D1T5: AC  AC + DR, E  Cout, SC  0
I=1
SC =0
Note :
Log2(65536)=16
Thanks

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