PAE2248 System-on-Chip Design

UI-SoC Design Issues

L6: Architecture of the SoC

Presented By
Dr. V. Vaithianathan
Associate Professor, ECE Dept
 Lesson Plan
Sl. No. of
Lecture
No Hours
L1 Architecture of the SoC 1
L2 Design Issues of SoC 1

Hardware-Software Codesign - Codesign Flow &

L3 2
Codesign Tools

L4 Core Libraries, EDA tools, Web Pointers 1

L5 SoC Design Flow 1
L6 General Guidelines for Design Reuse 1
L7 On Chip Buses – Clock Distribution 1
L8 Physical Design and Deliverable Models 1
 Lecture 6
• General Guidelines for Design Reuse
 Session Objectives
• To learn the General Guidelines for Design Reuse
 Session Outcomes
• At the end of this lecture, the students will
be able to know about
– General Guidelines for Design Reuse
 General Guidelines for Design
Reuse
• A number of precautions must be taken at various
design steps to ensure design reusability.
• Some of these precautions are basic common-sense
while others are specific architectural or physical
design guidelines.
• Synchronous Design
• Memory and Mixed-Signal Design
• On-Chip Buses
• Clock Distribution
• Clear/Set/Reset Signals
• Physical Design
• Deliverable Models
 Synchronous Design
• Synchronous design style is extremely useful for core-
based SoC design.
• In synchronous design, data changes based on clock
edges only (and, hence, instructions and data) are
easily manageable.
• Use of registers in random logic as well as registration
at the inputs and outputs of every core as shown in
figure 1.12 is very useful in managing core-to-core
interaction.
• Such registration essentially creates a wrapper
around a core.
• Besides providing synchronization at the core
boundary, it also has other benefits such as portability
and application of manufacturing test.
 Synchronous Design

Figure 1.12 Use of registers for synchronization in core logic

and its inputs and outputs.
 Synchronous Design
• Latch-based designs on the other hand are not easy
to manage because the data capture is not based on
a clock edge; instead, it requires a longer period of an
active signal.
• It is thus useful to avoid latches in random logic and
use them only in blocks such as FIFOs, memories,
and stacks.
• In general, asynchronous loops and internal pulse
generator circuits should be avoided in the core
design.
• Similarly, multicycle paths and direct combinational
paths from block inputs to outputs should be avoided.
• If there are any asynchronous clear and set signals,
then their deactivation should be resynchronized.
 Synchronous Design
• Furthermore, the memory boundaries at which read,
write, and enable signals are applied should be
synchronous and register-based.
Memory and Mixed-Signal Design
• Most embedded memories in SoC are designed using
memory compilers.
• While the memory design itself is technology
dependent, some basic rules are very useful in SoC-
level integration.
• In large memories, the parasitics at the boundary cell
are substantially different than the parasitics of a cell
in the middle of an array.
• To minimize this disparity, it is extremely useful to
include rows and columns of dummy cells at the
periphery of large memories as shown in figure
1.13(a).
Memory and Mixed-Signal Design
• To minimize the area overhead penalty because of
these dummy cells, these rows and columns should
be made part of the built-in self-repair (BISR)
mechanism.
• BISR allows a bad memory cell to be replaced and
improves the manufacturing yield.
• While the large memories are generally placed along
the side or corner of the chip, small memories are
scattered all over the place.
• If not carefully planned, these small memories create
a tremendous hurdle in chip-level routing.
• When implementing these small memories, it is
extremely useful for the metal layers to be kept less
than the technology allowable layers.
Memory and Mixed-Signal Design
• Subsequently, these metals can be used to route
chip-level wires over the memories.
• In present-day SoC design, more than 60% of the
chip is memories; mixed-signal circuits make up
hardly 5% of the chip area.
• The most commonly used analog/mixed-signal circuits
used in SoC are PLLs, digital-to-analog converters
(DACs), analog-to-digital converters (ADCs), and
temperature sensors.
• These circuits provide specialized functionality such as
on-chip clock generation, synchronization, RGB
output for color video display, and communication
with the outside world.
Memory and Mixed-Signal Design

Figure 1.13 (a) Use of dummy cells with memory array.

(b) Placement of memory and analog circuits at SoC level.
Memory and Mixed-Signal Design
• Because these blocks are analog/mixed-signal
circuits, they are extremely sensitive to noise and
technology parameters.
• Thus, it is useful to place these circuits at the corners
as shown in figure 1.13(b).
• This also suggests that placing the I/Os of the analog
circuit on only two sides is somewhat useful in
simplifying their placement at the SoC level.
• Further, the use of guard-bands and dummy cells
around these circuits (as shown in figure 1.13) is
useful to minimize noise sensitivity
 Review Questions
1. What is the design for reuse?
2. How is design reuse implemented?
3. What is IP reuse?
4. How do you design for reuse?
5. List out General Guidelines for Design Reuse.
6. What is synchronous design?
7. What is synchronous design in SoC? Explain.
8. What is mixed-signal design?
9. What is mixed-signal in SoC?
10.What is mixed-signal microcontroller?
11.What is a mixed-signal application in SoC?
 Session Summary
• In this lecture, we have discussed about
– General Guidelines for Design Reuse
 Text Books & References
1. Rochit Rajsuman, “System-on-a-chip: Design and
Test”, Advantest America R & D Centre, 2000.
2. Hubert Kaeslin, “Digital Integrated Circuit Design: From
VLSI Architectures to CMOS Fabrication”, Cambridge
University Press, 2008.
3. B. Al Hashimi, “System on chip-Next generation
electronics”, The IET, 2006.
4. P Mishra and N Dutt, “Processor Description Languages”,
Morgan Kaufmann, 2008.
5. Michael J. Flynn and Wayne Luk, “Computer System
Design: System-on-Chip”, Wiley, 2011.
Thank You