Digital Verification Intro
Digital Verification Intro
Introduction Session
Verification
is the process of checking that a software achieves its goal without any
bugs. It is the process to ensure whether the product that is developed
is right or not. It verifies whether the developed product fulfills the
requirements that we have. Verification is static testing.
Verification means Are we building the product, right?
Validation
is the process of checking whether the software product is up to the
mark or in other words product has high level requirements? It is the
process of checking the validation of product i.e. it checks what we are
developing is the right product. it is validation of actual and expected
product. Validation is the dynamic testing.
Validation means Are we building the right product?
(unit testing – system testing)
Digital Flow:
Companies:
• Si-vision (Major)
• Si-ware systems / Goodex (Major)
• ICpedia (Major)
• ADI (Analog Devices)
• MIXEL
• Riot Micro (STM)
• MEMS vision -Varkon - Vidatronic- Wasiela – TTC - Scenario
• VALEO (FPGA PROTOPYING - VALIDATION)
• Mentor (FPGA PROTOPYING- EMULATION)
• NXP, QUALCOMM, Synopsys, ST, Maxim, Intel, Microchip, Apple,
Xilinx, Altera, Nvidia, Marvell, etc.
Types of digital verification:
• Dynamic (front end) vs static (synthesis process)
• Coverage driven verification Functional (directed Vs Randomized)
• Assertion Based
• Co-simulation (analog and digital)
• Sub-Systems verification
• hardware-assisted verification (FPGA prototyping -Emulation)
https://semiwiki.com/eda/cadence/4980-whats-the-difference-
between-emulation-and-prototyping/
(Dr: Mohamed Dessouky -CAD for Digital Design, lec 18-)
• Power Aware Verification (clock gating – power gating)
• Modeling: SystemC (blocks In Mentor) – Matlab (Arch level)
• Formal (Boolean) – Back end related-
• Physical Verification (LVS) – Back end related-
• DFT – Back end related-
UVM Environment
Job Description:
• Extract verification requirements from system specification.
• Contribute in generating the verification plan for block level.
• Contribute in architecting the verification environment which is
mapped from the verification plan for block level.
• Implement the verification environment using UVM.
• Debug test failures and work with designers to develop fixes.
• Work on achieving targeted coverage goal for the verification sign
off for block level.
• Perform Co-simulation activities and work with analog and digital
teams to gather Co-sim requirements and develop fixes on the
interaction between analog and digital parts in the IP
Skills:
• Detailed Oriented/Debugging Skills.
• Working under Pressure (Releases/Tape out)
• Teamwork
• Problem solving
What to study:
• Digital Flow (HDL language) ASIC/FPGA
• Coverage Driven Verification Concepts
• System-Verilog / System-Verilog Assertion
• UVM (environment view)
• OOP concepts (c++, java)
• scripting (Perl, TCL, Python)
• Digital Project at companies or internships (ex : Si-Vision)
• ITI diploma for Digital Field
• Communication Protocols: SPI, UART,,, etc.
• Wireless Communication, High speed links,,-Protocols optional-
Digital Resources
• VLSI ACADEMY
• VLSI-Egypt Page
• Dr: Paul Franzon (digital Course YouTube)
• Principle of VLSI RTL design (book)
• VLSI physical Design (NPTEL YouTube )
• Digital Course (Dr: Hisham Omran YouTube)
• CU , Dr: Karim Ossama (digital electronics course)
• ASU , Dr: Mohamed Dessouky (CAD for Digital Design)
Verification Resources:
• Language LRM (system Verilog)
• Accellera UVM user guide / class reference
• verification academy Mentor (basic – advanced)
• verification excellence
• Udemy Ramdas course
• Chris spear (springer book): system Verilog for verification
• Janick Bergeron: writing testbench using verification
• Tutorials: testbench.in , chipverify.com , asic-world.com
• OOP/C++ Tutorials : https://www.tutorialspoint.com/index.htm
• RTL/projects: opencores.com
• Eng.Sameh ALashry :
https://www.slideshare.net/Ash-Ash/functional-verification-
techniques-ew16-session
• Eng.Mohamed Alaa:
https://www.facebook.com/groups/1418463171538052/permalin
k/1894324237285274/
• Cliff Cumming: https://www.sunburst-design.com/papers/
• Pedro Thesis: https://colorlesscube.com/uvm-guide-for-
beginners/