Section 11

Hardware
 8088
8088 is a 40-pin microprocessor chip that can
work
in two modes: minimum mode and maximum
mode.
Maximum mode is used to connect to 8087
coprocessor. If a coprocessor is not needed,
8088 is used in minimum mode.
8088 vs 8086
Pins 9-16 (AD0–AD7) are
used for both data and
addresses in 8088.

AD stands for
"address/data.”

The ALE (address latch

enable) pin signals
whether the information
on pins AD0–AD7 is
address or data.
Memory
ROM: Read Only Memory (non-volatile)
RAM: Radom Access Memory (volatile)
Transistors (Faster)

Transistors Capacitors
(Faster) (Smaller cell size)
High density
EEPROM can be programmed while in its system
board socket, The program/erase cycle is
500,000 for Flash and EEPROM; 2000 for UV-
EPROM
1 address pin

1
2 address pins

0 0

0 1

1 0

1 1
3 address pins

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1
Number of locations = 2^number of address pins
Size of each locations = # of data pins
1 address pin

1
1 address pin

1
1 address pin

1
2 address pins

0 0

0 1

1 0

1 1
2 address pins

0 0

0 1

1 0

1 1
2 address pins

0 0

0 1

1 0

1 1
3 address pins

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1
3 address pins

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1
3 address pins

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1
True
True
False
True
 DRAM

Pin 4:
RAS (Row Access Strobe)
Pin 15:
CAS (Column Access Strobe)
a. organization: 215 x 8 = 25 x210x8 = 32Kx8
capacity: 256K bits
b. organization: 213 x 8 = 23 x210x8 = 8Kx8
capacity: 64K bits
c. organization: 212 x 8 = 22 x210x8 = 4Kx8
capacity: 32K bits
a. 16K x 8 ROM
capacity: 128k bits
data pins: 8 ; D0 -> D7
address pins: 16K = 24 x210 = 214
or address pins: log2(16K) = 14
address pins: 14; A0 -> A13
b. 32K x 8 ROM
capacity: 256k bits
data pins: 8 ; D0 -> D7
address pins: 32K = 25 x210 = 215
or address pins: log2(32K) = 15
address pins: 15; A0 -> A14
C . 64K x 8 SRAM
capacity: 512k bits
data pins: 8 ; D0 -> D7
address pins: 64K = 26 x210 = 216
or address pins: log2(64K) = 16
address pins: 16; A0 -> A15
 CS
CS
CS

CS

CS
One Chip Multiple chips
1.

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

10011000000000000000=98000
10011111111111111111=9FFFF
 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

11000000000000000000=C0000
11000000111111111111=C0FFF
A11 to A0
A12 0
A13 0
A14 0
A15 0
A16 CS
0
A17
0
A18 1
A19 1
 Three inputs:
A, B & C,
generate
eight
active-low
outputs:
Y0–Y7.

Fig. 10-11 74LS138 Decoder

 Y3

1
1
0
1
1
1
1

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

11110110000000000000=F6000
11110111111111111111=F7FFF
 Y6

0
1
1
1
1
1
1

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

11111100000000000000=FC000
11111101111111111111=FDFFF
 C B A 4.
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

00000000000000000000=00000
00000011111111111111=03FFF
A14
A15
A16
A13 to A0
A17

A18

A19
 C B A 4.
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

00000000000000000000=00000
00000011111111111111=03FFF
A14
A15
A16
A13 to A0
A17

A18

A19
Size = 214 bytes = 16K
 Range of Y3

A14
A15
A16

A17

A18

A19

C B A
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

00001100000000000000=0C000
00001111111111111111=0FFFF
A B A or B
0 0 0
0 1 1
1 0 1
1 1 1
 6.
C B A
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

10000000000000000000=80000
10000000011111111111=807FF
A11
A12
A14
A13
A15
A10 to A0
A16
A17 A18

A19
 Range of Y5

A11
A12
A14
A13
A15
A16
A17 A18

A19
A10 to A0

C B A
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

10000010100000000000=82800
10000010111111111111=82FFF