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UNIT- 7 (Notes) 7.1 FEATURE OF 8096/80196 MICROCONTROLLER

Faculty : S V Altaf

16 BIT microcontroller. It performs 16 bit processing Princeton Architecture Continuous address space for SFRs, Registers, Internal RAM & ROM and external memory Register based arithmetic and logic operations 16 BIT stack pointer BIU & MUX unit 4 byte instruction queue 5 ports P0,P1,P2,P3 & P4 Timers, serial ports, ADC & PWM Interrupt control circuit and watch dog timer 16 KB ROM/EPROM starting from address 2000H Timers are 16 bit with the facility of input capture and out compare The ports are multiplexed
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P0 is multiplexed with analog inputs P1 is multiplexed with PWM & PTS signals P2 is multiplexed with serial port and timer signals

P3 & P4 have alternate functions in expanded mode of operation P3 has AD00-AD07 P4 has AD00-AD15 1ST 24 bytes of memory is for SFRs. There are 4 horizontal windows. Each window is of 24 bytes each and address of 24 bytes will be the same for all 4 windows. So we can say window 0,window1, window2, window3.

Page 0 addresses is from 00 to FFH First 512 bytes between 0000 to 01FFH are divided into vertical windows These windows are 16 of 32 bytes each, 8 of 64 bytes each or 4 of 128 bytes each

7.2 OPERATIONAL FEATURES It does 16 bits operations on 1 instruction cycle It does not have separate data and code memory Data memory Code memory contains variable contains code

Both operands can be registers PWM can be used as DAC Facility which will continuously check whether CPU is properly working or not (Watch dog timer) PTS Peripheral Transaction Server

7.3 MEMORY MAP OF 80196 KC

Faculty : S V Altaf

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7.4 SFRs of 80196KC

Special function Registers are available from address 0000H-0017H i.e. 24 addresses. Out of these 24 addresses,9 addresses are common to horizontal window 0 (read), horizontal window 0 (write), horizontal window 1(Read ) and horizontal window 15. Registers common to all windows are given below. ADD (Hex) 0000-0001H 0008H 0009H 0012H 0013H 0014H SFR R0 Int_mask INT_pending INT_pend1 INT_mask1 WSR

Registers of Horizontal window 0 (read) and window 0 (write) ADD (Hex) 0002 0002 SFR AD_command(write) AD_Result_L0 (read)
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0003 0003 0004-0005 0004-0005 0006 0006 0007 000A 000B 000A-000B 000C-000D 000E 000E 000F 0010 0011 0011 0015 0015 0016 0016 0017 Horizontal window 1 (read/write) ADD (Hex) 0003 0004 0005 0006 0007 000C 0016 0017 SFR

HSI_mode (write) AD_result_high(read) HS0_Time (Write) HS0_Time (read) HS0_Command (write) HS0_status (read) SBUF Watchdog (Write) I0C2(Write) Timer 1 (Read) Timer 2 (read) Baud rate (write) P0 (read) P1 (read/write) P2 (read/write) SP_Control (write) SP_stat (read) 10C0(write) 10S0(read) 10C1 (write) 10S1 (read) 10S2 (Read/write)

AD_Time PTSSEL_L0 PTSSEL_H0 PTSSRV_L0 PTSSRV_H0 10C3 PWM2 control PWM1 control

Unused addresses are reserved for future expansion. Common addresses are same as earlier
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SFRs at horizontal window 15 ADD (Hex) 000C 0016 SFR T2 Capture_L0 T2 Capture_L0

7.5 PORTS OF 80196

It has got 5 ports P0,P1,P2,P3,P4. P0, P1and P2 are SFRs and P3 & P4 are outside SFR area. All the ports have got different functions in single chip mode or extended mode of operation. PORT P0 This is a general purpose port which is read only in single chip mode. In expanded mode of operation ,it is used to accept analog inputs at P0.0 to P0.7, P0.7 is also used as external interrupt under the control of register. PORT P1 This port is a general purpose quasi bidirectional port in single chip mode operation. In extended mode P1.5-P1.7 are used by PTS controlling the DMA operation. P1.3 & P1.4 are used for PWM1 and PWM2 in extended mode operation. PORT P2 P2 is a general purpose bidirectional port. In extended mode operation P2.5 is used for PWM0. P2.3 & P2.4 are used as inputs, T2 clock & T2 reset of timer 2. P2.2 is used for external interrupts. P2.0 & P2.1 are used as data and clock for synchronous serial communication. For asynchronous communication they are used as T*D and R*D. PORT P3 It is outside SFR. Its address is 1FFEH. It is a quasi bi directional port. During extended operation it carries AD00-AD07 bits. PORT P4 This is also outside SFR its address is 1FFFH. It is similar to P3 in single chip mode but in expanded mode of operation it carries signals AD8-AD15.

7.6 WINDOW SELECTION REGISTER (WSR)

WSR is one of the important SFR which is used to select horizontal windows and vertical windows.

Faculty : S V Altaf

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Faculty : S V Altaf

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The 4 LSBs of WSR are used to select the horizontal window. The four bit value will indicate window number. 3 bits of WSR i.e. BIT4,5 & 6 will decide the vertical window configuration. If BIT4 is set it will select 4 vertical windows, if bit5 is set it will select 8 vertical windows and if bit6 is set it will select 16 vertical windows.

Once a vertical window is selected the memory location within a window will be selected by the instruction directly

7.7 TIMERS, HSIs & HSOs

T1 is a 16 bit free running timer Input to the timer comes from internal clock
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It always runs and cannot be reset It is used to generate accurate time delays and to arrive at time of the day It is used mainly for HSIs o 4HSIs o o o o FIFO is used to store time of capture 8 entries of FIFO Each entry is 20 bits 16 bits are for time and 4 bits are for the type of HIS

It is rarely used for HSO operation The input capture is a high speed signal Its input signal is connected to micro controller It can capture very fast events also 4 different events can be captured simultaneously T2 is a 16 bit internal or external counter o Used mainly for HSOs o o o o o 6 HSOs Compares entries in CAM Each entry is 23 bits 16 bits for comparison data 7 bits for command

T2 has nothing to do with real time operation The CAM memory means content addressable memory. Memory location is not addressed by CPU address Width of the memory location is user defined Memory location is read when a part of memory location data is equal to input data Status and control registers are used to control and read information of timer 1 and timer 2 There are 4 software timers o The overflows of software timers are indicated by ISO1.0 ISO1.3 o Hardware counters are not used and instead memory locations are used

7.8 INTERRUPTS

Faculty : S V Altaf

18 groups of interrupts 3 NMI groups 15 general interrupt groups Priority scheme is implemented
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Masking facility is provided. 2 levels of masking is available. The higher level is by bit 9 of PSW and secondary level is by individual bits of INT mask and INT mask1 registers. Each interrupt has a specific vector. The vector area is from 2000H 2014H & 2030H-203FH Priority of interrupt is fixed as INT0 being higher priority and INT17 being lowest priority Each interrupt is indicated by a flag. For example FIFO full flag Details of each interrupt group o Group 0 External HW o o o o o o o o o o o o o o o o Group 1 Group 2 Group 3 Group 4 Group 5 Group 6 Group 7 Group 8 Group 9 Group 11 Group 12 Group 13 Group 14 Group 16 Group 17 HSI External HW Timer 2 overflow Timer 2, T2 capture HSI,FIFO HALF FULL Serial Port, RI flag Serial Port, TI flag Illegal code Instruction trap Serial Port, TI or RI HSO HSI HSO.0-HSO.5 ADC T1 or T2 overflow

Group 10 External HW

7.9 ADDRESSING MODES

Implicit address mode o PUSHF o SETC Immediate addressing mode o LD AX,#55AH o ADD AX,NUM,#1234H Direct addressing mode o LD AL,P0 o ADD BX,NUM1,NUM2 Indirect addressing mode o Without port increment
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LD AX,[SI] o o o Width post increment LD AX,[SI]+ Index Long LD AX,[SI+offset] Index short LD AX,DISP[SI]

7.10 INSTRUCTIONS OF 80196

Maximum number of operands can be upto 3 The memory locations are treated as registers Each memory location used should be given a name These names to be used in the instructions Data transfer instructions o LD o o o ST PUSH POP

Arithmetic Instructions o ADD o o o o o o o ADC SUB SUBB MULTIPLY MULTIPLY SIGN NUMBERS DIVIDE DIVIDE SIGN NUMBERS

DATA Manipulation instructions o CLR o o EXT NOT

BIT Manipulation instructions o SETC o CLRC

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EIDI

Logical instructions o AND o o OR XOR

Program control flow instructions o CALL SCALL LCALL o JMP SJMP LJMP o Conditional jump based on flags

Miscellaneous instructions o RST o TRAP

Faculty : S V Altaf

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