COMPUTER ORGANIZATION AND ARCHITECTURE BEC306C

MODULE 1: BASIC STRUCTURE OF COMPUTERS

1.1 Introduction

BASIC CONCEPTS
• Computer Architecture (CA) is concerned with the structure and behaviour of
thecomputer.
• CA includes the information formats, the instruction set and techniques for
addressingmemory.
• In general covers, CA covers 3 aspects of computer-design namely: 1) Computer
Hardware, 2) Instruction set Architecture and 3) ComputerOrganization.
1. ComputerHardware
 It consists of electronic circuits, displays, magnetic and optical storage media
and communicationfacilities.
2. Instruction SetArchitecture
 It is programmer visible machine interface such as instruction set, registers,
memory organization and exceptionhandling.
 Two main approaches are 1) CISC and 2)RISC.
(CISCComplex Instruction Set Computer, RISCReduced
Instruction Set Computer)
3. ComputerOrganization
 It includes the high level aspects of a design, suchas
→ memory-system
→ bus-structure &
→ design of the internal CPU.
 It refers to the operational units and their interconnections that realize the
architectural specifications.
 It describes the function of and design of the various units of digital computer
that store and processinformation.

1.3 BasicOperationalConcepts

FUNCTIONAL UNITS
• A computer consists of 5 functionally independent mainparts:
1) Input
2) Memory
3) ALU
4) Output&
5) Controlunits.

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1.4 BASIC OPERATIONAL CONCEPTS

• An Instruction consists of 2 parts, 1) Operation code (Op code) and 2)Operands.
OPCODE OPERANDS
• The data/operands are stored in memory.
• The individual instruction is brought from the memory to theprocessor.
• Then, the processor performs the specifiedoperation.
• Let us see a typical instruction
ADD LOCA, R0
• This instruction is an addition operation. The following are the steps to execute
theinstruction: Step 1: Fetch the instruction from main-memory into
theprocessor.
Step 2: Fetch the operand at location LOCA from main-memory into the
processor.
Step 3: Add the memory operand (i.e. fetched contents of LOCA) to the
contents of register R0. Step 4: Store the result (sum) in R0.
• The same instruction can be realized using 2 instructionsas:
Load LOCA,
R1 Add R1,
R0
• The following are the steps to execute theinstruction:
Step 1: Fetch the instruction from main-memory into the processor.
Step 2: Fetch the operand at location LOCA from main-memory into
the register R1. Step 3: Add the content of Register R1 and the
contents of register R0.
Step 4: Store the result (sum) in R0.

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MAIN PARTS OF PROCESSOR

• The processor contains ALU, control-circuitry and manyregisters.
• The processor contains ‘n’ general-purpose registers R0 throughRn-1.
• The IR holds the instruction that is currently beingexecuted.
• The control-unit generates the timing-signals that determine when a given action is
to takeplace.
• The PC contains the memory-address of the next-instruction to be fetched
&executed.
• During the execution of an instruction, the contents of PC are updated to point to
nextinstruction.
• The MAR holds the address of the memory-location to beaccessed.
• The MDR contains the data to be written into or read out of the addressedlocation.
• MAR and MDR facilitates the communication
withmemory. (IR Instruction-Register, PC
ProgramCounter)
(MAR Memory Address Register, MDRMemory Data Register)

STEPS TO EXECUTE AN INSTRUCTION

1) The address of first instruction (to be executed) gets loaded intoPC.
2) The contents of PC (i.e. address) are transferred to the MAR & control-unit issues
Read signal to memory.
3) After certain amount of elapsed time, the first instruction is read out of memory
and placed into MDR.
4) Next, the contents of MDR are transferred to IR. At this point, the instruction can
be decoded & executed.
5) To fetch an operand, its address is placed into MAR & control-unit issues Read
signal. As a result, the operand is transferred from memory into MDR, and then it is
transferred from MDR toALU.
6) Likewise required number of operands is fetched into processor.
7) Finally, ALU performs the desired operation.
8) If the result of this operation is to be stored in the memory, then the result is sent to
theMDR.
9) The address of the location where the result is to be stored is sent to the MAR and
a Write cycle is initiated.
10) At some point during execution, contents of PC are incremented to point to next
instruction in the program.

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1.5 BUS STRUCTURE

• A bus is a group of lines that serves as a connecting path for severaldevices.
• A bus may be lines orwires.
• The lines carry data or address or controlsignal.
• There are 2 types of Bus structures: 1) Single Bus Structure and 2) Multiple
BusStructure.
1) Single BusStructure
 Because the bus can be used for only one transfer at a time, only 2 units can
actively use the bus at any giventime.
 Bus control lines are used to arbitrate multiple requests for use of thebus.
 Advantages:
1. Low cost&
2. Flexibility for attaching peripheraldevices.
2) Multiple BusStructure
 Systems that contain multiple buses achieve more concurrency inoperations.
 Two or more transfers can be carried out at the sametime.
 Advantage: Betterperformance.
 Disadvantage: Increasedcost.

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• The devices connected to a bus vary widely in their speed ofoperation.

• To synchronize their operational-speed, buffer-registers can be used.
• BufferRegisters
→ are included with the devices to hold the information during transfers.
→ prevent a high-speed processor from being locked to a slow I/O device
during data transfers.

PERFORMANCE
• The most important measure of performance of a computer is how quickly it can
executeprograms.
• The speed of a computer is affected by the designof
1) Instruction-set.
2) Hardware & the technology in which the hardware isimplemented.
3) Software including the operatingsystem.
• Because programs are usually written in a HLL, performance is also affected by the
compiler that translates programs into machine language. (HLLHigh
LevelLanguage).
• For best performance, it is necessary to design the compiler, machine instruction set
and hardware in a co-ordinatedway.

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• Let us examine the flow of program instructions and data between the memory &
theprocessor.
• At the start of execution, all program instructions are stored in themain-memory.
• As execution proceeds, instructions are fetched into the processor, and a copy is
placed in thecache.
• Later, if the same instruction is needed a second time, it is read directly from
thecache.
• A program will be executedfaster
if movement of instruction/data between the main-memory and the
processor is minimized which is achieved by using the cache.

PROCESSOR CLOCK
• Processor circuits are controlled by a timing signal called aClock.
• The clock defines regular time intervals called ClockCycles.
• To execute a machine instruction, the processor divides the action to be performed
into a sequence of basic steps such that each step can be completed in one
clockcycle.
• Let P = Length of one clock
cycle R = Clockrate.
• Relation between P and R is givenby

• R is measured in cycles persecond.

• Cycles per second is also called Hertz(Hz)

BASIC PERFORMANCE EQUATION

• Let T = Processor time required to
executedaprogram.N = Actual number of
instructionexecutions.
S = Average number of basic steps needed to execute one
machine instruction. R = Clock rate in cycles per second.
• The program execution time is givenby

------(1)
• Equ1 is referred to as the basic performanceequation.
• To achieve high performance, the computer designer must reduce the value of T,
which means reducing N and S, and increasingR.
 The value of N is reduced if source program is compiled into fewer
machineinstructions.
 The value of S is reduced if instructions have a smaller number of basic steps

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toperform.
 The value of R can be increased by using a higher frequencyclock.
• Care has to be taken while modifying values since changes in one parameter may
affect theother.

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MODULE 1 (CONT.): MACHINE INSTRUCTIONS &

PROGRAMS

1.8 MEMORY-LOCATIONS & ADDRESSES

• The memory consists of many millions of storage cells(flip-flops).
• Each cell can store a bit of information i.e. 0 or 1 (Figure2.1).
• Each group of n bits is referred to as a word of information, and n is called the
wordlength.
• The word length can vary from 8 to 64bits.
• A unit of 8 bits is called abyte.
• Accessing the memory to store or retrieve a single item of information (word/byte)
requires distinct addresses for each item location. (It is customary to use numbers
from 0 through 2k-1 as the addresses of successive-locations in thememory).
• If 2k = no. of addressablelocations
then 2k addresses constitute the address-space of the computer.
For example, a 24-bit address generates an address-space of 224
locations (16 MB).

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BYTE-ADDRESSABILITY
• In byte-addressable memory, successive addresses refer to successive byte locations
in thememory.
• Byte locations have addresses 0, 1, 2. . . ..
• If the word-length is 32 bits, successive words are located at addresses 0, 4, 8. .
with each word having 4bytes.

BIG-ENDIAN & LITTLE-ENDIAN ASSIGNMENTS

• There are two ways in which byte-addresses are arranged (Figure2.3).
1) Big-Endian: Lower byte-addresses are used for the more significant bytes of
theword.
2) Little-Endian: Lower byte-addresses are used for the less significant bytes of
theword
• In both cases, byte-addresses 0, 4, 8. . . . . are taken as the addresses of
successive words in the memory.

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• Consider a 32-bit integer (in hex): 0x12345678 which consists of 4 bytes: 12, 34, 56,
and78.
 Hence this integer will occupy 4 bytes inmemory.
 Assume, we store it at memory address starting1000.
 On little-endian, memory will looklike
Addres Value
1000
s 78
1001 56
1002 34
1003 12

 On big-endian, memory will looklike

Addres Value
s
1000 12
1001 34
1002 56
1003 78

WORD ALIGNMENT
• Words are said to be Alignedin memory if they begin at a byte-address that is a
multiple of the number of bytes in aword.
• Forexample,
 If the word length is 16(2 bytes), aligned words begin at byte-addresses 0, 2, 4
. . . ..
 If the word length is 64(2 bytes), aligned words begin at byte-addresses 0, 8,
16 . . . ..
• Words are said to have Unaligned Addresses, if they begin at an arbitrarybyte-
address.

ACCESSING NUMBERS, CHARACTERS & CHARACTERS STRINGS

• A number usually occupies one word. It can be accessed in the memory by
specifying its word address. Similarly, individual characters can be accessed by
theirbyte-address.
• There are two ways to indicate the length of thestring:
1) A special control character with the meaning "end of string" can be used as
the last character in thestring.
2) A separate memory word location or register can contain a number indicating
the length of the string inbyte.

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1.9 MEMORY OPERATIONS

• Two memory operationsare:
1) Load (Read/Fetch)&
2) Store(Write).
• The Load operation transfers a copy of the contents of a specific memory-location
to the processor. The memory contents remainunchanged.
• Steps for Loadoperation:
1) Processor sends the address of the desired location to thememory.
2) Processor issues ‘read’ signal to memory to fetch thedata.
3) Memory reads the data stored at thataddress.
4) Memory sends the read data to theprocessor.
• The Store operation transfers the information from the register to the specified
memory-location. This will destroy the original contents of thatmemory-
location.
• Steps for Store operationare:
1) Processor sends the address of the memory-location where it wants to
storedata.
2) Processor issues ‘write’ signal to memory to store thedata.
3) Content of register(MDR) is written into the specifiedmemory-location.

INSTRUCTIONS & INSTRUCTION SEQUENCING

• A computer must have instructions capable of performing 4 types ofoperations:
1) Data transfers between the memory and the registers (MOV, PUSH,
POP,XCHG).
2) Arithmetic and logic operations on data (ADD, SUB, MUL, DIV, AND, OR,NOT).
3) Program sequencing and control (CALL.RET, LOOP,INT).
4) I/0 transfers (IN,OUT).

REGISTER TRANSFER NOTATION (RTN)

• The possible locations in which transfer of information occurs are: 1) Memory-
location 2) Processor register & 3) Registers in I/Odevice.

Location Hardware Binary Address Example Description

Memory LOC, PLACE, NUM R1 [LOC] Contents of memory-location
LOC are transferred into
register R1.
Processor R0, R1 ,R2 [R3] [R1]+[R2] Add the contents of register
R1 &R2 and places their sum
into R3.
I/O Registers DATAIN, DATAOUT R1 DATAIN Contents of I/O register
DATAIN are transferred into
register R1.
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ASSEMBLY LANGUAGE NOTATION

• To represent machine instructions and programs, assembly language format isused.

Assembly Language Description

Format
Move LOC, R1 Transfer data from memory-location LOC to register R1.
The contents of LOC are unchanged by the execution of this
instruction, but the old contents of register R1 are
overwritten.

Add R1, R2, R3 Add the contents of registers R1 and R2, and places their
sum into register R3.

BASIC INSTRUCTION TYPES

Instructio Syntax Example Description Instruction
n Type s for
Operation
C<-
[A]+[B]
Three Opcode Source1,Source2,Destination Add A,B,C Add the contents of
Addres memory-locations A & B.
s Then, place the result
into locationC.

Two Address Opcode Source, Destination Add A,B Add the contents of Move B,
memory-locations A & B. C Add A,
Then, place the result C
into location B, replacing
the original
contents of this
location.
Operand B is both a
source and a destination.

One Address Opcode Source/Destination Load A Copy contents of Load A

memory- location A into Add B
accumulator. Store
Add B Add contents of memory- C
location B to contents of
accumulator register &
place sum back into
accumulator.

Store C Copy the contents of the

accumulator into location
C.

Zero Opcode [no Source/Destination] Push Locations of all operands Not possible
Addres are definedimplicitly.
s The operands are stored
in a pushdownstack.

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• Access to data in the registers is much faster than to data stored inmemory-locations.
• Let Ri represent a general-purpose register.Theinstructions:
LoadA,Ri
Store Ri,A
AddA,Ri
are generalizations of the Load, Store and Add Instructions for the single-accumulator
case, in which register Ri performs the function of the accumulator.
• In processors, where arithmetic operations as allowed only on operands that are in
registers, the task C<-[A]+[B] can be performed by the instructionsequence:
Move A,Ri
Move B,Rj
Add Ri,Rj
Move Rj,C

1.10 INSTRUCTION EXECUTION & STRAIGHT LINE SEQUENCING

• The program is executed asfollows:
1) Initially, the address of the first instruction is loaded into PC (Figure2.8).
2) Then, the processor control circuits use the information in the PC to fetch
and execute instructions, one at a time, in the order of increasing addresses.
This is called Straight-Line sequencing.
3) During the execution of each instruction, PC is incremented by 4 to point to
nextinstruction.
• There are 2 phases for InstructionExecution:
1) Fetch Phase: The instruction is fetched from the memory-location and placed
in theIR.
2) Execute Phase: The contents of IR is examined to determine which
operation is to be performed. The specified-operation is then performed by
theprocessor.

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Program Explanation
• Consider the program for adding a list of n numbers (Figure2.9).
• The Address of the memory-locations containing the n numbers are symbolically
given as NUM1, NUM2…..NUMn.
• Separate Add instruction is used to add each number to the contents of registerR0.
• After all the numbers have been added, the result is placed in memory-locationSUM.
BRANCHING
• Consider the task of adding a list of ‘n’ numbers (Figure2.10).
• Number of entries in the list ‘n’ is stored in memory-locationN.
• Register R1 is used as a counter to determine the number of times the loop
isexecuted.
• Content-location N is loaded into register R1 at the beginning of theprogram.
The Loop is a straight line sequence of instructions executed as many times asneeded.
The loop starts at location LOOP and ends at the instructionBranch>0.
• During eachpass,
→ address of the next list entry is determined and
→ that entry is fetched and added to R0.
• The instruction Decrement R1 reduces the contents of R1 by 1 each time through
theloop.
• Then Branch Instruction loads a new value into the program counter. As a result,

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the processor fetches and executes the instruction at this new address called the
BranchTarget.
• A Conditional Branch Instruction causes a branch only if a specified condition is
satisfied. If the condition is not satisfied, the PC is incremented in the normal way,
and the next instruction in sequential address order is fetched andexecuted.

CONDITION CODES
• The processor keeps track of information about the results of various operations.
This is accomplished by recording the required information in individual bits, called
condition codeflags.
• These flags are grouped together in a special processor-register called the condition
code register (or statueregister).
• Four commonly used flagsare:
1) N (negative) set to 1 if the result is negative, otherwise cleared to0.
2) Z (zero) set to 1 if the result is 0; otherwise, cleared to0.
3) V (overflow) set to 1 if arithmetic overflow occurs; otherwise, cleared to0.
4) C (carry) set to 1 if a carry-out results from the operation; otherwise cleared to 0

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