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Paper / Subject Code: 32223 / Digital VLSI

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1T01035 - T.E.(Electronics and Telecommunication )(SEM-V)(Choice Base Credit Grading System ) (R-

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19) (C Scheme) / 32223 - Digital VLSI QP CODE: 10040575 DATE : 29/11/2023

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Time: 3hrs [Total Marks:80]

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N.B. : (1) Question No 1 is Compulsory.

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(2) Attempt any three questions out of the remaining five.

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(3) All questions carry equal marks.

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(4) Assume suitable data, if required and state it clearly.

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1 Attempt any FOUR [20]

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a State Working of TG logic with proper diagram

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b Explain Flash memory in brief.

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c For n-channel MOSFET VT = 1.75 V, VGS=5V, VDS = 2V, ID = 120A,

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COX=51.72 nF/CM2, µn =400 CM2/S. Find the region of operation and W/L

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ratio.

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d Explain MOSFET electrical characteristics.
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e Write short note on clock distribution.
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2 a Explain P-MOS fabrication with neat and clean diagram. [10]

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b Consider a CMOS inverter with following parameters: [10]

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nMOS VTN = 0.6 V Kn = 200 µA/V2

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pMOS VTp = -0.7 V Kp = 80 µA/V2 Kr = 2.5

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Calculate noise margin. The power supply voltage is VDD = 3.3 V.

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3 a Design SR Latch using CMOS logic and draw its layout [10]
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b i) Explain short channel effects in VLSI 2 2 [10]

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ii) Implement carry circuit of 4 bit carry lookahead adder.
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4 a Realize the expression for AND gate using the following logic style. [10]
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1. Clocked CMOS logic

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2. Pseudo NMOS
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3. Dynamic PMOS
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4. Domino Logic
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b Draw and explain 6-T SRAM with neat and clean diagram. Explain read and [10]
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write condition with equations.

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5 a Implement using CMOS logic 1) 1-Bit full adder 2) DFF using TG. [10]
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b State and explain different types of ROM memory. Draw 4 *4 bit NAND based [10]
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array to store the following data in respective memory locations.

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Memory address Data

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1000 1101
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0100 1001
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0010 1010
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0001 1001
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6 a Illustrate RTL design of 3 TAP Serial FIR filter with HLSM,FSM and datapath. [10]
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Calculate hardware required for 100 TAP filter.

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b Draw and explain VTC characteristics of CMOS inverter in detail. [10]

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40575 Page 1 of 1
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