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syllabus

Uploaded by

poojithapooja256
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© © All Rights Reserved
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Course Name

Semiconductor Processing

Course Number
ECE418/518

Credits
4

Instructor
Sieun Chae
Assistant Professor, Electrical Engineering & Computer Science
Email: [email protected]
Office Location: 3093 Kelley Engineering Center

Teaching Assistants
There are two TA’s helping out with this class:

Name Email Address


Lakshmi Prakasan [email protected]
Fatimah Abdulqader [email protected]

Class Meeting Times


Lecture: Tuesday & Thursday 9:00 – 9:50 am, Waldo Hall 132
Laboratory: Group 1 – Monday & Friday 2:00 – 3:50 pm, Owen Hall 433
Group 2 – Monday & Friday 4:00 – 5:50 pm, Owen Hall 433
Office hours: Tuesday 10:00 am – 11:00 am in Kelley Atrium
Thursday 3:00 pm – 4:00 pm in Kelley 3130-27

Prerequisite and/or Corequisite


Prerequisite: ECE 416

Catalog Course Description


Theory and practice of basic semiconductor processing techniques. Introduction to process
simulation.

Course Specific Measurable Student Learning Outcomes


At the completion of the course, students will be able to…
1. Design and perform dry and wet oxidation of silicon wafers in the laboratory,
calculate the expected thickness of the oxide from the process conditions, and
measure the resulting oxide thickness comparing with predicted values.
2. Fabricate Al gate MOS capacitors on silicon wafers in the laboratory and perform
capacitance-voltage (C-V) measurements
3. Determine the substrate type and calculate the doping concentration in the
substrate, flat band voltage, threshold voltage and the oxide charge from the
measured C-V curves.
4. Design and perform a dopant diffusion process in the laboratory and calculate the
junction depth and sheet resistance of the diffused layer from the process conditions.
5. Fabricate a simple MOS transistor (gate length ~ 10mm) using a four-stage
photolithography process and measure the current vs voltage (I-V) characteristics
Determine the threshold voltage and the transconductance from the measured I-V
curves.
6. Simulate the MOS capacitor and MOS transistor using Athena and compare with
measured results after fabrication.
7. Prepare two reports on projects involving fabrications and characterizations of MOS
capacitors and transistors.

Textbook
 Introduction to Microelectronic Fabrication: Volume V, Second Edition: Richard C
Jaeger (2002), Prentice Hall.

Course Schedule

Lecture Schedule
 The below schedule is provisional and subject to change.

Week Date Topic Assessment


1 Jan 7 Introduction and Course Overview (Zoom)
Jan 9 Safety, Cleanroom, Cleaning (Zoom)
2 Jan 14 Basic Properties of Silicon
Jan 16 Silicon Growth
3 Jan 21 MOS Capacitors I
Jan 23 MOS Capacitors II
4 Jan 28 Vacuum Science and Technology HW1 Due (Jan 28)
Jan 30 Photolithography
5 Midterm week (Date: TBD) Midterm Exam
6 Feb 11 Etching Lab Report 1 Due (Feb
Feb 13 Diffusion 13)
7 Feb 18 Field Effect Transistors I
Feb 20 Field Effect Transistors II
8 Feb 25 Athena Modeling I HW2 Due (Feb 27)
Feb 27 Athena Modeling II
9 Mar 4 Oxidation
Mar 7 Thin-Film Growth
10 Final Exam (Date: TBD) Final Exam
11 Lab Report 2 Due (Mar
18)

Laboratory Schedule
 The below schedule is provisional and subject to change.
 Extra lab sessions will run to accommodate procedures taking longer than expected.
 Lab sessions are mandatory and attendance will be taken. Email Sieun and your
respective TA if you anticipate missing a session.
 For every unexplained absence, you will be deducted 10% for the relevant report.

Week Sessio Process Flow Content


n
3 1 MOS Capacitor Wafer testing, Cleaning, Oxide Growth
3 2 MOS Capacitor Cleaning, Etching, Cleaning, Sputtering
4 3 MOS Capacitor Thermal Evaporation, Electrical Device Measurement
4 3b MOS Capacitor [Overrun of previous sessions]
5 - - Break for Midterm Examination
5 4 NMOS Clean, Oxide Growth
Transistor
6 5 NMOS Photolithography, Etching, Cleaning, Diffusion
Transistor
6 6 NMOS Photolithography, Etching, Cleaning, Oxide Growth
Transistor
7 7 NMOS Photolithography, Etching, Cleaning, Thermal
Transistor Evaporation
7 8 NMOS Photolithography, Etching, Cleaning
Transistor
8 9 NMOS Electrical Device Measurement, Parameter
Transistor Evaluation
8 9b NMOS [Overrun of previous sessions]
Transistor
9 9c NMOS [Overrun of previous sessions]
Transistor

Evaluation of Student Performance


 Homework - 20 points
 Midterm Exam – 15 points
 Final Exam – 15 points
 Lab Report 1 – 15 points
 Lab Report 2 – 35 points
 Total – 100 points

Grading Scale

Lower Bound (%) Upper Bound (%) Grade


93 100 A
90 92 A-
87 89 B+
83 86 B
80 82 B-
77 79 C+
73 76 C
70 72 C-
67 69 D+
63 66 D
 Percentages will be rounded-off to the nearest whole percent to determine letter
grade.

Homework
 There will be a total of 2 homeworks.
 The homeworks overall contribute 20% of the course grade.
o 10% each.
 The homeworks are designed to test your understanding of the concepts covered in
the lectures.
o Sometimes you will be expected to apply knowledge obtained in the lectures
to new (previously unseen) situations.
 You will be assessed via a mixture of:
o Text-based answers.
o Analytical problems (pen, paper & calculator).
 They will be due 1 week after they are set.
 Please submit homework on canvas
 Late homework will be deducted 10% per day late for a maximum of 5 days, after
which the homework grade will be zero.
 The solutions will be posted online when the homeworks are returned.

Examinations
 There will be two examinations.
 They will carry equal weight to the final course grade: 15% each.
 The exams are designed to test your ability to apply knowledge acquired during the
exams to new (previously unseen) situations.
 You will be allowed (and expected) to use a calculator.
 Both exams will be closed book and closed notes.
 Besides a small number of well-known equations, most equations will be provided at
the start of the exam.
 All physical constants and parameters will be provided.
 The exams will last 90 minutes.
o Please ensure you arrive on time.

Laboratory Sessions
 During weeks 3 – 8 you will attend 2 laboratory sessions per week.
 Lab sessions are mandatory and attendance will be taken.
o Email Sieun and your respective TA if you anticipate missing a session.
o For every unexplained absence you will be deducted 10% for the relevant
report.
 All laboratory sessions will be held in the cleanroom in Owen Hall: Owen Hall 433.
 Lab sessions are scheduled for 2 hours, but frequently overrun to 2 ½ to 3 hours.
 Lab group sizes will be 4 – 6 students.
 You will be assigned one TA per group.
 Details on requirements for entering the cleanroom, safety, etc. will be covered in
Lecture 2.

Laboratory Reports
 As part of this course you will be expected to write 2 laboratory reports based
on work you have carried out during laboratory sessions.
 Report 1 will be an individual report.
 Report 2 will be a group report.
 More details will be available during the course.

Report Due Topic


#
1 Thursday MOS capacitors
02/13/25
2 Tuesday NMOS transistors
03/18/25

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