USOO886O176B2

(12) United States Patent (10) Patent No.: US 8,860,176 B2

Fritz et al. (45) Date of Patent: Oct. 14, 2014

(54) MULTI-DOPED SILICON ANTIFUSE DEVICE 5,042,386 A 8, 1991 Kruse et al.

FOR INTEGRATED CIRCUIT 5,159,629 A 10, 1992 Double et al.
5,486,707 A 1/1996 Look et al.
(71) Applicant: International Business Machines g A 13 2. SNR, al al.
Corporation, Armonk, NY (US) 5,776,235 A 7/1998 Camilletti et al.
5,821,558 A 10, 1998 Han et al.
(72) Inventors: Gregory M. Fritz, Yorktown Heights, 5,970,372 A 10/1999 Hartet al.
6,087,677 A 7, 2000 Wu et al.
NY (US); Bahman T.502.256 B2 3, 2009 M Jr. etal
Hekmatshoartabari, White Plains, NY 7880248 B1 2, 2011 R.A.
(US); Ali Khakifirooz, Mountain View, 7898.855 B2 3, 2011 Merry, Jr. et al.
CA (US); Dirk Pfeiffer, Croton on (Continued)
Hudson, NY (US); Kenneth P. Rodbell, O1
Sandy Hook, CT (US); Davood
Shahrijerdi. White Plains, NY (US) OTHER PUBLICATIONS
(73) Assignee: Corporation,
International Armonk,
BusinessNY
Machines
(US)
N
p ous I Icon
its U.S.at rogramma
A. R. R P.
e- ray- Ogic
m
WCS O
High Relilability Space Applications' consists of 4 pages.
(*) Notice: Subject to any disclaimer, the term of this (Continued)
patent is extended or adjusted under 35
U.S.C. 154(b) by 0 days.
1 Primary Examiner — Chuong A Luu
(21) Appl. No.: 13/654,040 Assistant Examiner — Rodolfo Fortich
(22) Filed: Oct. 17, 2012 (74) Attorney, Agent, or Firm — Louis J. Percello
(65) Prior Publication Data
(57) ABSTRACT
US 2014/O103485-A1 Apr. 17, 2014
The present disclosure relates to an antifuse for preventing a
(51) Int. Cl. flow of electrical current in an integrated circuit. One such
HOIL 23/525 (2006.01) antifuse includes a reactive material and a silicon region
(52) U.S. Cl. thermally coupled to the reactive material, where an electrical
CPC .................................. HOIL 23/5252 (2013.01) current to the reactive material causes the reactive material to
USPC ........... 257/530; 438/131; 438/132:438/281; release heat which transitions the silicon region from a high
438/467:438/600 resistance state to a low resistance state. Another such anti
(58) Field of Classification Search fuse includes a reactive material, at least one metal and a
USPC .. .. . .. . .. .. 257/.530, 50, 531, 183 silicon region adjacent to the at least one metal and thermally
See application file for complete search history. coupled to the reactive material, where an electrical current to
(56) References Cited the reactive material causes the reactive material to release
heat which transitions the silicon region from a high resis
U.S. PATENT DOCUMENTS tance state to a low resistance State.

3,666,967 A 5, 1972 Keister et al.

3,882,323 A 5, 1975 Smoker 18 Claims, 6 Drawing Sheets

WIREs (Cu)
DELECTRIC
r' sis::
res of E:: SLION
DE 8.

1. 110 10
 US 8,860,176 B2
Page 2

(56) References Cited Heat and Velocity in Reactive Al/Ni Multilayers' Journal of Applied
Physics 105 (2009) pp. 083504-1-083504-9.
U.S. PATENT DOCUMENTS J. Braeuer, J. Besser, M. Wiemer, T. Gessner, “Room-Temperature
Reactive Bonding by Using Nano Scale Multilayer Systems' Trans
7,936,603 B2 5/2011 Merry, Jr. ducers' 11, Beijing, China, Jun. 5-9, 2011. pp. 1332-1335.
7, 2011
7,982.488 B2 Nirschl et al. C. Rossi, K. Zhang, D. Esteve, P. Alphonse, P. Tailhades, C. Vahlas,
2004.0034782 A1 2/2004 Park et al. “Nanoenergetic Materials for MEMS: A Review” Journal of
2006.0049256 A1 3, 2006 Von Mueller et al. Microelectromechanical Systems, vol. 16, No. 4. Aug. 2007. pp.
2006/01O2982 A1* 5/2006 Park et al. ..................... 257/528 919-931.
2008/0223932 A1 9, 2008 Von Mueller et al. D. Schellekens, P. Tuyls, B. Preneel, “Embedded Trusted Computing
2010, O255380 A1 10/2010 Baba et al. with Authenticated Non-Volatile Memory' Trust 2008, LNCS, pp.
2011, 0078.933 A1 4/2011 Lukawitz et al. 60-74.
2011/0226148 A1 9, 2011 Sawka et al. S.W. Smith, S. Weingart, “Building a High-Performance, Program
2013,0089943 A1 4/2013 Chen et al.
2013/0117138 A1 5, 2013 Hazel et al. mable Secure Coprocessor' Revised Feb. 17, 1998, consist of 10
pages and numbered pp. 1-51.
OTHER PUBLICATIONS G.E. Suh, S. Devadas, “Physical Unclonable Functions for Device
Authentication and Secret Key Generation” DAC 2007, consists of 6
Jae Sung Lee, Young Hyun Lee, "Metal-to-Metal Antifuse with pageS.
Amorphous Ti-Rich Barium Titanate Film and Silicon Oxide Film”. T. Matsumoto, S. Nakajima, T. Shibata, A. Yamagishi,"Studying LSI
Solid State, Electronics 43 (1999) pp. 469-472. Tamper Resistance with Respect to Techniques Developed for Fail
S.H. Fischer, M.G. Grubelich, “A Survey of Combustible Metals ure Analysis” Sep. 2005, consists of 13 pages.
Thermites, and Intermetallics for Pyrotechnic Applications' pp. S.P. Skorobogatov, R.J. Anderson, "Optical Fault Induction Attacks'
1-13. CHES 2002, LNCS 2523, pp. 2-12 2003.
S. Raoux, G.W. Burr, M.J. Breitwisch, C.T. Rettner, Y.C. Chen, R.M. O. Kömmerling, M.G.Kuhn, “Design Principles for Tamper-Resis
Shelby, M. Salinga, D. Krebs, S.H. Chen, H.L. Lung, C.H.Lam. “ tant Smartcard Processors' May 1999 USENIX Association, pp.
Phase-change Random Access Memory: A Scalable Technology” 1-12.
IBMJ Res. & Dev. vol. 52 No. 4/5 Jul/Sep. 2008. pp. 465-479. L. Teyssier, “Strong Encryption and Correct Design are not Enough:
A.J. Gavens, D. Van Heerden, A.B. Mann, M.E. Reiss, and T.P. Weihs Protecting Your Secure System from Side Channel Attacks' 2010, pp.
“Effect of Intermixing on Self-Propagating Exothermic Reactions in 1-18.
Al/NiNanolaminate Foils” Journal of Applied Physics, vol.87.No. 3, M. MeterelliyoZ, P. Song, F. Stellari, J. Kulkarni, K. Roy, “A High
Feb. 2000. pp. 1255-1263. Sensitivity Process Variation Sensor Utilizing Sub-Threshold Opera
Y.N. Picard, J.P. McDonald, T.A. Friedmann, S.M. Yalisove, D.P. tion” 2006, pp. 125-128.
Adams “Nanosecond Laser Induced Ignition Thresholds and Reac N. Papandreou, H. Pozidis, T. Mittelholzer, G.F. Close, M.
tion Velocities of Energetic Bimetallic Nanolaminates' Applied Breitwisch, C. Lam, E. Eleftheriou, "Drift-Tolerant Multilevel
Physics Letters 93 (2008) pp. 104104-1-104104-3. Phase-Change Memory’ 2011 consists of 4 unnumbered pages.
R. Knepper, M.R. Snyder, G. Fritz, K. Fisher, Omar M. Knio, T.P.
Weihs, “Effect of Varying Bilayer Spacing Distribution on Reaction * cited by examiner
U.S. Patent Oct. 14, 2014 Sheet 1 of 6 US 8,860,176 B2

1 OO

WIRES (Cu)

oneere
DEL

: s

REST OF THE :... . . .

110 110 110

FIG.
U.S. Patent Oct. 14, 2014 Sheet 2 of 6 US 8,860,176 B2

Top ElectroDE (e.g., tin)

210
PHASE CHANGE MATERIAL
(e.g., Ge2Sb Tes)
220
NSULATOR NSULATOR
230 230

- - BOTTOM
LOWERELECTRODE EECTRODE
(e.g., TiN) (e.g., TiN)
250 24O

PHASE CHANGE MEMORY 200 IN "SET" STATE

-1 AMORPHOUS
PO LY CRYSTALLINE m
NSULATOR NSULATOR
230 230
--

LOWER ELECTRODE - BOTTOM

250 ELECTRODE
o 240

PHASE CHANGE MEMORY 200 IN "RESET" STATE

FIG 2
U.S. Patent Oct. 14, 2014 Sheet 3 of 6 US 8,860,176 B2

OO

32O

310---

320

F.G. 3
U.S. Patent Oct. 14, 2014 Sheet 4 of 6 US 8,860,176 B2

47O 470

410
LOW
RESISTANCE RESISTANCE

DELECTRIC
460 460 460

4 OO 4. OO

FIG 4
U.S. Patent Oct. 14, 2014 Sheet 5 of 6 US 8,860,176 B2

500

510
PROVIDE SUBSTRATE/DE FOR AN INTEGRATED CIRCUET

FORMAT LEAST ONE PHOTOWOLAIC CELLIN THE 520

INTEGRATED CIRCUIT

DEPOSIT REACTIVE MATERIAL IN INTEGRATED CIRCUIT P?'

INCLUDE ARMING SWITCH BETWEEN AT LEAST ONE

PHOTOVOLAIC CEL AND REACTEVE MATERIAL AND/OR 540
AT LEAST ONE MEMORY CELL

FABRCATE AT LEAST ONE MEMORY CELLIN THE 550

INTEGRATED CIRCUIT

t
COUPLE THEAT LEAST ONE MEMORY CELL TO THE ONE 560
ORMORE PHOTOVOLTAC CELLS AND/OR REACTIVE
MATERA

OEACTIVATE ARMING SWCH 570

FIG. 5
U.S. Patent Oct. 14, 2014 Sheet 6 of 6 US 8,860,176 B2

OO

START / 6O2

y
1
FORM SILICON REGION IN THE INTEGRATED CIRCUIT s O

y
FORM DELECTRC LAYER o
y
DEPOST REACTWE MATERAL IN THE INTEGRATED
CIRCUIT, WHEREIN THE REACTIVE MATERIALIS
THERMALLY COUPLED TO THE SILICON REGION,
WHEREN ANELECTRICA CURRENT TO THE REACTIVE -630
MATERAL CAUSES THE REACTIVE MATERAL TO
RELEASE HEAT WHICH RANSiTIONS THE SICON
REGION FROM A HGH RESISTANCE STATE TO ALOW
RESISTANCE SATE

DEPOSIT AT LEAST ONE METAL IN THE INTEGRATED

CIRCUIT
635
y
INCLUDE AT LEAST ONE ELECTRICAL CONTACT FOR ré40
DEACTIVATNG ANTIFUSE

Y.
DEACTIVATE ANTEFUSE L-650

END 695

F.G. 6
 US 8,860,176 B2
1. 2
MULT-DOPED SILICON ANTIFUSE DEVICE FIG. 6 is a flowchart of a method for manufacturing an
FOR INTEGRATED CIRCUIT exemplary anti-fuse, e.g., an arming Switch, according to
embodiments of the present disclosure.
FIELD OF THE DISCLOSURE To facilitate understanding, identical reference numerals
have been used, where possible, to designate identical ele
The present disclosure relates to integrated circuits, and ments that are common to the Figures.
more particularly to antifuse devices for integrated circuits.
DETAILED DESCRIPTION
BACKGROUND OF THE DISCLOSURE
10
Embodiments of the present disclosure present a novel
Hardware based "Root of Trust' is a fundamental building on-chip anti tamper device for detecting physical tampering
block for any secure computing system. Key elements of as well as for providing a tamper response by erasure of data.
secure computing require authentication, sending data to an Exemplary components include miniaturized photovoltaic
authorized source, and/or loading data onto a designated cells (PV) integrated into the back end of the line (or backend)
device. In general, cryptographic keys in binary code form the 15
interconnect structure at various levels, non-volatile memory
basis of securing data and bit streams. Typically, Such cryp (NVM) (e.g., phase change memory (PCM)) to store sensitive
tographic keys are stored in non-volatile memory and are data, Such as secret authentication codes, and an embedded
present on an integrated circuit (IC) at all times. If an attacker reactive material (RM), which may comprise a multilayer
can extract the key from a device, the entire foundation for thin film metal stack that reacts when triggered by a current
secure computing is in jeopardy. For example, an attacker pulse generated from the photovoltaic (PV) elements. Nota
with physical access to a device can delayer the chip and read bly, many physical reverse engineering techniques require
out the stored code based on the state of the transistors. Thus,
securing cryptographic keys requires anti-tamper technolo accessing the chip structures through imaging (e.g., electron
gies. For example, an anti-tamper mesh may surround a beams from Scanning electron microscopy (SEM), focused
printed circuit board and may include a tamper sensor chip 25 ion beam (FIB), X-ray, etc.) and therefore generate radiation
and its own battery pack to deter Such attacks. If the sensor (e.g., photocurrent, laser beam induced current (LBIC), elec
detects that the mesh is being cut, the cryptographic code is tron beam induced current (EBIC), and the like). Embodi
erased. However, Such anti-tamper technologies may be rela ments of the present disclosure exploit this principle by using
tively expensive and may therefore not be suitable for imple the miniature photovoltaic PV cells to convert the radiation
30
mentation in mass produced, cost sensitive devices like field from a tampering attempt into a current which triggers the
programmable gate arrays (FPGAs), mobile devices, and sen tamper response (e.g., either directly or through an exother
SOS. mic reaction generated in the reactive material) to erase the
data.
SUMMARY OF THE DISCLOSURE Tampering/attacks range from electrical probing and
35
delayering for extracting secret keys to inducing faults (e.g.
Embodiments of the present disclosure describe an anti flipping states) in order to force an integrated circuit to con
fuse that includes a reactive material and a silicon region duct unauthorized operations. An attacker typically needs to
thermally coupled to the reactive material, where an electrical deploy a range of techniques in order to locate specific cir
current to the reactive material causes the reactive material to
release heat which transitions the silicon region from a high 40 cuits and structures which usually involve radiation for imag
resistance state to a low resistance state. ing or inducing currents and faults. Table 1 illustrates several
In another embodiment, an antifuse includes a reactive failure analysis/tampering techniques.
material, at least one metal and a silicon region adjacent to the
at least one metal and thermally coupled to the reactive mate TABLE 1
rial, where an electrical current to the reactive material causes 45
Failure Analysis technique Radiation involved
the reactive material to release heat which transitions the Delayering by ashing, polishing Requires optical microscope to stop
silicon region to change from a high resistance state to a low at a specific layer
resistance state. Single and dual beam focus ion Gaion beam for FIB cuts (produce
beam secondary electrons)
Scanning electron microscope (e-
BRIEF DESCRIPTION OF THE DRAWINGS 50 beam up to 30 KeV)
Electron beam induced current Scanning electron microscope (e-
The teachings of the present disclosure can be readily (EBIC), electron beam probing beam up to 30 KeV)
understood by considering the following detailed description Laser techniques: laser voltage Lasers wavelength up to 1.3
probing, optical beam induced microns
in conjunction with the accompanying drawings, in which: current (OBIC), thermal e.g.
FIG. 1 illustrates an exemplary device, according to 55 optical beam induced resistance
embodiments of the present disclosure; change (OBIRCH)
FIG. 2 illustrates an exemplary phase change memory cell X-Ray tomography X-Ray ranging from 50-200 keV
in “set and “reset' states, according to embodiments of the
present disclosure; Embodiments of the present disclosure are compatible
FIG. 3 illustrates an exemplary reactive material (e.g., a 60 with standard metal oxide semiconductor (MOS) chip fabri
thin metal stack), according to embodiments of the present cation techniques, thereby reducing the cost per die during
disclosure; implementation and integration of Such embodiments. Fur
FIG. 4 illustrates an exemplary anti-fuse, e.g., an arming thermore, the security against physical tampering is increased
Switch, according to embodiments of the present disclosure; compared to packaging based approaches due to miniaturiza
FIG. 5 is a flowchart of a method for manufacturing an 65 tion and containment within the chip. In addition, the on-chip
exemplary device, according to embodiments of the present anti-tamper devices of the present disclosure may also be
disclosure; and implemented with established hardware security products.
 US 8,860,176 B2
3 4
To aid in understanding the present disclosure, FIG. 1 example, silicon-on-insulator (SOI) based substrates can be
illustrates across-section of an exemplary device 100 (e.g., an used to fabricate photovoltaic cells by integrating a P N
integrated circuit) related to embodiments of the present dis junction into the silicon body as well as contacts on both sides
closure. In particular, device 100 includes a substrate or die of the silicon body.
160, which may be comprised of crystalline silicon (Si), Although the embodiment of FIG. 1 includes a reactive
germanium (Ge), SiGe, gallium arsenide (GaAs), or other material (RM) 180 as part of the tamper detection and
semiconductors, as well as other materials for forming tran response device, it should be noted that various embodiments
sistors, resistors, capacitors and other structures. Although are configured to directly erase one or more bits, i.e., without
the example of FIG. 1 refers to a die 160, the present disclo the use of a reactive material, via a direct electrical current
sure is not so limited. For example, the die may be one of 10 from the photovoltaic cell(s) 170 to the non-volatile memory
many dies that may be formed from a common Substrate or 120 and/or one or more of the gates 110. For example, in some
wafer. Thus, embodiments of the present disclosure may embodiments a current pulse between 200-500LA for several
incorporate a Substrate prior to separation of multiple dies. In nanoseconds is Sufficient to erase/reset each bit of a phase
any case, the die 160, which forms part of the front end of the change memory. Depending on the size of a particular pho
integrated circuit, may have a number of structures formed 15 tovoltaic cell 170 and/or the quantity and type of incident
thereon, Such as an array of one or more gates 110. In one radiation, the photovoltaic cell may generate currents in this
embodiment, the array of gates 110 may comprise a number range.
of transistors that form a non-volatile memory 120 (e.g., In embodiments that feature a reactive material 180, the
random-access memory (RAM), static random-access thin metal film of the reactive material 180 spontaneously
memory (SRAM), and the like). For example, each of the mixes in selective areas where current flows. Alternatively, or
gates 110 may comprise an n-type or p-type field effect tran in addition, the reactive material 180 provides a self-propa
sistor, or any number of other similar structures. Alterna gating exothermic reaction set off by a current pulse at a
tively, or in addition, the non-volatile memory 120 may com single site. In any case, both reaction mechanisms generate
prise a phase change memory (PCM). Exemplary phase sufficient heat, which causes the non-volatile memory 120 to
change memory devices are discussed in further detail below 25 change memory state, reset or to melt, leading to irreversible
in connection with FIG. 2. In one embodiment, the non erasure of any bits representing sensitive data, like crypto
volatile memory 120 stores sensitive data to be protected by graphic keys. For instance, in embodiments which employ a
the tamper detection and response device(s) of the present non-volatile memory comprising a phase change memory
disclosure. (PCM), the reaction heat sets or resets a PCM cell if the
The backend of device 100 is a multi-layer interconnect 30 reactive material is in close proximity to the PCM array. This
structure which includes wiring for transporting signals is due to the reaction heat affecting the PCM phase (amor
between transistors, gates and other structures in the frontend phous vs. crystalline). After erasure, there is no way to reverse
and Supply Voltages, ground, and C4S (solder bumps), in the engineer the bits, while the remaining portion of the inte
package. For example, the backend of a typical integrated grated circuit (device 100) remains intact. In some embodi
circuit may include insulating materials, e.g., dielectric 130, 35 ments, the heat generated by reactive material 180 is suffi
which may comprise a low-k dielectric material Such as boro ciently high to destroy all or part of non-volatile memory 120
phosphosilicate glass, and copper (Cu) or tungsten (Tu) wir (which, in some embodiments, may comprise a phase change
ing formed in vias 140 and traces 150. memory).
According to various embodiments of the present disclo In some embodiments, Scaling and Substrate effects, like
sure, device 100 also includes one or more photovoltaic (PV) 40 heat loss, may potentially lead to quenching of the reaction in
cells 170 which may be connected by way of wiring in the reactive material 180. Thus, in some embodiments the reac
traces 150 and vias 140 in the backend of the device 100 to the tive material 180 may be situated sufficiently close to the
non-volatile memory 120 and/or a reactive material (RM) non-volatile memory 120 to deliver sufficient heat to destroy
180. In particular, the photovoltaic cells 170 (or the photo or reset the non-volatile memory 120. Alternatively, or in
voltaic cells in combination with the reactive material 180) 45 addition, the reaction temperature of the reactive material is
comprise a tamper detection and response device for protect increased to deliver sufficient heat to destroy or reset the
ing the non-volatile memory 120. However, in another non-volatile memory 120 over a relatively greater distance
embodiment device 100 also includes one or more regions of within the device 160. Advantageously, the reactive material
reactive material 180 which may be connected by way of 180 stores energy on-chip that is benign during normal chip
wiring in the traces 150 and vias 140 in the backend of the 50 operations, but which can be triggered by a low current pulse.
device 100 to the non-volatile memory 120 and/or one or This is contrary to traditional tamper schemes with on-chip
more photovoltaic (PV) cells 170. In particular, the reactive batteries requiring a constant power, where the tamper detec
material 180 (or the reactive material in combination with the tion and response circuitry must be kept operational through
photovoltaic cells 170) comprises the tamper detection and out the lifetime of the die. Exemplary reactive materials and
response device. In one embodiment, the reactive material 55 thin-film metal stacks are discussed in further detail below in
(RM) 180 comprises a multilayer thin film metal stack that connection with FIG. 3.
causes an exothermic reaction when triggered by a current In one embodiment, a plurality of photovoltaic cells 170
pulse generated from one or more of the photovoltaic cells are placed at various locations and in various levels of the
170. It should be noted that although FIG. 1 illustrates pho interconnect structure of device 100. Notably, an attacker
tovoltaic cells 170 and reactive material 180 in the backend of 60 employing one or more reverse engineering techniques, such
device 100, the present disclosure is not limited to integration as focused ion beam (FIB) or X-ray tomography, may begin
in the back-end only. Namely, in other, further and different tampering/probing at various locations of the device 100. To
embodiments, one or more photovoltaic cells 170 and/or address the uncertainly as to the exact location where an
reactive material 180 may be located at the transistor level or attacker will begin, or where the attacker will proceed, bury
in the front-end at the silicon level (e.g., on, at, or near the 65 ing photovoltaic cells 170 at various locations and using
substrate, or die 160), which may be useful in preventing multiple photovoltaic cells increases the likelihood that a
intrusion and tampering attempts via the front-end. For probing attack is detected and that the non-volatile memory
 US 8,860,176 B2
5 6
120 is destroyed at an earlier instance. Similarly, by placing a junctions. The photocurrent for a LBIC is given by Ji-0.8
plurality of photovoltaic cells 170 at different levels in the mA/cm xQExilmWxk(laser), where #mW is the laser power
interconnect structure, the tamper response device is more in milliwatts, QE is the quantum efficiency and k is the wave
likely to detect/prevent an intrusion via delayering and other length in microns. Since lasers used by microanalysis tech
techniques at any given layer of the device 100. In addition, in niques range from 100 to 500 mW with wavelengths of 1-1.3
Some embodiments, for example in a large array, the microns, depending on the absorption coefficient and the
location(s) of one or more photovoltaic cells 170 can be band gap of the material of the photovoltaic cell 170, the
varied, randomly or otherwise, so that from one device to the photocurrents can be significant (e.g., Sufficient to meet or
next, the location(s) of the photovoltaic cells 170 are not exceed the 200-500 LA for several nanoseconds which is
necessarily the same. Thus, an attacker may not know where 10 Sufficient to erase/reset each bit of a phase change memory).
to avoid photovoltaic cells going from chip to chip, increasing In addition, electron beams from a scanning electron micro
the difficulty of an attacker's task many-fold. Scope (SEM), X-ray, and focused ion beam will generate
Furthermore, in Some embodiments the composition or Substantial current, based on the electron beam induced cur
material(s) used for photovoltaic cells 170 may be chosen rent (EBIC) effect. Therefore, photovoltaic cells can respond
based on their potential effectiveness to correspond to tam 15 effectively to a wide range of imaging techniques deployed in
pering from techniques employing radiation of different tampering. Furthermore photocurrent generation is almost
wavelengths. Notably, tamper techniques utilize a wide range instantaneous which is particularly advantageous since cur
of incident radiation for imaging, which can vary from ultra rent generation has to occur before an attacker has time to
violet (UV) visible to near-infrared (IR) (see Table 1). Thus, disable any anti-tamper elements.
including multiple photovoltaic cells 170 with various mate In some embodiments, device 100 also includes an anti
rials can provide a way to detect probing at different wave fuse, or arming switch (AS) 190 that may be situated in an
lengths. For example, a first photovoltaic cell 170 may com electrical path (e.g., in a trace 140 and/or via 150) between the
prise a particular material (such as amorphous silicon, photovoltaic cells 170 and the non-volatile memory 120 and/
crystalline silicon, silicon germanium, germanium, indium or the reactive material 180. As described herein, the term
gallium arsenide, indium arsenide or other material) while a 25 anti-fuse encompasses a class of devices that is intended to
second photovoltaic cell 170 may comprise a second, differ prevent a flow of current when armed, or when in an activated
ent material (e.g., selected from the same group). Each of state, and to allow a flow of current when disarmed, or placed
these two materials may therefore have different quantum in a deactivated State. In other words, an anti-fuse essentially
efficiencies at the same wavelength of incident radiation and operates in the reverse of a typical fuse which allows a flow of
provide a different response to one or more probing tech 30 current until the fuse breaks (e.g., by an over-current or over
niques. For example, one material may generate a strong voltage) and the flow of current is prevented. One particular
current in response to irradiation by a laser at a particular application of an anti-fuse is as an arming switch, which is
wavelength, whereas the second material generates a weaker designed to prevent a flow of current until a deactivation or
response to the same laser wavelength, but may show a strong disarming signal, is received. However, it should be under
response to X-rays. 35 stood that an aiming Switch is only one embodiment of an
Alternatively, or in addition, one or more dimensions, anti-fuse according to the present disclosure, which may have
dopant concentrations, or other properties may be varied other applications. Such as for use in a field programmable
between at least two photovoltaic cells 170 included in device gate array. Specifically, in one embodiment the arming Switch
100, which also results in different wavelength responses to 190 may comprise an anti-fuse that prevents current flow
the stimuli of various probing techniques. For example, tun 40 from the photovoltaic cells 170 to the reactive material 180
ing the absorption of a photovoltaic cell 170 can be achieved during the fabrication of the device 100. Since the photovol
by involving proper materials engineering (e.g., varying the taic cells 170 may be exposed to light until they are com
absorption coefficient and/or band gap). Similarly, decreas pletely sealed off within the interconnect structure, the anti
ing the size of a cell generally increases efficiency. For fuse/arming switch 190 may sufficiently prevent any
instance, an approximately 16 mA/cm (milliampere per 45 unintentional current from flowing from one or more of the
square centimeter) photocurrent has been observed for an photovoltaic cells 170. A one-time irreversible deactivation
approximately 1.2 mm (square millimeter) amorphous sili step converts a particular material in the anti-fuse from a high
con photovoltaic cell, demonstrating that photocurrent at resistance to a low resistance State, enabling current flow if
Small dimensions can be substantial. In any case, the inclu the chip structure is exposed to radiation again during tam
sion of photovoltaic cells 170 having various responses to 50 pering. Exemplary anti-fuses, arming Switches, and materials
stimuli of various wavelengths addresses circumstances that may be used in Such devices, are discussed in further
where it is unknown which particular probing technique(s) an detail below in connection with FIG. 4.
attacker will use. By including at least a first photovoltaic cell FIG. 2 illustrates an exemplary phase change memory cell
170 that is strongly reactive to a particular first probing tech 200 according to various embodiments of the present disclo
nique and at least a second photovoltaic cell 170 that is more 55 sure. For example, the top of FIG. 2 shows the phase change
strongly reactive to a second, different probing technique, the memory cell 200 in a “set' state, while the bottom of FIG.2
device 100 is more robust and stands a greater chance of shows the same phase change memory cell 200 in the “reset'
detecting and preventing an attack using a random probing state. The exemplary phase change memory cell 200 includes
technique, or a multi-faceted attack using several different a top electrode 210, a bottom electrode 240 and a lower
probing techniques. 60 electrode 250, each of which may comprise titanium nitride
The incident radiation of typical tampering/probing tech (TiN) or other suitable materials, as are known to those skilled
niques can be significant. If a photovoltaic cell. Such as a in the art. The phase change memory cell 200 further includes
photovoltaic cell 170, is exposed to microscope light during an insulator 230 and a phase change material 220 which can
delayering, input estimates are about 30 to 60 mA/cm with a change phase from polycrystalline (e.g., the “set state) to
(photocurrent density, which depends on quantum efficiency) 65 amorphous (e.g., the “reset' state) as well as take one or more
of 10-15 mA/cm for Si and Ji 20 mA/cm for Ge. Lasers intermediate states. For example, the “set and “reset' states
are known to generate laser beam induced current (LBIC) on may be achieved using single pulses, whereas two interme
 US 8,860,176 B2
7 8
diate levels may be programmed using iterative write-and and/or other metallic structures. As shown in FIG.3, the stack
Verify steps. Each programming pulse is a box-type rectan 300 includes an aluminum layer 310 sandwiched between
gular pulse. The “reset' pulse may comprise a high current, two nickel layers 320. Advantageously, the reactive material
while the “set pulse may comprise a trapezoidal pulse of 300 stores energy on-chip that is benign during normal chip
long trailing edge that permits Sufficient crystallization. 5 operations, but which can be triggered by a low current pulse.
The phase change material 220 may comprise a chalco This is contrary to traditional tamper schemes with on-chip
genide glass or other material which changes crystallographic batteries requiring a constant power since the tamper detec
phase when exposed to a laser. For example, a chalcogenide tion and response circuitry has to be kept operational through
glass may exhibit wide resistance ranges between crystalline out the lifetime of the die. In addition, current based ignition
and amorphous states. In general, a chalcogenide includes 10 is potentially only needed on a single site/contact of the
one or more elements from group 16 of the periodic table, reactive material 300. In particular, a reaction self-propagates
Such as Sulfur, selenium, or tellurium. Thus, in various in free standing foils and similarly will Sustain a self-propa
embodiments, one or more of the gates 110 may be comprised gating reaction front on the chip. Furthermore, if the heat loss
of doped GeSbTes, ASS, ASS, and various other phase away from the reactive material 300 to the surrounding chip
change materials. 15 environment quenches the reaction, bit erasure can still be
While some embodiments of the present disclosure may accomplished by exothermic reaction in reactive material
employ other types of non-volatile memory, phase change regions exposed to current flows. The current to drive the
memory has particular advantages which make it a Suitable reaction without a self Sustaining reaction front is still lower
choice for use in a secure device according to the present the current required for direct bit erasure. For example, igni
disclosure. More specifically, from a physical anti-tamper tion current may be substantially lower than that required to
perspective phase change memory does not give off any elec directly reset the non-volatile memory (e.g., nano-amperes
tromagnetic signature. Therefore, reading out the memory Versus micro-amperes).
states can only be accomplished by direct probing and imag In various embodiments, the ignition temperature and heat
ing, which requires physical access to the phase change of reaction are tuned/adjusted to requirements of the particu
memory. Once a reactive material has ignited and melted the 25 lar manufacturing environment. In particular, the reactive
phase change memory, there is no way to read out the bits material 300 must be inert during processing and survive
since the physical attributes of the material have been normal chip operation and stress tests, but be sensitive enough
changed. This is different from SRAM and other technolo to ignite during tampering and provide Sufficient heat to
gies, where it is possible to read out the last state due to destroy or erase non-volatile memory cells. It has been
imprinting, even after the chip power is turned off. On the 30 shown, for example, that in a titanium/amorphous-silicon
other hand, metal oxide semiconductor based memory cells stack, with a bilayer spacing of 75 nm deposited on 1 um of
may be advantageous in some application because metals, silicon oxide on silicon, the reaction quenches when the reac
Such as aluminum (which may be used in exemplary reactive tive material thickness is less than 2.25 um. Thus, in some
materials), cause significant reactions with dielectrics such as embodiments the potential for reaction quenching is taken
silicon dioxide, silicon nitride, and high-K gate dielectrics, 35 into account in providing a reactive material 300 that gener
reacting with oxygen and forming stable oxides. Thus, there ates a sufficient reaction front that will not be quenched prior
is significant potential for extensive gate/memory cell to destroying the non-volatile memory. In some cases, the
destruction when such materials are used. ignition threshold and heat of the reaction is varied by chang
FIG. 3 illustrates an exemplary reactive material 300, ing of the chemistry, Stoichiometry, and microstructure (grain
according to various embodiments of the present disclosure. 40 structure and line spacing in thin films comprising the stack of
In some embodiments, reactive material 300 is included in an reactive material 300). For instance, the number of layers, the
integrated circuit (e.g., device 100) which provides a way to spacing between layers, the width of the layers and the com
store the required amount of energy for irreversible erasure of ponent metals in the stack of reactive material 300, can all be
memory cells on the chip through an exothermic reaction. In varied, resulting in different ignition fluences (current densi
particular, in many cases the radiation of a given tamper event 45 ties required for ignition), different reaction heats, etc. In
may be insufficient to generate a large enough current pulse Some embodiments, the ignition current density can also be
from one or more integrated photovoltaic cells to directly varied via lithography, Such as by varying of the size of the
alter, e.g., erase or destroy, the non-volatile memory, whereas electrical contacts/vias connected to the stack of reactive
the reactive material 300 may have a steep chemical gradient material 300. For example, a connection from a first photo
and require only an ultra low trigger current to release the 50 voltaic cell may be fabricated with electrical contacts having
energy. In one embodiment, the exothermic reaction irrevers a different cross-sectional area than electrical contacts for a
ibly destroys all or a portion of a non-volatile memory (e.g., connection from a second photovoltaic cell. Accordingly, the
one or more gates 110 of non-volatile memory 120 in FIG.1), current densities delivered from the first and second photo
providing unmistakable evidence of tampering. In one voltaic cells may be different from one another despite, for
embodiment, the reactive material is deposited in at least one 55 example, the first and second photovoltaic cells being other
continuous layer adjacent to the non-volatile memory or Suf wise the same and receiving the same incident radiation.
ficiently close to alter the non-volatile memory, e.g., to Similarly, in embodiments employing oxide systems, such
change the memory state of the non-volatile memory or to oxides can be made porous by producing nanoparticles of
damage or destroy it such that it is no longer useable as a different sizes. Likewise, the potential for reaction quenching
memory. 60 can be reduced by fabricating specific patterns and geom
As illustrated in FIG. 3, reactive material 300 comprises a etries for the reactive material 300, or one or more layers
thin metal film stack of several metallic layers where w is the thereof, through lithography, undercutting, chemical
interlayer spacing and 20 is the bilayer thickness or spacing mechanical planarization, and other similar techniques, in
(which is also sometimes referred to as ). For example, the order to promote self-propagation by reducing heat loss. For
reactive material 300 comprises one or more specific metals 65 example, a multilayer, Such as nickel-aluminum Ni/Al, can be
Such as copper, copper oxide, aluminum, nickel, hafnium grown by sputtering and evaporation. In any case, when the
oxide, silicon, boron, titanium, cobalt, palladium, platinum, reactive material 300 is triggered by a current pulse, the stack
 US 8,860,176 B2
10
of reactive material 300 reacts by spontaneous mixing to Ni--Al), but can produce heat greater than 600°C. up to more
release a large quantity of heat through an exothermic reac than approximately 2800° C. Given that a phase change
tion, without any pressure waves or gaseous byproducts. memory's amorphous state can be made crystalline at tem
In one embodiment, nickel/aluminum multilayers are used peratures of approximately 400° C. (for an approximately
for the stack of reactive material 300, since such a reactive 100 ns pulse), and that there are typically greater than 1000
material can be ignited using a short, low-current electrical PCM cells on a chip, the energy to ignite a reactive material is
pulse. For example, a bilayer spacing w is frequently used to far less that that required to resistively heat each cell individu
characterize the microstructure of a multilayer reactive mate ally.
rial. For Ni/A1 multilayers, the bilayer spacing w is defined as In addition, in various embodiments an exothermic reac
the thickness of one layer of nickel and one layer of aluminum 10 tion of the reactive material is triggered by a current from a
(e.g., layer 310 and bottom layer 320 in FIG. 3). As one photovoltaic cell. However, in various other, further and dif
example, assuming a Ni/A1 multilayer with a density of 5.09 ferent embodiments, such an exothermic reaction can be trig
glee, a heat capacity of 0.588J/g/K, a resistivity of 1.3x10 gered by a number of other mechanisms. For example, the
S2-cm and a 51 nm bilayer spacing, the ignition temperature is reactive material may also be ignited by a mechanical impact,
177°C. In addition, assuming that 50 nm electrodes are used 15 sectioning of the chip, a direct energy source (such as radia
to Supply an ignition current, a 100 ns 1.5 p.A pulse is suffi tion from a laser or X-ray, a focused ion beam, etc.), a direct
cient, assuming a lossless environment. However, estimating thermal heating, a current from another source. Such as
80% heat loss, an approximately 3.3 p.A pulse of 100 ns will another type of tampering detector (e.g., a wire mesh Sur
ignite the Ni/Al(since electrical energy scales as the square of rounding the chip, and others). In one embodiment, the reac
the current). Notably, the reaction of the reactive material to tive material is ignited by a current directed to the reactive
various currents of various durations can be tuned by chang material by a Software program. For example, the reactive
ing the film thickness, bilayer spacing and chemistry, as well material may be incorporated in an integrated circuit of a
as through lithographic variation of the contact area to the computer. A Software program running on the computer may
reactive material structure, which will vary the current den be configured to cause an electrical signal to be sent to the
S1ty. 25 reactive material if a number of incorrect password login
In addition to Ni--Al multilayers, suitable reactive material attempts exceeds a threshold, thereby triggering a reaction.
components and combinations include: Si-2B, Cu+Pd, Various embodiments described herein relate to the use of
Al-Ti, Si-Co, Ni--Ti, Co--Al, Al--Pt, and combination of the reactive materials in conjunction with phase change memory.
foregoing as well as Al-Ni, halfnium oxide, copper, copper Depending upon the configuration of reactive material (e.g.,
oxide and various other metal and/or metal oxide material 30 component metal(s)/materials, dimensions, size of contact
platforms already used in metal oxide semiconductor manu areas, anticipated tampering techniques, and hence expected
facturing. It should be noted that the foregoing is provided by ignition currents, etc.), the phase change memory (PCM) can
way of example only and not limitation. Thus, numerous be tuned for optimal use with the reactive material. For
other, further and different combinations of component mate example, the doping level can be varied to change the PCM
rials may be incorporated into a multilayer reactive material 35 sensitivity to the heat of reaction of the reactive material.
in accordance with various embodiments of the present dis In some embodiments, a reactive material is used in con
closure. Some exemplary reactive materials that may be used junction with CMOS based memory technology. For
in embodiments of the present disclosure are described in “A example, reactive materials may generate heat greater than
Survey of Combustible Metals. Thermites, and Intermettalics approximately 1300° C., which is sufficient to cause device
for Pyrotechnic Applications', by S. H. Fischer and M. C. 40 damage through reactions with dielectrics such as silicon
Grubelich, Sandia National Laboratories, 32" AIAA/ oxide, silicon nitride and high-k/metal gate dielectrics. For
ASME/SAE/ASEE Joint Propulsion Conference, Lake instance, metals such as aluminum strongly react with oxygen
Buena Vista, Fla., 1996, which is incorporated by reference to form stable oxides. In one embodiment, a reactive material
herein in its entirety. In this regard, it should be noted that is integrated between the N and P wells of a CMOS gate. As
although some embodiments describe a reactive material that 45 Such, the heat from a reaction in the reactive material causes
comprises a multi-layer stack, the present disclosure is not so a short due to the destruction of the gate dielectric, causing the
limited. Namely, in other, further and different embodiments, circuit element to discharge and thereby irreversibly erasing
the reactive material may comprise a single layer or region of the state of the memory bit.
a single metal or other material, or may comprise a different FIG. 4 illustrates an exemplary anti-fuse 400 according to
mechanism for generating heat, such as a thermite mixture, a 50 various embodiments of the present disclosure. In particular,
metal fuel (e.g., a metal oxidation reaction), an intermetallic the left side of FIG. 4 illustrates the anti-fuse 400 in a high
arrangement other than a multi-layer stack, and the like. In resistance or “activated state and the right side of FIG. 4
other words, some embodiments may feature an intermetallic illustrates the anti-fuse 400 in a low-resistance, or "de-acti
reaction whereas other embodiments may rely upon an exo vated State. In one embodiment, the anti-fuse comprises an
thermic reduction-oxidation reaction, or other mechanism to 55 arming Switch. For instance. Such an anti-fuse deployed as an
generate heat. arming Switch may be placed in an activated State between a
Reactions in Such materials can be ignited by ignition photovoltaic cell and a region of reactive material. The acti
fluencies in the range of, for example, 0.5-5 J/cm, for an vated state prevents current flow via an electrical path 460
approximately 100 um spot size, or 5-900 J/cm, for an from the photovoltaic cell to the region of reactive material
approximately 10um spot size (the size of electrical contacts 60 and/or to at least one memory cell during fabrication of an
delivering an ignition current). Typical interlayer/bilayer integrated circuit/die. For example, as shown in FIG. 1, anti
spacing is from approximately 2 nm to 200 nm. Reactive fuse 190 (e.g., an arming Switch) is situated in an electrical
materials such as the above can produce heats of reaction path between, and is coupled to both the photovoltaic cells
ranging from approximately 150 calories per cubic centime 170 and reactive material 180 (e.g., by way of vias 140 and/or
ter (cal/cc) to approximately 2500 cal/cc or more. Exemplary 65 traces 150). Once the integrated circuit/die is finished, a one
multilayer reactive materials have been show to ignite at time deactivation is performed to convert a material in the
temperatures below 300° C. under certain conditions (e.g., anti-fuse 190 having a high resistance to a low resistance state
 US 8,860,176 B2
11 12
by an irreversible reaction thereby allowing a current to flow ties are not evenly distributed throughout the substrate 420.
through the material in the low resistance State. For instance, a greater level of dopants/impurities may be
As illustrated in FIG. 4, the exemplary anti-fuse 400 contained in parts of the substrate 420 that are nearer to the
includes a Substrate 420, e.g., patterned or unpatterned amor reactive material 410 and less or no dopants/impurities may
phous silicon, which may be doped or undoped, or polycrys be contained in parts of the substrate that are further away
talline or crystalline silicon (monocrystal), Surrounded by an from the reactive material. Alternatively, or in addition, the
insulator? dielectric 430. The anti-fuse 400 also includes a reaction of the reactive material 410 can induce silicide for
reactive material 410 atop a thin layer 440. The layer 440 may mation, which also leads to a change in resistance. For
comprise the same material as insulator/dielectric 430. For example, one or more metals from the reactive material 410
example, layer 440 may comprise a dielectric layer. In one 10
may combine with the Substrate 420 (e.g., amorphous silicon
embodiment, the layer 440 comprises a non-metal Such as at or crystalline/polycrystalline silicon) to form a conductive
least one of silicon oxide (SiO), silicon nitride (SiN.), alu silicide layer 480. As such, the substrate in low resistance
minum oxide (Al2O), hafnium oxide (H?O), titanium diox state 490 may comprise a silicide layer 480. In still another
ide (TiO), lanthanum aluminum oxide (LaAlO) or other embodiment, the reaction of the reactive material 410 com
metal oxide, or a combination thereof. In various embodi 15
ments, the layer 440 is thin enough to be consumed during a prises one or more metals of the reactive material 410 mixing
reaction of the reactive material 410, but provides sufficient with or diffusing into the substrate 420 to form a conductive
electrical insulation from the reactive material 410 to the high silicon layer 490 with metallic impurities. In one embodi
resistance material (i.e., the Substrate 420) before triggering ment, the layer 440 is consumed as part of the reaction
the reaction, since current could otherwise flow through anti between the reactive material/metal and the silicon substrate
fuse 400. For example, when anti-fuse 400 is used as an 420. In one embodiment, the layer 440 acts as a diffusion
arming Switch (e.g., between a photovoltaic cell and a region barrier which, at Some minimum threshold temperature,
of reactive material) any current flowing from the photovol allows metal from the reactive material 410 to pass through.
taic cell to the region of reactive material could cause the Alternatively, or in addition, in one embodiment, the layer
erasure of any connected non-volatile memory cell(s). 25 440 may also facilitate the mixing process between the reac
Accordingly, in some embodiments the insulating properties tive material/metal and the silicon substrate 420.
of such layer may be of lesser importance than its ability to Although FIG. 4 illustrates only a single region of reactive
facilitate an intermixing between a metal of the reactive mate material 410 on one side of the substrate 420, in other
rial and the silicon substrate 420. embodiments multiple regions of reactive material may be
In one embodiment, the reactive material 410 takes the 30 used in a single anti-fuse. For example, a second region of
form of the exemplary reactive material 300 described above. reactive material may be placed under the amorphous silicon
In one embodiment, the anti-fuse 400 is directly connected to substrate 420 as illustrated in FIG. 4. Alternatively or in
a dedicated external connection 470 (such as a C4 solder addition, one or more other regions of reactive material may
bump) which provides away to directa one-time deactivation be placed around the amorphous silicon substrate 420 in
signal to the anti-fuse 400. For example, an electrical current 35 various orientations (e.g., to the left and the right). In addition,
may be applied to the reactive material 410 causing an exo one or more further layers of thin insulators/dielectrics may
thermic reaction in the reactive material 410 (e.g., an inter be situated between the additional regions of reactive material
metallic reaction, an exothermic reduction-oxidation reac and the substrate 420. Likewise, one or more additional dedi
tion, or the like), which in turn causes the substrate 420 cated external connections may be provided to allow delivery
(and/or the insulating layer 440) to change from a high resis 40 of an electrical flow or current to the one or more additional
tance state to a low resistance state. In particular, the right side regions of reactive material. Further, although FIG. 4 appears
of FIG. 4 illustrates the anti-fuse 400, including the byprod to illustrate an anti-fuse 400 in a horizontal orientation, the
ucts of the reaction of the reactive material 410, as well as the present disclosure is not so limited. In other words, the anti
substrate in low resistance state 490. For example, where the fuse may have any orientation within and with respect to the
Substrate comprises amorphous silicon, the heat from the 45 integrated circuit and may be fabricated within or as part of
reactive material 410 affects the crystallization of the amor any one or more layers if the integrated circuit.
phous silicon 420 leading to a change or transition from high Notably, to directly cause a state change in the Substrate
resistance 420 to low resistance 490. In other words, in one 420 via an electrical current, a relatively high current is
embodiment, the heat of the reaction causes crystallization of required. Advantageously, using embodiments of the present
the amorphous silicon. In one embodiment, the substrate 420 50 disclosure a relatively low current delivered to the reactive
comprises doped amorphous silicon. For example, in one material can generate a high heat Sufficient to cause a state
embodiment the amorphous silicon substrate 420 is doped change in the Substrate 420 avoiding the need for a large direct
with one or more group IV (also referred to as group 14) current to alter the substrate 420. Thus, novel anti-fuses/
elements, such as germanium or carbon, or a combination arming switches are described herein where the reactive
thereof. Alternatively, or in addition, in one embodiment the 55 material 410 acts as a low power heater for delivering the
silicon Substrate comprises additional impurities such as required energy for crystallization of the amorphous silicon
potassium (P), boron (B), arsenic (AS), or a combination substrate 420. However, in accordance with one embodiment
thereof, or hydrogen, helium, deuterium, or a combination of the present disclosure a system may nevertheless comprise
thereof, and the like. a photovoltaic cell and/or a region of reactive material
In one embodiment, the substrate 420 comprises amor 60 coupled via an electrical path having an arming Switch that is
phous silicon doped with one or more impurity metals. Such deactivated conventionally, e.g., by an electrical current
as aluminum (Al), nickel (Ni), copper (Cu) or a combination applied to the substrate.
thereof, in order to lower the required energy for crystalliza FIG. 5 illustrates a flowchart of a method 500 for manu
tion through a metal induced crystallization (MIC) process. facturing an integrated circuit having a tamper response
For instance, the metallic impurities may provide one or more 65 device. In particular, exemplary steps of the method 500 may
nucleation sites for crystal formation. In one embodiment, the be performed in accordance with any one or more of the above
amorphous silicon is graded, e.g., where the dopants/impuri described embodiments.
 US 8,860,176 B2
13 14
The method 500 begins at step 502 and proceeds to step At step 540, the method 500 includes at least one anti-fuse,
510 where the method provides a substrate/die. For example, or arming Switch, between at least one photovoltaic cell and
a substrate/die may be the basis for at least one integrated the reactive material and/or one or more memory cells
circuit, each of which may comprise a front end layer of (which, in some embodiments, may be yet to be formed). For
semiconducting silicon, gallium arsenide, germanium and the 5 example, as the integrated circuit, and the backend in particu
like, along with other materials and/or combinations thereof, lar, is formed, copper or other conductive wiring may be
and having formed therein a number of transistors, gates, formed in Vias and traces connecting devices Such as gates,
nets, and the like. The integrated circuit may also comprise a transistors, and the like with one another. In some embodi
number of backend layers including a dielectric (e.g., a low-k ments, an exemplary tamper response device comprises at
dielectric) or other insulating materials, vias, traces, and wir 10 least one photovoltaic cell formed at step 520 and the reactive
ing connecting various elements in the front end to each other, material deposited at step 530. The photovoltaic cell(s) may
to ground, and to power sources, among other things. An be connected to the reactive material by this backend wiring.
exemplary integrated circuit is illustrated in FIG. 1 and However, as additional layers are added to the integrated
described above. circuit and as the manufacturing process of the integrated
At step 520, the method 500 forms at least one photovoltaic 15 circuit continues, the photovoltaic cell(s) will continue to be
cell on or in the at least one integrated circuit. For example, exposed to radiation including visible light, irradiation from
the photovoltaic cell may be formed using any number of lasers (e.g., due to laser anneal of other components), and
known techniques. For example, exemplary materials that others forms of radiation. As such, it is possible for the pho
may be used for a photovoltaic cell can be deposited using tovoltaic cell to trigger a reaction in the reactive material if
electron beam induced deposition, a focused ion beam directly connected through backend wiring, or to directly
induced deposition, Sputtering, evaporation and similar tech affect one or more memory cells of a non-volatile memory. As
niques, and may be further formed using a lithography pro Such, an anti-fuse, or arming Switch, may be included at step
cess, laser anneal, reactive ion etching, chemical mechanical 540 between the photovoltaic cell(s) and the reactive material
planarization, and other MOS processing techniques. In some and/or one or more memory cells. The arming Switch may be
embodiments, multiple photovoltaic cells are included at 25 placed in the path of a backend wiring connection between
various layers and at various locations, random or otherwise, one or more of the photovoltaic cells and the reactive material
in the backend, or front end, of the integrated circuit. As such, and/or memory cells to prevent the flow of current during
different photovoltaic cells included in the integrated circuit additional steps of manufacturing the integrated circuit.
may be formed at different times as each of the layers of the Exemplary anti-fuses, aiming Switches and suitable compo
integrated circuit is fabricated. In this regard, it should be 30 nents are described above in connection with FIGS. 1 and 4.
noted that any one or more of the steps of the method 500 may The anti-fuse, or arming Switch, may be fabricated using any
be repeated or performed in a different order thanas explicitly of the same techniques described above in connection with
depicted in FIG. 5. In some embodiments, multiple photovol steps 520 or 530, or other similar MOS fabrication tech
taic cells are formed at step 520 having different sizes, geom niques.
etries, configurations or materials/compositions, resulting in 35 At step 550, the method 500 fabricates at least one memory
different response from one another in response to various cell in the integrated circuit. The at least one memory cell can
tampering techniques (e.g., different quantum efficiencies be fabricated using any of the same techniques described
when exposed to the same wavelength radiation). above in connection with steps 520–540, or other similar
In various embodiments, a tamper response device MOS fabrication techniques. The at least one memory cell
includes a reactive material and an anti-fuse, or arming 40 may comprise one or more gates/transistors that form a non
switch, to prevent the flow of current between the at least one Volatile memory, Such as static random access memory
photovoltaic cell and the reactive material. Thus, in some formed of metal oxide semiconductors (MOS) transistors,
embodiments, following step 520 the method 500 simply high-k/metal gates, and the like, or read only memory (ROM),
proceeds to step 550. However, in some embodiments, either phase change memory (PCM), and the like.
or both of steps 530-540 of the method 500 may be performed 45 At step 560, the method 500 connects the at least one
following step 520. memory cell to the photovoltaic cell(s) and/or reactive mate
At step 530, the method 500 deposits, or forms a reactive rial. For example, electrical coupling(s) may be made
material in the integrated circuit. Exemplary reactive materi between Such components through wiring in the Vias and
als are described above in connection with FIGS. 1 and 3. As traces in the backend of the integrated circuit. Note that as the
with the photovoltaic cells formed at step 520, the reactive 50 fabrication of an entire integrated circuit generally involves a
material can be deposited and formed using electron beam layer-by-layer process, only certain portions of the wiring
induced deposition, a focused ion beam induced deposition, connections, as well as the components to be connected, may
sputtering, evaporation and similar techniques, and may be be deposited or formed in connection with each layer. As
further formed using a lithography process, laser anneal, Subsequent layers are added to the integrated circuit, addi
reactive ion etching, chemical mechanical planarization, and 55 tional portions of the wiring connections, vias, traces, gates,
other MOS processing techniques. In addition, the reactive dielectric insulators, and other components may additionally
material can be formed at a single location or multiple dis be created. Thus, it should be understood that any one or more
tributed locations, and can take various shapes, patterns and of the steps of the method 500 may be repeated (e.g., for
geometries depending upon the particular configuration of depositing/forming additional portions of an anti-fuse,
the integrated circuit. For example, the reactive material can 60 memory cell, reactive material or photovoltaic cell as each
be placed in various layers and at various locations, random or layer of the integrated circuit is manufactured) or performed
otherwise, in the backend, or front end, of the integrated in a different order than as explicitly depicted in FIG. 5.
circuit. In one embodiment, the method 500 couples the reac The photovoltaic cell(s), or the photovoltaic cell(s) in con
tive material to the at least one photovoltaic cell. For example, junction with the reactive material, comprise a tamper
the reactive material and the at least one photovoltaic cell may 65 response device for the integrated circuit. Radiation from
be electrically coupled through one or more Vias and/or tampering/probing techniques that are received at the photo
traces, and the like. Voltaic cell(s) generate a photocurrent from the photovoltaic
 US 8,860,176 B2
15 16
cell(s) to the reactive material or directly to the at least one chip Such that a heat from an exothermic reaction in the
memory cell. The direct photocurrent, or heat from an exo reactive material will cause a desired change in the state of the
thermic reaction in the reactive material erases or changes a silicon region (e.g., changing from a high resistance state to a
state of the at least one memory cell, preventing extraction of low resistance state). Thus, the reactive material and the sili
any data previously stored in the at least one memory cell. 5 con region may be touching, or may be coupled via one or
Following step 560, the method 500 may further proceed to more additional layers or other intervening regions. For
step 570. In particular, if the method 500 included an anti-fuse example, in one embodiment, the dielectric layer is situated
at step 540, the anti-fuse must then be deactivated before the between the reactive material and the silicon region. Never
tamper response device (i.e., the photovoltaic cell(s), or the theless, the reactive material and silicon region remain ther
photovoltaic cell(s) plus reactive material) is functional. In 10 mally coupled. For example, the dielectric layer is thin
one embodiment, the anti-fuse is directly connected to a enough to be consumed during a reaction of the first region of
dedicated external connection (such as a C4 Solder bump) reactive material, but provides sufficient electrical insulation
which provides away to directa one-time deactivation signal from the first region of reactive material to the dielectric
to the anti-fuse. For example, in one embodiment the heat region before triggering the reaction.
from a small reactive material in the anti-fuse affects the 15 In one embodiment, following step 630, the method 600
crystallization of a region of doped amorphous silicon lead may proceed to step 635 where the method deposits at least
ing to a phase change from high resistance to low resistance. one metal in the integrated circuit. For example, in one
The heat-generating reaction is set off by the deactivation embodiment a separate metal layer may be deposited adjacent
signal. Alternatively, or in addition, the reaction of the reac to the silicon region. In one embodiment, the at least one
tive material in the anti-fuse can induce silicide formation metal comprises nickel, aluminum, titanium, copper, plati
and/or a mixing of a metal from the reactive material in the num cobalt or tungsten. Notably, the at least one metal may
arming Switch with a silicon Substrate, which also leads to a reactor interact with the silicon region when heated by a heat
change in resistance. In any case, once the anti-fuse is placed from the reactive material to form a silicide or to otherwise
in a low resistance state, a path exists for a current to flow mix with the silicon region Such that the silicon region tran
between the photovoltaic cell(s) formed at step 520 and the 25 sitions to a low resistance state. It should also be noted that in
reactive material deposited at step 530, through wiring in the one embodiment, the at least one metal comprises part of the
vias and traces of the integrated circuit, as well as through the reactive material deposited at step 630. For example, the at
(deactivated) anti-fuse) that was placed in the pathat step 540. least one metal may comprise one of the metals that is used in
At step 595, the method 500 ends. Accordingly, the steps of a thin-metal film or other intermetallic reactive material. As
the method 500 produce a secure integrated circuit that 30 such, in some embodiments step 635 may be considered a
includes a tamper response device. sub-step of step 630.
FIG. 6 illustrates a flowchart of a method 600 for manu Following step 630 and/or step 635, the method 600 may
facturing an anti-fuse, e.g., an arming Switch, for an inte proceed to step 640 where the method includes at least one
grated circuit in accordance with the present disclosure. In electrical contact for conveying a deactivation signal to the
particular, exemplary steps of the method 600 may be per 35 anti-fuse. For example, an electrical contact such as electrical
formed in accordance with any one or more of the above contact 470 may be formed in accordance with the integrated
described embodiments. circuit manufacturing process.
The method 600 begins at step 602 and proceeds to step Following step 640, the method 600 may proceed to step
610 where the method forms a silicon region in the integrated 650 where the method deactivates the anti-fuse, or arming
circuit. For example, a silicon region, such as Substrate 420 as 40 Switch. For example, an external current from a dedicated
described above in connection with FIG.4, may be formed in connection may deliver Sufficient energy to trigger an exo
the integrated circuit. For instance, the silicon region may thermic reaction in the reactive material. In one embodiment,
comprise an amorphous silicon Substrate or crystalline/poly the external current is delivered via the at least one electrical
crystalline silicon. In one embodiment, the silicon region is contact formed at step 640. It should be noted that step 650
formed/deposited in a high resistance state. In addition, in one 45 may comprise Substantially the same process as described
embodiment, the silicon region includes one or more dopants above in connection with step 570 of the method 500. In
or other impurities such as described above in connection addition, the exothermic reaction may follow any of the above
with FIG. 4. described processes (e.g., an intermetallic reaction, an exo
Following step 610, the method 600 may proceed to step thermic reduction-oxidation reaction, etc.) and may cause the
620 where the method forms a layer over the silicon region. 50 silicon region to change from a high resistance state to a low
For example, a dielectric layer may beformed substantially as resistance State through any of the above described processes
layer 440 is shown in FIG.4, or may take a different arrange (e.g., a change from amorphous silicon to crystalline silicon
ment depending upon the location, orientation or other char and/or a metal induced crystallization process, silicide for
acteristic of the silicon region. mation, etc.).
At step 630 the method 600 deposits a reactive material in 55 At step 695 the method ends. Accordingly, the steps/opera
the integrated circuit. For example, a region of reactive mate tions/functions of the method 600 produce a secure integrated
rial may be formed in Substantially the same manner as circuit that includes an antifuse.
described above in connection with step 530 of the method Although the methods 500 and 600 have been described in
500. However, in this case the first region of reactive material connection with certain exemplary materials, in other, further
is not intended for destroying or altering a memory cell, but is 60 and different embodiments, at steps 510-550 and steps 610
for inclusion in an anti-fuse for delivering sufficient heat to 680 respectively the methods 500 and 600 may use alternative
change the silicon region from a high resistance state to a low materials suitable for use as a Substrate, photovoltaic cells,
resistance state. Further at step 630, the first region of reactive reactive materials, anti-fuses/arming Switches, memory cells,
material may be deposited Such that it is coupled to the silicon including gates, transistors and Sub-components, and other
region. For example, the reactive material may be thermally 65 components, such as wiring, backend insulating dielectrics,
coupled to the silicon region, e.g., where the reactive material and the like. In addition, it should be noted that in various
and silicon region are sufficiently close to one another on the embodiments it is not strictly necessary that each and every
 US 8,860,176 B2
17 18
step depicted in the respective methods 500 and 600 be per 7. The antifuse of claim 6, wherein the thin metal film
formed. In other words, any one or more of the steps of the comprises a plurality of layers comprising at least two differ
respective methods 500 and 600 may be deemed optional ent types of materials.
steps. Similarly, although the steps of the respective methods 8. The antifuse of claim 1, further comprising at least one
500 and 600 are listed in a particular order, as shown in FIGS. contact for delivering the first electrical current to the reactive
5 and 6, it should be noted that alternate embodiments of the material for triggering an exothermic reaction in the reactive
present disclosure may implement these steps in a different material.
order or may repeat Such steps as necessary (e.g., as different 9. The antifuse of claim 1, wherein the reactive material is
layers of the integrated circuit are formed). on only one side of the silicon region.
While various embodiments have been described above, it 10
10. The antifuse of claim 1, further comprising:
should be understood that they have been presented by way of a dielectric layer between the reactive material and the
example only, and not limitation. Thus, the breadth and scope silicon region.
of a preferred embodiment should not be limited by any of the
above-described exemplary embodiments, but should be 11. The antifuse of claim 10, wherein the dielectric layer
defined only in accordance with the following claims and 15 comprises at least one of silicon oxide, silicon nitride, alu
their equivalents. In addition, although various embodiments minum oxide, hafnium oxide, titanium dioxide, lanthanum
which incorporate the teachings of the present disclosure aluminum oxide, or other metal oxide.
have been shown and described in detail herein, those skilled 12. An antifuse comprising:
in the art can readily devise many other varied embodiments a reactive material;
that still incorporate these teachings. at least one metal; and
What is claimed is: a silicon region comprising amorphous silicon adjacent to
1. An antifuse comprising: the at least one metal and thermally coupled to the reac
a reactive material; and tive material, wherein an electrical current to the reactive
a silicon region comprising amorphous silicon and ther material causes the reactive material to release heat
mally coupled to the reactive material, wherein an elec 25 which transitions the silicon region from a high resis
trical current to the reactive material causes the reactive tance state to a low resistance state, and wherein the
material to release heat which transitions the silicon amorphous silicon is doped with at least one of:
region from a high resistance state to a low resistance deuterium or helium.
state, and wherein the amorphous silicon is doped with 13. The antifuse of claim 12, wherein the silicon region
at least one of: 30
deuterium or helium. transitions from the high resistance state to the low resistance
2. The antifuse of claim 1, wherein the amorphous silicon state by forming a silicide with the at least one metal.
contains an impurity metal comprising at least one of 14. The antifuse of claim 12, wherein the silicon region
aluminum, nickel or copper, to lower a required energy for transitions from the high resistance state to the low resistance
crystallization of the amorphous silicon through a metal 35 state by mixing with the at least one metal of the reactive
induced crystallization process. material.
3. The antifuse of claim 1, wherein a concentration of 15. The antifuse of claim 12, wherein the at least one metal
dopants or impurities within the amorphous silicon is graded. comprises at least one of:
4. The antifuse of claim 1, wherein the reactive material nickel, aluminum, titanium, copper, platinum, cobalt or
undergoes at least one of 40 tungsten.
an exothermic intermetallic reaction or an exothermic 16. The antifuse of claim 12, further comprising:
a dielectric between the reactive material and the silicon
reduction-oxidation reaction to crystallize at least part of region.
the silicon region.
5. The antifuse of claim 1, wherein the reactive material 17. The antifuse of claim 16, wherein the dielectric com
comprises at least one of nickel, aluminum, titanium, copper, 45 prises at least one of
cobalt, silicon, boron, palladium, copper oxide, silicon oxide, silicon oxide, silicon nitride or aluminum oxide.
hafnium oxide, arsenic, potassium, germanium or carbon. 18. The antifuse of claim 12, wherein the at least one metal
6. The antifuse of claim 1, wherein the reactive material is part of the reactive material.
comprises a thin metal film. k k k k k