Ultra-Low Power Analog Multiplier Based on

Translinear Principle
Mohammadhadi Danesh, Akshay Jayaraj, Sanjeev Tannirkulam Chandrasekaran, and Arindam Sanyal
Electrical Engineering, State University of New York at Buffalo, Buffalo, NY 14260, USA
Email: {mdanesh, akshayja, stannirk, arindams}@buffalo.edu

Abstract—In this paper, a wide dynamic range, current- technology process by this author for RMS-to-DC conversion
mode four-quadrant analog multiplier circuit is proposed that application [13], and it has been developed and modified to be
utilizes MOS translinear principle. The proposed multiplier is used as the main part of the multiplier circuit designed in 65nm
designed in 65nm technology using CMOS transistors operating
in weak inversion. A thorough analysis of the proposed design technology process. The proposed multiplier provides a wide
is performed using Spectre and monte-carlo simulations. The dynamic range and consumes less power than state-of-the-art
multiplier consumes a low power of 0.48µW and supports an designs. The loop architecture reduces the effect of mismatch
input range of ±200nA while operating from 0.8V supply and leading to reduced errors in the output. The hierarchical design
exhibits an average total harmonic distortion (THD) 1.12%. Post methodology, based on squarer circuit design, can be easily
layout simulation results show a high figure-of-merit (FoM) of
1302 verifying superiority of our design against other state-of- extended to circuits for other mathematical operations, such
the-art multiplier circuits. as square-root, division, geometric mean and absolute value.
The rest of this work is organized as follows: Section II
I. I NTRODUCTION presents the architecture of the proposed multiplier and pro-
While analog multipliers have been around for a long vides analysis of the squarer and multiplier circuits, simulation
time, there is a recent increase in research attention on low- results are presented in Section III. The conclusion is brought
power, low-voltage analog current-mode circuits. This research up in Section IV.
attention has been primarily driven by the need to have low
II. P ROPOSED A RCHITECTURE
power and small area analog computing systems that can be
used for machine learning or hardware security applications. A. Multiplier Architecture
Four-quadrant multiplication is a core operation that is widely The proposed multiplier block diagram is shown in Fig. 1.
used in analog signal processing applications. Four quad- As can be seen from Fig. 1, multiplication operation is done by
rant multipliers are used as modulators, frequency doublers, three squarer blocks. Iout is the output current of multiplier.
adaptive filters [1], phase detection [2], mixers [3], neural IB is DC bias current. Iin1 , Iin2 , and Iin1 + Iin2 are the
networks [4], sensor applications [5], gain controlling [6], and input currents of squarer1, squarer2 and squarer3 respectively.
fuzzy systems [7], to name a few. Basically, the first two squarer cells have two outputs that
The first four-quadrant analog multiplier is the widely I2
Iout1 1 = Iin1 and Iout2 1 = 4Iin1B
are the outputs of squarer
used glibert cell [8] which was implemented using bipolar I2
cell 1 and Iout1 2 = Iin2 and Iout2 2 = 4Iin2 are the outputs of
transistors. Since then, a noticeable number of works have B
the second squarer cell. Iout11 and Iout12 are added to form
been reported in CMOS technology. The increasing demand
the input current of the third squarer cell. Output current of
for low voltage/low-power integrated circuits has encouraged
the multiplier can be shown to be
the development of CMOS current-mode architectures. As in
2
their voltage-mode counterparts, the operating principle of Iin1 I2 (Iin1 + Iin2 )2 Iin1 Iin2
+ in2 + Iout = =⇒ Iout = (1)
most current-mode structures uses MOS drain current either 4IB 4IB 4IB 2IB
in strong inversion [9] or in weak inversion region [10], [11].
Current-mode four-quadrant analog multiplier circuits have B. Squarer Circuit
been designed from different principles such as stacked [12] In weak inversion region, MOS current can be written as
and folded MOS translinear loops (MTL) [11]. However, these follows [14]:
techniques require either additional supply voltages, which W VGS

increase power, or are sensitive to body effect. ID = ID0 exp ηVT (2)
L
This work presents a current-mode four-quadrant multiplier Vth
using MOS transistors operating in weak inversion. The pro- where ID0 = Is exp VGS , Is = 2ηµCox VT2 which is a
posed multiplier is built by using 3 squarer cells utilizing characteristic current that defines the current that leaks through
translinear loops in a cascode up-down structure which, as the transistor, VT = kT q and η > 1 (around 1 ∼ 1.5)
will be shown later, improves linearity compared to the folded and defines the effect that the gate voltage has on the drain
translinear loop architecture of [11]. The squarer cell is basi- current. Except for η, (2) is similar to the exponential IC /VBE
cally inspired by the one which was designed in 180nm CMOS relationship in a bipolar transistor. With typical values of η and

978-1-7281-0397-6/19/$31.00 ©2019 IEEE

 Accordingly, output currents will be Iout2 = I7 + I12 −
I17 , Iout1 = I6 − I9 . Based on power series approximation
2 2
and (5), x = Iin /4IB . Therefore, the above results hold for
−2IB ≤ Iin ≤ 2IB . For better approximation, x limit could
be chosen by −0.5 ≤ x ≤ 0.5. Using (6) and I17 = 2IB , it
2
can be shown that Iout2 = Iin /4IB and Iout1 = Iin . It should
be noted that n has been applied in naming the nodes in Fig. 2
due to the fact that three squarer cells are used to build the
multiplier circuit. Therefore, we use 1,2, and 3 instead of n
in the figure showing the full circuit diagram of the multiplier
(see Fig. 3).
Fig. 1. Complete circuit of the multiplier. C. Multiplier Circuit
at room temperature, ID reduces by approximately a factor of Fig. 3 shows the multiplier which is made by combining
10 for every 80mV drop in VGS . Fig. 2 shows the squarer three squarer cells (see Fig. 1). As mentioned in the previous
cell used in the proposed multiplier. In this section, for better sections, the multiplier consists of 3 squarer cells and is based
on Fig. 1. Thus, there will be 3 translinear loops consisting
of M1-M2 and M3-M4 for the first loop, M1-M2 and M5-M6
for the second loop, and finally M1-M2 and M7-M8 for the
third loop. According to Fig. 3, M3, M4, M11, output circuit1
block, and shared circuit in green make the first squarer. Also,
M5, M6, M12, output circuit2 block, and shared circuit in
green make the second squarer. Similarly, M7, M8, M13,
output circuit3 block, and shared circuit in green make the
third squarer. The currents of M11, M12, and M13 are equal
to IB which is the bias current. Iout2 1 and Iout2 2 are equal
2 2
to Iin1 /4IB and Iin2 /4IB , respectively. As the input current of
the third squarer cell is Iout1 1 +Iout1 2 = Iin1 +Iin2 , then the
2
output current of this cell will be equal to (Iin1 + Iin2 )
/4IB .
2 2
Fig. 2. The squarer cell made by the translinear loop including M1-M4 Also, Iout2 1 and Iout2 2 are added to form Iin1 + Iin2 /4IB .
Therefore, the output of the multiplier can be written as
understanding, the drain current of transistor Mm is defined Iout = Iout2 3 − Iout2 1 − Iout2 2 = Iin1 Iin2 /2IB (see Fig. 1
as Im . Since M1−M4 form a translinear loop, we can write and Fig. 3). From Fig. 1 and Fig. 3, currents Iin1 , Iin2 , and
the following equations for such a loop: Iin1 + Iin2 are the inputs of squarer cell1, squarer cell2, and
squarer cell3, respectively.
2
X 4
X
VGSi = VGSi
i=1 i=3
! !
I I
ηVT Ln W

1 + ηVT Ln W

2 =
L I
1 D0 L I
2 D0
! !
I I
ηVT Ln W

3 + ηVT Ln W

4
L I
3 D0 L I
4 D0 (3)
W W W W





Assuming that L 1 = L 4 and L 2 = L 3 , I1 .I2 =
I3 .I4 . From Fig. 2, I1 = I2 = IB and I4 = Iin + I3 . Thus,
I32 + Iin I3 − IB
2
=0 (4)

 12 Fig. 3. Complete circuit of the multiplier.

I2

1
=⇒ I3 = − Iin + IB 1 + in2 (5)
2 4IB As Iin1 + Iin2 goes to the third squarer cell, Iin1 and Iin2
should be chosen such that they meet the following criteria
Equation (5) can
 get linearized by Applying power
 series
1 1
approximation (1 + x) ≈ 1 + 2 x, −1 ≤ x ≤ 1 results in
2 | Iin1 + Iin2 |≤ 2IB (7)

1 I2 If x limit of −0.5 ≤ x ≤ 0.5 were

√ applied, then the criteria
I3 = I6 = I7 = − Iin + IB + in , (6) would follow | Iin1 + Iin2 |≤ 2 0.5IB .
2 8IB
D. Transconductance mismatch analysis
The effect of transconductance mismatch between NMOS
and PMOS transistors in the design can be modeled by
considering (2) and re-writing (3) as shown below
! !
I1 I4
ηp VT Ln W

− ηp VT Ln W

=
L 1 ID01 L 4 ID04
! ! (8)
I2 I3
ηn VT Ln W

− ηn VT Ln W


L 2 ID02 L 3 ID03
  Vthp

W

2
 I1 L 4 2ηp µp Cox VT exp
−VGS4

(η + δ) VT Ln 
 I4  Vthp
= Fig. 4. Layout of the multiplier circuit
W

2 exp −VGS1
L 1 2η µ C
p p ox TV
  Vthn

W

2
 I2 L 3 2η n µn Cox VT exp VGS3

(η − δ) VT Ln 
 I3  V

thn 
W

2 exp VGS2
L 2 2η n µn Cox VT
   
I1 I2
→ (η + δ)Ln = (η − δ)Ln
I4 I3
→ I1η+δ I3η−δ = I4η+δ I2η−δ
(9)
where ηp = η+δ and ηn = η−δ, and δ is the slope factor mis-
match between NMOS and PMOS transistors. VGS2 = VGS3
and VGS1 = VGS4 since these transistors have the same bias Fig. 5. Multiplication performance of the multiplier with the error.
current IB .
III. S IMULATION R ESULTS Table II shows variations of THD, bandwidth, and output
The multiplier circuit has been designed in 65nm CMOS
technology. The supply voltage and power dissipation are
100
0.8V and 0.48µW, respectively. Transistor aspect ratios of the Iin2=200nA
squarer cell in Fig. 2 are shown in Table I (squarer cells have Iin2=150nA
the same transistors in aspect ratio), W/L unit of transistors 50 Iin2=100nA
Output Current(nA)

Iin2=0nA
in nm/nm. To bias the devices in weak inversion region, the Iin2=50nA

bias current is set to 200nA. This current is implemented by a 0

simple two-transistor current mirror with a resistor. Post layout Iin2=-50nA
simulations have been done on the layout shown in Fig. 4. Both -50 Iin2=-100nA
Iin1 and Iin2 are between ±200nA. Fig. 5 shows the transient Iin2=-150nA
Iin2=-200nA
output current for inputs of I1 = 100 sin (2π × 100kHz · t)nA
-100
and I2 = 100 sin (2π × 10kHz · t)nA. The dotted curve shows -200 -150 -100 -50 0 50 100 150 200
Iin1(nA)
the transient error of the multiplier which is Iout minus the
ideal output. This simulation has been done in SS corner, Fig. 6. DC response of the multiplier for both inputs changes.
temperature of 85 ◦ C, and supply voltage of 0.75V.
current error across the different process corners, voltages, and
TABLE I temperature (PVT variations). Vhigh and Vlow are the supply
T RANSISTOR A SPECT R ATIOS
voltages with variations which are equal to Vsupply ×(1+0.05)
Transistor Name (W/L) and Vsupply × (1 − 0.05), respectively, and error = maxi-
M1, M4, M17 300/60 mum{(simulated output - ideal output)/(ideal output)}×100.
M2, M3 180/60 To evaluate the robustness of the multiplier against fabrication
M5-M7, M11-M15 250/60 process uncertainties, monte carlo analysis with 50 iterations is
M8-M10, M16 150/60 carried. In addition, monte carlo simulations are done for THD
and bandwidth to evaluate the robustness of the multiplier
Fig. 6 shows dc analysis of the proposed multiplier circuit circuit against random mismatches and process corners. Fig. 7
for different inputs in the range of −200nA ≤ Iin ≤ 200nA. shows the histogram of THD across different process and
 TABLE II Table III shows a comparison between this work and the
P OST LAYOUT PVT VARIATION ANALYSIS other reported current mode multipliers including transistors
working in weak inversion. For performance comparison of
THD(%) BW(MHz) Error(%)
@100KHz multiplier circuits, FOM is defined as
Temp (◦ C) -20 20 85 -20 20 85 -20 20 85 BW(MHz) · Input range(nA)
FoM = (10)
THD(%) · Power(µW )
Vhigh // SS 1.3 1.25 1.51 2.9 3.8 2.7 2.4 2.1 2.5
Vhigh // FF 1.9 1.35 1.6 3.3 3.5 3.8 2.2 2 2.4
The multiplier circuit shows better FoM than existing mul-
tipliers due to its higher dynamic range and better THD.
Vlow // SS 1.83 1.55 1.76 2.5 2.9 3.1 2.6 2.2 2.7
Another advantage of this circuit is that it can work in
Vlow // FF 1.59 1.41 1.5 2.9 3.2 3.4 2.8 2.3 2.9 scaled CMOS technologies, unlike [11] which requires a high
voltage headroom for good dynamic range. Fig. 9 shows THD
TABLE III comparison between this work and [11], THD of which is not
C OMPARISON WITH OTHER MULTIPLIER RESULTS depicted for input currents more than 100nA because its input
range is ±100nA. Based on this figure, it can be concluded
Parameters [10] [11] This work
that up-down structure can improve THD when the transistors
Process(µm) 0.18 0.18 0.065
work in weak inversion region.
Supply(V) 0.5 1.8 0.8
Input range(nA) ±0.2 ±100 ±200
Power (µW) 0.85×10−3 1.2 0.48
THD(%) 1.28@1KHz 1.37@100KHz 1.12@100KHz
BW(MHz) 1.57×10−3 8.2 3.5
FoM 0.2 500 1302

mismatch corners. The mean value and standard deviation of

THD are 1.42% and 0.33% respectively. Fig. 8 shows the
histogram of bandwidth across different process and mismatch
corners. Fig. 8 indicates the mean value and standard deviation
of the bandwidth are 3.4MHz and 0.24MHz respectively.

Fig. 9. THD (without applying PVT variations) difference between cascode

up-down multiplier (This work) and the folded one [11]

IV. C ONCLUSION
In this paper, a very low-power current mode multiplier
based on MOS translinear loops operating with the devices in
weak inversion region is presented. The proposed multiplier
has many applications for a wide range of analog signal
processing. The results obtained in Sec. III are based on
post-layout simulations. Multiplication performance of the
circuit at corner cases and Monte Carlo analysis has been
Fig. 7. Monte Carlo analysis result for THD investigated for THD, bandwidth, and output current error to
verify the circuit performance. Additionally, post layout Monte
Carlo for THD as well as bandwidth and PVT variations
analysis indicate that the proposed circuit is less dependent
on fabrication mismatches.
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