Solution: Assignment-3

Course Digital Electronics (BOE 310)

SEMESTER AIML-III Semester

1. A flip flop has 5ns delay from the time the clock edge occurs to the time when output
is complemented. What is the maximum delay in a 10 bit binary ripple counter?
What is the maximum frequency of the counter?

Ans: To determine the maximum delay and maximum frequency of a 10-bit binary ripple
counter, let’s break down the problem step by step:

Key Information:

1. Flip-flop delay: 5 ns (time for a single flip-flop to toggle).

2. Ripple counter: A 10-bit binary ripple counter has 10 flip-flops connected in series.

3. Maximum delay in a ripple counter: Delay accumulates through all flip-flops

because the output of one flip-flop serves as the clock input to the next flip-flop.

(a) Maximum Delay:

In a ripple counter, the output of each flip-flop depends on the toggling of the previous flip-
flop. For n flip-flops, the total delay is:

Total Delay = n × Delay per Flip-Flop.

Here: Total Delay = 10 × 5 ns = 50 ns.

(b) Maximum Frequency:

The maximum frequency (fmax) is determined by the time it takes for the entire ripple counter
to complete its operation, which is the total delay. Frequency is the reciprocal of the time
period:

fmax = 1/Total Delay.

Substitute the total delay:

fmax = 1/50 ns=1/50×10−9 = 20 MHz.

Final Answers:

1. Maximum Delay: 50 ns.

2. Maximum Frequency: 20 MHz.

2. Define Critical and Non Critical Race with example.
Ans: Explained in notes- Chapter 4: Section 4.3

3. Design a 3 bit UP/ DOWN counter using J K flip flop.

Ans: Explained in notes- Chapter 3: Section 3.11- Example 1.

4. Differentiate Asynchronous and Synchronous circuits.

Ans:

Difference Between Asynchronous and Synchronous Circuits

Aspect Asynchronous Circuits Synchronous Circuits

Clock Do not use a clock signal for

Operate using a global clock signal.
Dependency operation.

Signal Transitions occur immediately upon Transitions occur only on clock

Transition input changes. edges (rising/falling).

Faster because operations are not Slower due to clock

Speed
limited by a clock. synchronization.

More complex due to the need to

Design Easier to design as all components
handle race conditions and timing
Complexity are synchronized by the clock.
issues.

Power Potentially lower as circuits are active Higher due to continuous clock
Consumption only when inputs change. operation.

Example Ripple counters, handshaking systems, Shift registers, synchronous

Circuits event-driven logic. counters, memory systems.

Less reliable due to race conditions More reliable due to controlled

Reliability
and hazards. timing.

Depends on the delays of individual

Timing Control Depends on the global clock signal.
components.

Used in small-scale systems or where Used in large-scale and complex

Applications
speed is critical. systems like CPUs.
Key Points to Remember

• Asynchronous Circuits are faster but harder to design and debug.

• Synchronous Circuits are slower but more predictable and easier to implement.

5. Explain the use of clock in digital circuits. Also explain the type of triggering.
Ans: Use of Clock in Digital Circuits: The clock is an essential component in digital circuits,
serving as a timing reference for the sequential operation of digital systems. Its primary
functions include:

1. Synchronization:
The clock signal ensures all parts of the circuit operate in sync, providing a unified
time reference for sequential events.
2. Control of Data Flow:
The clock determines when data should be read, written, or moved within a circuit,
ensuring proper coordination between different components.
3. State Transitions:
Sequential circuits, such as flip-flops and counters, change their state based on the
clock signal.
4. Timing Signal:
The clock helps establish regular intervals for operations, crucial for tasks like
sampling in analog-to-digital converters (ADCs).

Types of Triggering in Digital Circuits: Triggering determines how a circuit reacts to the
clock signal. The two common types are:
1. Edge Triggering: Edge triggering occurs at the transition or “edge” of the clock signal. It
ensures that the circuit reacts only at a specific moment, either when the clock signal:

• Rises (Positive Edge): Triggering occurs when the clock transitions from LOW to
HIGH.
• Falls (Negative Edge): Triggering occurs when the clock transitions from HIGH to
LOW.

Example: Flip-flops (e.g., D flip-flop) use edge triggering to change states.

2. Level Triggering: Level triggering responds to the clock signal’s level (HIGH or LOW)
rather than its transition. It can be:

• High-Level Triggering: The circuit is active as long as the clock is HIGH.

• Low-Level Triggering: The circuit is active as long as the clock is LOW.

Example: Latches (e.g., SR latch) are typically level-triggered.

Importance of Triggering in Design

• Prevents Race Conditions: Proper triggering avoids errors due to overlapping

signals.
 • Accuracy in Sequential Circuits: Ensures state changes occur only at designated
times.
• Stable Data Processing: Supports reliable data transfer between circuit components.

By selecting the appropriate clock and triggering type, digital circuits achieve precision and
reliability in complex systems like processors, memory, and communication devices.

6. Elaborate the characteristic equation and excitation table of S R and J K flip flop.
Ans: Explained in notes- Chapter 3 at Section 3.2 and Section 3.4

7. Explain the working and circuit of a modulo-5 counter using gates.

Ans: Explained in notes- Chapter 3 at Section 3.11-Example 2 for modulo 6 counter using JK
FF. For Modulo 5; do same process but consider count 0-1-2-3-4 only.
8. Explain positive edge triggered T-flip-flop with the help of circuit diagram and
waveforms.
Ans: T-flip-flop is explained in notes- Chapter 3 at Section 3.5

T Flip-Flop

The toggle, or T, flip-flop is a two-input flip-flop. The inputs are the toggle (T) input and a
clock (CLK) input. If the toggle input is HIGH, the T flip-flop changes state (toggles) when
the clock signal is applied. If the toggle input is LOW, the T flip-flop holds the previous state.

T flip-flop symbol.
The standard symbol for a T flip-flop is illustrated in the figure above. The clock input may
be preceded by an inverter. An inverter indicates a flip-flop will toggle on a HIGH-to-LOW
transition of the clock pulse. The absence of an inverter indicates the flip-flop will toggle on a
LOW-to-HIGH transition of the pulse.

Now, follow the explanation of the circuit using the truth table and the timing diagram shown
in the figure above. The timing diagram shows the inputs and the resulting outputs. We will
assume an initial condition (t0) of Q being LOW and Q being HIGH. At t1, when the clock
changes from a LOW to a HIGH, the outputs remain the same as the T input is LOW. The T
input goes HIGH at t2. At t3, the clock changes from a LOW to a HIGH and the device
changes state; Q goes HIGH and Q goes LOW. The outputs remain the same at t4 since the
device is switched only by a LOW-to-HIGH transition. At t5, when the clock goes HIGH, Q
goes LOW and Q goes HIGH; they remain that way until t7.

Between t3 and t7, two complete cycles of CLK occur. During the same time period, only
one cycle is observed for Q or Q. Since the output frequency is one-half the clock (input)
frequency, this device can be used to divide the input frequency by 2.

The most commonly used T flip-flops are J-K flip-flops wired to perform a toggle function.
This use will be demonstrated later in this section.