Q1.

Find the truth table for figure ( a), figure ( b), figure ( c), figure ( d), figure ( e), and
figure ( f)
A A

B
B

Y Y

figure -(a) figure -(b)

A A

B B

Y Y
C

D
figure -(c) figure -(d)

RS
A

Y
B TO Y

B
figure -(e) figure -(f)
Q2. Draw the logic circuit for which Boolean equation is Y  ABC  ABC
EN

Q3. Find the output for the inputs shown in figure-I and figure-II for NAND –gate and OR-
Gate
Input A Input A
M

Input B
Input B
E

Figure-I
Figure- II

Q4.
IT

B Y (output)
EL

The inputs (A, B, C) to the logical circuit above are given electrical pulses as shown
below:
 A time

C
The output Y is :

(A) (B)

(C) (D)

RS
Q5. Which of the following circuits correctly represents the A B C
following truth table?
0 0 0
0 1 0
TO 1 0 1
1 1 0
(A) (B) A
B
EN

A C
C
B
(C) A (D) A
B B C
C
M

Q6. The truth table for the circuit A

shown in the figure is
B
E

Y
IT

(A) A B Y (B) A B Y
1 1 1 1 1 0
EL

0 1 0 0 0 1
1 0 0 1 0 0
0 0 1 0 1 1

(C) A B Y (D) A B Y
1 1 0 1 1 1
0 1 0 0 1 1
1 0 0 1 0 1
0 0 0 0 0 1
Q7. Refer to the arrangement of logic gates. A
For A = 0, B = 0 and A = 1, B = 0, the B
values of output Y are, respectively. Y
(A) 0 and 1
(B) 1 and 0
(C) 1 and 1
(D) 0 and 0

Q8. Truth table for the given circuit in the figure A C

B D

A B E A B E
0 0 1 0 0 1
0 1 0 0 1 0

RS
(A) (B)
1 0 1 1 0 0
1 1 0 1 1 1

A B E A B E
0 0 0
TO 0 0 0
(C) 0 1 1 (D) 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0
EN

Q9. In the circuit below, A and B represent two

inputs and C represents the output. A
The circuit represents
( A) NOR gate C
M

( B) AND gate
( C) NAND gate B
( D) OR gate
(2008)
E

Q10. The combination of gates shown below

yields
IT

( A) OR gate ( B) NOT gate

( C) XOR gate ( D) NAND gate
(2010)
This comes out to be truth table of OR gate
EL

Q11. The output of an OR gate is connected to both the inputs of a NAND gate. The
combination will serve as a: (2012)
( A) AND gate ( B) OR gate ( C) NOT gate ( D) NOR gate
Q12. Which of the following circuits correctly represents the following A B C
truth table?
0 0 0
0 1 0
1 0 1
1 1 0
(2013)
( A) ( B) A
B
A C
C
B
( C) A ( D) A

B B C
C

Q13. Consider two npn transistors as shown in 5V

figure. If 0 volts corresponds to false and 5
volts correspond to true then the output at C C
correspond to true then the output at C

RS
1
corresponds to A
( A) A NAND B
( B) A OR B
2
( C) A and B TO
( D) A NOR B B

(2013)
Q14. If a, b, c, d are inputs to a gate and x is its output, then, as per the following time graph,
EN

the gate is : (2016)

d
c
M

b
a
x
( A) AND ( B) OR ( C) NAND ( D) NOT
E
IT
EL